VCVTDQ2PS (YMM, YMM) - Throughput and Uops (IACA 3.0)
With different registers for different operands
With 1 independent instruction
Throughput Analysis Report
--------------------------
Block Throughput: 0.49 Cycles Throughput Bottleneck: Dependency chains
Loop Count: 56
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
--------------------------------------------------------------------------------------------------
| Cycles | 0.5 0.0 | 0.5 | 0.0 0.0 | 0.0 0.0 | 0.0 | 0.0 | 0.0 | 0.0 |
--------------------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
-----------------------------------------------------------------------------------------
| 1 | 0.5 | 0.5 | | | | | | | vcvtdq2ps ymm0, ymm1
Total Num Of Uops: 1
With 12 independent instructions
Throughput Analysis Report
--------------------------
Block Throughput: 5.95 Cycles Throughput Bottleneck: Backend
Loop Count: 22
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
--------------------------------------------------------------------------------------------------
| Cycles | 6.0 0.0 | 6.0 | 0.0 0.0 | 0.0 0.0 | 0.0 | 0.0 | 0.0 | 0.0 |
--------------------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
-----------------------------------------------------------------------------------------
| 1 | 1.0 | | | | | | | | vcvtdq2ps ymm0, ymm1
| 1 | | 1.0 | | | | | | | vcvtdq2ps ymm2, ymm1
| 1 | 1.0 | | | | | | | | vcvtdq2ps ymm3, ymm1
| 1 | | 1.0 | | | | | | | vcvtdq2ps ymm4, ymm1
| 1 | 1.0 | | | | | | | | vcvtdq2ps ymm5, ymm1
| 1 | | 1.0 | | | | | | | vcvtdq2ps ymm6, ymm1
| 1 | 1.0 | | | | | | | | vcvtdq2ps ymm7, ymm1
| 1 | | 1.0 | | | | | | | vcvtdq2ps ymm8, ymm1
| 1 | 1.0 | | | | | | | | vcvtdq2ps ymm9, ymm1
| 1 | | 1.0 | | | | | | | vcvtdq2ps ymm10, ymm1
| 1 | 1.0 | | | | | | | | vcvtdq2ps ymm11, ymm1
| 1 | | 1.0 | | | | | | | vcvtdq2ps ymm12, ymm1
Total Num Of Uops: 12
With the same register for for different operands
Throughput Analysis Report
--------------------------
Block Throughput: 3.95 Cycles Throughput Bottleneck: Backend
Loop Count: 81
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
--------------------------------------------------------------------------------------------------
| Cycles | 0.5 0.0 | 0.5 | 0.0 0.0 | 0.0 0.0 | 0.0 | 0.0 | 0.0 | 0.0 |
--------------------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
-----------------------------------------------------------------------------------------
| 1 | 0.5 | 0.5 | | | | | | | vcvtdq2ps ymm0, ymm0
Total Num Of Uops: 1