PCLMULQDQ (XMM, XMM, I8)

With unroll_count=500 and no inner loop

Code:

   0:	66 0f 3a 44 c1 02    	pclmullqhqdq xmm0,xmm1

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 7.0
- Reference cycles: 5.55
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	66 0f 3a 44 c1 02    	pclmullqhqdq xmm0,xmm1

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 7.0
- Reference cycles: 5.58
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 1.11
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.3

With loop_count=100 and unroll_count=100

Code:

   0:	66 0f 3a 44 c1 02    	pclmullqhqdq xmm0,xmm1

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 7.0
- Reference cycles: 5.57
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	66 0f 3a 44 c1 02    	pclmullqhqdq xmm0,xmm1
   6:	66 0f 3a 44 d1 02    	pclmullqhqdq xmm2,xmm1
   c:	66 0f 3a 44 d9 02    	pclmullqhqdq xmm3,xmm1
  12:	66 0f 3a 44 e1 02    	pclmullqhqdq xmm4,xmm1

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 7.0
- Reference cycles: 5.6
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	66 0f 3a 44 c1 02    	pclmullqhqdq xmm0,xmm1
   6:	66 0f 3a 44 d1 02    	pclmullqhqdq xmm2,xmm1
   c:	66 0f 3a 44 d9 02    	pclmullqhqdq xmm3,xmm1
  12:	66 0f 3a 44 e1 02    	pclmullqhqdq xmm4,xmm1

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 7.01
- Reference cycles: 5.84
- UOPS_EXECUTED.THREAD: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	66 0f 3a 44 c1 02    	pclmullqhqdq xmm0,xmm1
   6:	66 0f 3a 44 d1 02    	pclmullqhqdq xmm2,xmm1
   c:	66 0f 3a 44 d9 02    	pclmullqhqdq xmm3,xmm1
  12:	66 0f 3a 44 e1 02    	pclmullqhqdq xmm4,xmm1

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 7.01
- Reference cycles: 5.62
- UOPS_EXECUTED.THREAD: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	66 0f 3a 44 c1 02    	pclmullqhqdq xmm0,xmm1
   6:	66 0f 3a 44 d1 02    	pclmullqhqdq xmm2,xmm1
   c:	66 0f 3a 44 d9 02    	pclmullqhqdq xmm3,xmm1
  12:	66 0f 3a 44 e1 02    	pclmullqhqdq xmm4,xmm1
  18:	66 0f 3a 44 e9 02    	pclmullqhqdq xmm5,xmm1
  1e:	66 0f 3a 44 f1 02    	pclmullqhqdq xmm6,xmm1
  24:	66 0f 3a 44 f9 02    	pclmullqhqdq xmm7,xmm1
  2a:	66 44 0f 3a 44 c1 02 	pclmullqhqdq xmm8,xmm1

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 7.98
- Reference cycles: 5.11
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

Code:

   0:	66 0f 3a 44 c1 02    	pclmullqhqdq xmm0,xmm1
   6:	66 0f 3a 44 d1 02    	pclmullqhqdq xmm2,xmm1
   c:	66 0f 3a 44 d9 02    	pclmullqhqdq xmm3,xmm1
  12:	66 0f 3a 44 e1 02    	pclmullqhqdq xmm4,xmm1
  18:	66 0f 3a 44 e9 02    	pclmullqhqdq xmm5,xmm1
  1e:	66 0f 3a 44 f1 02    	pclmullqhqdq xmm6,xmm1
  24:	66 0f 3a 44 f9 02    	pclmullqhqdq xmm7,xmm1
  2a:	66 44 0f 3a 44 c1 02 	pclmullqhqdq xmm8,xmm1

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.02
- Reference cycles: 6.35
- UOPS_EXECUTED.THREAD: 9.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	66 0f 3a 44 c1 02    	pclmullqhqdq xmm0,xmm1
   6:	66 0f 3a 44 d1 02    	pclmullqhqdq xmm2,xmm1
   c:	66 0f 3a 44 d9 02    	pclmullqhqdq xmm3,xmm1
  12:	66 0f 3a 44 e1 02    	pclmullqhqdq xmm4,xmm1
  18:	66 0f 3a 44 e9 02    	pclmullqhqdq xmm5,xmm1
  1e:	66 0f 3a 44 f1 02    	pclmullqhqdq xmm6,xmm1
  24:	66 0f 3a 44 f9 02    	pclmullqhqdq xmm7,xmm1
  2a:	66 44 0f 3a 44 c1 02 	pclmullqhqdq xmm8,xmm1

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.01
- Reference cycles: 6.35
- UOPS_EXECUTED.THREAD: 8.1
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 12 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	66 0f 3a 44 c1 02    	pclmullqhqdq xmm0,xmm1
   6:	66 0f 3a 44 d1 02    	pclmullqhqdq xmm2,xmm1
   c:	66 0f 3a 44 d9 02    	pclmullqhqdq xmm3,xmm1
  12:	66 0f 3a 44 e1 02    	pclmullqhqdq xmm4,xmm1
  18:	66 0f 3a 44 e9 02    	pclmullqhqdq xmm5,xmm1
  1e:	66 0f 3a 44 f1 02    	pclmullqhqdq xmm6,xmm1
  24:	66 0f 3a 44 f9 02    	pclmullqhqdq xmm7,xmm1
  2a:	66 44 0f 3a 44 c1 02 	pclmullqhqdq xmm8,xmm1
  31:	66 44 0f 3a 44 c9 02 	pclmullqhqdq xmm9,xmm1
  38:	66 44 0f 3a 44 d1 02 	pclmullqhqdq xmm10,xmm1
  3f:	66 44 0f 3a 44 d9 02 	pclmullqhqdq xmm11,xmm1
  46:	66 44 0f 3a 44 e1 02 	pclmullqhqdq xmm12,xmm1

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 12.0
- Reference cycles: 9.73
- UOPS_EXECUTED.THREAD: 12.0
- RETIRE_SLOTS: 12.0
- UOPS_MITE: 12.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 12.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 3.0

With loop_count=1000 and unroll_count=1

Code:

   0:	66 0f 3a 44 c1 02    	pclmullqhqdq xmm0,xmm1
   6:	66 0f 3a 44 d1 02    	pclmullqhqdq xmm2,xmm1
   c:	66 0f 3a 44 d9 02    	pclmullqhqdq xmm3,xmm1
  12:	66 0f 3a 44 e1 02    	pclmullqhqdq xmm4,xmm1
  18:	66 0f 3a 44 e9 02    	pclmullqhqdq xmm5,xmm1
  1e:	66 0f 3a 44 f1 02    	pclmullqhqdq xmm6,xmm1
  24:	66 0f 3a 44 f9 02    	pclmullqhqdq xmm7,xmm1
  2a:	66 44 0f 3a 44 c1 02 	pclmullqhqdq xmm8,xmm1
  31:	66 44 0f 3a 44 c9 02 	pclmullqhqdq xmm9,xmm1
  38:	66 44 0f 3a 44 d1 02 	pclmullqhqdq xmm10,xmm1
  3f:	66 44 0f 3a 44 d9 02 	pclmullqhqdq xmm11,xmm1
  46:	66 44 0f 3a 44 e1 02 	pclmullqhqdq xmm12,xmm1

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 12.01
- Reference cycles: 9.51
- UOPS_EXECUTED.THREAD: 13.0
- RETIRE_SLOTS: 13.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 12.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	66 0f 3a 44 c1 02    	pclmullqhqdq xmm0,xmm1
   6:	66 0f 3a 44 d1 02    	pclmullqhqdq xmm2,xmm1
   c:	66 0f 3a 44 d9 02    	pclmullqhqdq xmm3,xmm1
  12:	66 0f 3a 44 e1 02    	pclmullqhqdq xmm4,xmm1
  18:	66 0f 3a 44 e9 02    	pclmullqhqdq xmm5,xmm1
  1e:	66 0f 3a 44 f1 02    	pclmullqhqdq xmm6,xmm1
  24:	66 0f 3a 44 f9 02    	pclmullqhqdq xmm7,xmm1
  2a:	66 44 0f 3a 44 c1 02 	pclmullqhqdq xmm8,xmm1
  31:	66 44 0f 3a 44 c9 02 	pclmullqhqdq xmm9,xmm1
  38:	66 44 0f 3a 44 d1 02 	pclmullqhqdq xmm10,xmm1
  3f:	66 44 0f 3a 44 d9 02 	pclmullqhqdq xmm11,xmm1
  46:	66 44 0f 3a 44 e1 02 	pclmullqhqdq xmm12,xmm1

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12

Show nanoBench command
Results:
- Instructions retired: 12.2
- Core cycles: 12.01
- Reference cycles: 9.51
- UOPS_EXECUTED.THREAD: 12.1
- RETIRE_SLOTS: 12.1
- UOPS_MITE: 0.12
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 12.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With the same register for for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	66 0f 3a 44 c0 02    	pclmullqhqdq xmm0,xmm0

Init:
```
VZEROALL;
PXOR XMM0, XMM0
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 7.0
- Reference cycles: 5.84
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	66 0f 3a 44 c0 02    	pclmullqhqdq xmm0,xmm0

Init:
```
VZEROALL;
PXOR XMM0, XMM0
```
Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 7.0
- Reference cycles: 5.57
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 1.11
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.3

With loop_count=100 and unroll_count=100

Code:

   0:	66 0f 3a 44 c0 02    	pclmullqhqdq xmm0,xmm0

Init:
```
VZEROALL;
PXOR XMM0, XMM0
```
Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 7.0
- Reference cycles: 5.57
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	66 0f 3a 44 c0 02    	pclmullqhqdq xmm0,xmm0
   6:	66 0f 3a 44 c9 02    	pclmullqhqdq xmm1,xmm1
   c:	66 0f 3a 44 d2 02    	pclmullqhqdq xmm2,xmm2
  12:	66 0f 3a 44 db 02    	pclmullqhqdq xmm3,xmm3

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 7.0
- Reference cycles: 5.35
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	66 0f 3a 44 c0 02    	pclmullqhqdq xmm0,xmm0
   6:	66 0f 3a 44 c9 02    	pclmullqhqdq xmm1,xmm1
   c:	66 0f 3a 44 d2 02    	pclmullqhqdq xmm2,xmm2
  12:	66 0f 3a 44 db 02    	pclmullqhqdq xmm3,xmm3

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 7.01
- Reference cycles: 5.55
- UOPS_EXECUTED.THREAD: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	66 0f 3a 44 c0 02    	pclmullqhqdq xmm0,xmm0
   6:	66 0f 3a 44 c9 02    	pclmullqhqdq xmm1,xmm1
   c:	66 0f 3a 44 d2 02    	pclmullqhqdq xmm2,xmm2
  12:	66 0f 3a 44 db 02    	pclmullqhqdq xmm3,xmm3

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 7.01
- Reference cycles: 5.61
- UOPS_EXECUTED.THREAD: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	66 0f 3a 44 c0 02    	pclmullqhqdq xmm0,xmm0
   6:	66 0f 3a 44 c9 02    	pclmullqhqdq xmm1,xmm1
   c:	66 0f 3a 44 d2 02    	pclmullqhqdq xmm2,xmm2
  12:	66 0f 3a 44 db 02    	pclmullqhqdq xmm3,xmm3
  18:	66 0f 3a 44 e4 02    	pclmullqhqdq xmm4,xmm4
  1e:	66 0f 3a 44 ed 02    	pclmullqhqdq xmm5,xmm5
  24:	66 0f 3a 44 f6 02    	pclmullqhqdq xmm6,xmm6
  2a:	66 0f 3a 44 ff 02    	pclmullqhqdq xmm7,xmm7

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.01
- Reference cycles: 6.81
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

Code:

   0:	66 0f 3a 44 c0 02    	pclmullqhqdq xmm0,xmm0
   6:	66 0f 3a 44 c9 02    	pclmullqhqdq xmm1,xmm1
   c:	66 0f 3a 44 d2 02    	pclmullqhqdq xmm2,xmm2
  12:	66 0f 3a 44 db 02    	pclmullqhqdq xmm3,xmm3
  18:	66 0f 3a 44 e4 02    	pclmullqhqdq xmm4,xmm4
  1e:	66 0f 3a 44 ed 02    	pclmullqhqdq xmm5,xmm5
  24:	66 0f 3a 44 f6 02    	pclmullqhqdq xmm6,xmm6
  2a:	66 0f 3a 44 ff 02    	pclmullqhqdq xmm7,xmm7

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.01
- Reference cycles: 6.38
- UOPS_EXECUTED.THREAD: 9.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	66 0f 3a 44 c0 02    	pclmullqhqdq xmm0,xmm0
   6:	66 0f 3a 44 c9 02    	pclmullqhqdq xmm1,xmm1
   c:	66 0f 3a 44 d2 02    	pclmullqhqdq xmm2,xmm2
  12:	66 0f 3a 44 db 02    	pclmullqhqdq xmm3,xmm3
  18:	66 0f 3a 44 e4 02    	pclmullqhqdq xmm4,xmm4
  1e:	66 0f 3a 44 ed 02    	pclmullqhqdq xmm5,xmm5
  24:	66 0f 3a 44 f6 02    	pclmullqhqdq xmm6,xmm6
  2a:	66 0f 3a 44 ff 02    	pclmullqhqdq xmm7,xmm7

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.01
- Reference cycles: 6.86
- UOPS_EXECUTED.THREAD: 8.1
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.09
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 13 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	66 0f 3a 44 c0 02    	pclmullqhqdq xmm0,xmm0
   6:	66 0f 3a 44 c9 02    	pclmullqhqdq xmm1,xmm1
   c:	66 0f 3a 44 d2 02    	pclmullqhqdq xmm2,xmm2
  12:	66 0f 3a 44 db 02    	pclmullqhqdq xmm3,xmm3
  18:	66 0f 3a 44 e4 02    	pclmullqhqdq xmm4,xmm4
  1e:	66 0f 3a 44 ed 02    	pclmullqhqdq xmm5,xmm5
  24:	66 0f 3a 44 f6 02    	pclmullqhqdq xmm6,xmm6
  2a:	66 0f 3a 44 ff 02    	pclmullqhqdq xmm7,xmm7
  30:	66 45 0f 3a 44 c0 02 	pclmullqhqdq xmm8,xmm8
  37:	66 45 0f 3a 44 c9 02 	pclmullqhqdq xmm9,xmm9
  3e:	66 45 0f 3a 44 d2 02 	pclmullqhqdq xmm10,xmm10
  45:	66 45 0f 3a 44 db 02 	pclmullqhqdq xmm11,xmm11
  4c:	66 45 0f 3a 44 e4 02 	pclmullqhqdq xmm12,xmm12

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 13.0
- Reference cycles: 11.19
- UOPS_EXECUTED.THREAD: 13.0
- RETIRE_SLOTS: 13.0
- UOPS_MITE: 13.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 13.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 3.25

With loop_count=1000 and unroll_count=1

Code:

   0:	66 0f 3a 44 c0 02    	pclmullqhqdq xmm0,xmm0
   6:	66 0f 3a 44 c9 02    	pclmullqhqdq xmm1,xmm1
   c:	66 0f 3a 44 d2 02    	pclmullqhqdq xmm2,xmm2
  12:	66 0f 3a 44 db 02    	pclmullqhqdq xmm3,xmm3
  18:	66 0f 3a 44 e4 02    	pclmullqhqdq xmm4,xmm4
  1e:	66 0f 3a 44 ed 02    	pclmullqhqdq xmm5,xmm5
  24:	66 0f 3a 44 f6 02    	pclmullqhqdq xmm6,xmm6
  2a:	66 0f 3a 44 ff 02    	pclmullqhqdq xmm7,xmm7
  30:	66 45 0f 3a 44 c0 02 	pclmullqhqdq xmm8,xmm8
  37:	66 45 0f 3a 44 c9 02 	pclmullqhqdq xmm9,xmm9
  3e:	66 45 0f 3a 44 d2 02 	pclmullqhqdq xmm10,xmm10
  45:	66 45 0f 3a 44 db 02 	pclmullqhqdq xmm11,xmm11
  4c:	66 45 0f 3a 44 e4 02 	pclmullqhqdq xmm12,xmm12

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12

Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 13.01
- Reference cycles: 10.83
- UOPS_EXECUTED.THREAD: 14.0
- RETIRE_SLOTS: 14.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 13.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	66 0f 3a 44 c0 02    	pclmullqhqdq xmm0,xmm0
   6:	66 0f 3a 44 c9 02    	pclmullqhqdq xmm1,xmm1
   c:	66 0f 3a 44 d2 02    	pclmullqhqdq xmm2,xmm2
  12:	66 0f 3a 44 db 02    	pclmullqhqdq xmm3,xmm3
  18:	66 0f 3a 44 e4 02    	pclmullqhqdq xmm4,xmm4
  1e:	66 0f 3a 44 ed 02    	pclmullqhqdq xmm5,xmm5
  24:	66 0f 3a 44 f6 02    	pclmullqhqdq xmm6,xmm6
  2a:	66 0f 3a 44 ff 02    	pclmullqhqdq xmm7,xmm7
  30:	66 45 0f 3a 44 c0 02 	pclmullqhqdq xmm8,xmm8
  37:	66 45 0f 3a 44 c9 02 	pclmullqhqdq xmm9,xmm9
  3e:	66 45 0f 3a 44 d2 02 	pclmullqhqdq xmm10,xmm10
  45:	66 45 0f 3a 44 db 02 	pclmullqhqdq xmm11,xmm11
  4c:	66 45 0f 3a 44 e4 02 	pclmullqhqdq xmm12,xmm12

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12

Show nanoBench command
Results:
- Instructions retired: 13.2
- Core cycles: 13.01
- Reference cycles: 11.17
- UOPS_EXECUTED.THREAD: 13.1
- RETIRE_SLOTS: 13.1
- UOPS_MITE: 1.12
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 13.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.34

PCLMULQDQ (XMM, XMM, I8) - Throughput and Uops

With different registers for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 12 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With the same register for for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 13 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10