DIVPS (XMM, M128)

With unroll_count=500 and no inner loop

Code:

   0:	0f 10 d1             	movups xmm2,xmm1
   3:	41 0f 5e 16          	divps  xmm2,XMMWORD PTR [r14]

Init:

VZEROALL;
MOV RAX, 0x3f8000003f800000;
MOV RBX, 0x3f8000003f800000;
MOV [R14+0], RBX;
MOV [R14+8], RBX;
MOV [R14+16], RBX;
MOV [R14+24], RBX;
MOV [R14+32], RBX;
MOV [R14+40], RBX;
MOV [R14+48], RBX;
MOV [R14+56], RBX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX;
MOV [R14+104], RAX;
MOV [R14+112], RAX;
MOV [R14+120], RAX;
MOVUPS XMM0, [R14];
MOVUPS XMM1, [R14+64];
MOVUPS XMM2, XMM1

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.04
- Reference cycles: 2.58
- UOPS_EXECUTED.THREAD: 2.25
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.24
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.01
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 5.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.5

With unroll_count=500 and no inner loop

Code:

   0:	0f 10 d1             	movups xmm2,xmm1
   3:	41 0f 5e 16          	divps  xmm2,XMMWORD PTR [r14]
   7:	0f ae e8             	lfence

Init:

VZEROALL;
MOV RAX, 0x3f8000003f800000;
MOV RBX, 0x3f8000003f800000;
MOV [R14+0], RBX;
MOV [R14+8], RBX;
MOV [R14+16], RBX;
MOV [R14+24], RBX;
MOV [R14+32], RBX;
MOV [R14+40], RBX;
MOV [R14+48], RBX;
MOV [R14+56], RBX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX;
MOV [R14+104], RAX;
MOV [R14+112], RAX;
MOV [R14+120], RAX;
MOVUPS XMM0, [R14];
MOVUPS XMM1, [R14+64];
MOVUPS XMM2, XMM1

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 26.0
- Reference cycles: 20.63
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 2.0
- UOPS_MS: 2.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 5.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=10

Code:

   0:	0f 10 d1             	movups xmm2,xmm1
   3:	41 0f 5e 16          	divps  xmm2,XMMWORD PTR [r14]

Init:

VZEROALL;
MOV RAX, 0x3f8000003f800000;
MOV RBX, 0x3f8000003f800000;
MOV [R14+0], RBX;
MOV [R14+8], RBX;
MOV [R14+16], RBX;
MOV [R14+24], RBX;
MOV [R14+32], RBX;
MOV [R14+40], RBX;
MOV [R14+48], RBX;
MOV [R14+56], RBX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX;
MOV [R14+104], RAX;
MOV [R14+112], RAX;
MOV [R14+120], RAX;
MOVUPS XMM0, [R14];
MOVUPS XMM1, [R14+64];
MOVUPS XMM2, XMM1

Show nanoBench command
Results:
- Instructions retired: 2.2
- Core cycles: 3.0
- Reference cycles: 2.5
- UOPS_EXECUTED.THREAD: 2.33
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.14
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.09
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 5.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	0f 10 d1             	movups xmm2,xmm1
   3:	41 0f 5e 16          	divps  xmm2,XMMWORD PTR [r14]

Init:

VZEROALL;
MOV RAX, 0x3f8000003f800000;
MOV RBX, 0x3f8000003f800000;
MOV [R14+0], RBX;
MOV [R14+8], RBX;
MOV [R14+16], RBX;
MOV [R14+24], RBX;
MOV [R14+32], RBX;
MOV [R14+40], RBX;
MOV [R14+48], RBX;
MOV [R14+56], RBX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX;
MOV [R14+104], RAX;
MOV [R14+112], RAX;
MOV [R14+120], RAX;
MOVUPS XMM0, [R14];
MOVUPS XMM1, [R14+64];
MOVUPS XMM2, XMM1

Show nanoBench command
Results:
- Instructions retired: 2.02
- Core cycles: 3.0
- Reference cycles: 2.4
- UOPS_EXECUTED.THREAD: 2.26
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.2
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.16
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.08
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 5.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.05

Slow division

With unroll_count=500 and no inner loop

Code:

   0:	0f 10 d1             	movups xmm2,xmm1
   3:	41 0f 5e 16          	divps  xmm2,XMMWORD PTR [r14]

Init:

VZEROALL;
MOV RAX, 0x54ed392654ed3926;
MOV RBX, 0x3f99f4c03f99f4c0;
MOV [R14+0], RBX;
MOV [R14+8], RBX;
MOV [R14+16], RBX;
MOV [R14+24], RBX;
MOV [R14+32], RBX;
MOV [R14+40], RBX;
MOV [R14+48], RBX;
MOV [R14+56], RBX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX;
MOV [R14+104], RAX;
MOV [R14+112], RAX;
MOV [R14+120], RAX;
MOVUPS XMM0, [R14];
MOVUPS XMM1, [R14+64];
MOVUPS XMM2, XMM1

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.04
- Reference cycles: 2.38
- UOPS_EXECUTED.THREAD: 2.25
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.24
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.01
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 5.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.5

With unroll_count=500 and no inner loop

Code:

   0:	0f 10 d1             	movups xmm2,xmm1
   3:	41 0f 5e 16          	divps  xmm2,XMMWORD PTR [r14]
   7:	0f ae e8             	lfence

Init:

VZEROALL;
MOV RAX, 0x54ed392654ed3926;
MOV RBX, 0x3f99f4c03f99f4c0;
MOV [R14+0], RBX;
MOV [R14+8], RBX;
MOV [R14+16], RBX;
MOV [R14+24], RBX;
MOV [R14+32], RBX;
MOV [R14+40], RBX;
MOV [R14+48], RBX;
MOV [R14+56], RBX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX;
MOV [R14+104], RAX;
MOV [R14+112], RAX;
MOV [R14+120], RAX;
MOVUPS XMM0, [R14];
MOVUPS XMM1, [R14+64];
MOVUPS XMM2, XMM1

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 26.0
- Reference cycles: 20.59
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 2.0
- UOPS_MS: 2.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 5.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=10

Code:

   0:	0f 10 d1             	movups xmm2,xmm1
   3:	41 0f 5e 16          	divps  xmm2,XMMWORD PTR [r14]

Init:

VZEROALL;
MOV RAX, 0x54ed392654ed3926;
MOV RBX, 0x3f99f4c03f99f4c0;
MOV [R14+0], RBX;
MOV [R14+8], RBX;
MOV [R14+16], RBX;
MOV [R14+24], RBX;
MOV [R14+32], RBX;
MOV [R14+40], RBX;
MOV [R14+48], RBX;
MOV [R14+56], RBX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX;
MOV [R14+104], RAX;
MOV [R14+112], RAX;
MOV [R14+120], RAX;
MOVUPS XMM0, [R14];
MOVUPS XMM1, [R14+64];
MOVUPS XMM2, XMM1

Show nanoBench command
Results:
- Instructions retired: 2.2
- Core cycles: 3.0
- Reference cycles: 2.39
- UOPS_EXECUTED.THREAD: 2.33
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.13
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.09
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 5.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	0f 10 d1             	movups xmm2,xmm1
   3:	41 0f 5e 16          	divps  xmm2,XMMWORD PTR [r14]

Init:

VZEROALL;
MOV RAX, 0x54ed392654ed3926;
MOV RBX, 0x3f99f4c03f99f4c0;
MOV [R14+0], RBX;
MOV [R14+8], RBX;
MOV [R14+16], RBX;
MOV [R14+24], RBX;
MOV [R14+32], RBX;
MOV [R14+40], RBX;
MOV [R14+48], RBX;
MOV [R14+56], RBX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX;
MOV [R14+104], RAX;
MOV [R14+112], RAX;
MOV [R14+120], RAX;
MOVUPS XMM0, [R14];
MOVUPS XMM1, [R14+64];
MOVUPS XMM2, XMM1

Show nanoBench command
Results:
- Instructions retired: 2.02
- Core cycles: 3.0
- Reference cycles: 2.5
- UOPS_EXECUTED.THREAD: 2.26
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.2
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.16
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.08
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 5.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.05

With an indexed addressing mode

Fast division

With unroll_count=500 and no inner loop

Code:

   0:	0f 10 d1             	movups xmm2,xmm1
   3:	41 0f 5e 16          	divps  xmm2,XMMWORD PTR [r14]

Init:

VZEROALL;
MOV RAX, 0x3f8000003f800000;
MOV RBX, 0x3f8000003f800000;
MOV [R14+0], RBX;
MOV [R14+8], RBX;
MOV [R14+16], RBX;
MOV [R14+24], RBX;
MOV [R14+32], RBX;
MOV [R14+40], RBX;
MOV [R14+48], RBX;
MOV [R14+56], RBX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX;
MOV [R14+104], RAX;
MOV [R14+112], RAX;
MOV [R14+120], RAX;
MOVUPS XMM0, [R14];
MOVUPS XMM1, [R14+64];
MOVUPS XMM2, XMM1

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.04
- Reference cycles: 2.34
- UOPS_EXECUTED.THREAD: 2.25
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.24
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.01
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 5.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.5

With unroll_count=500 and no inner loop

Code:

   0:	0f 10 d1             	movups xmm2,xmm1
   3:	41 0f 5e 16          	divps  xmm2,XMMWORD PTR [r14]
   7:	0f ae e8             	lfence

Init:

VZEROALL;
MOV RAX, 0x3f8000003f800000;
MOV RBX, 0x3f8000003f800000;
MOV [R14+0], RBX;
MOV [R14+8], RBX;
MOV [R14+16], RBX;
MOV [R14+24], RBX;
MOV [R14+32], RBX;
MOV [R14+40], RBX;
MOV [R14+48], RBX;
MOV [R14+56], RBX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX;
MOV [R14+104], RAX;
MOV [R14+112], RAX;
MOV [R14+120], RAX;
MOVUPS XMM0, [R14];
MOVUPS XMM1, [R14+64];
MOVUPS XMM2, XMM1

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 26.0
- Reference cycles: 20.78
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 2.0
- UOPS_MS: 2.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 5.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=10

Code:

   0:	0f 10 d1             	movups xmm2,xmm1
   3:	41 0f 5e 16          	divps  xmm2,XMMWORD PTR [r14]

Init:

VZEROALL;
MOV RAX, 0x3f8000003f800000;
MOV RBX, 0x3f8000003f800000;
MOV [R14+0], RBX;
MOV [R14+8], RBX;
MOV [R14+16], RBX;
MOV [R14+24], RBX;
MOV [R14+32], RBX;
MOV [R14+40], RBX;
MOV [R14+48], RBX;
MOV [R14+56], RBX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX;
MOV [R14+104], RAX;
MOV [R14+112], RAX;
MOV [R14+120], RAX;
MOVUPS XMM0, [R14];
MOVUPS XMM1, [R14+64];
MOVUPS XMM2, XMM1

Show nanoBench command
Results:
- Instructions retired: 2.2
- Core cycles: 3.0
- Reference cycles: 2.39
- UOPS_EXECUTED.THREAD: 2.33
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.13
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.09
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 5.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	0f 10 d1             	movups xmm2,xmm1
   3:	41 0f 5e 16          	divps  xmm2,XMMWORD PTR [r14]

Init:

VZEROALL;
MOV RAX, 0x3f8000003f800000;
MOV RBX, 0x3f8000003f800000;
MOV [R14+0], RBX;
MOV [R14+8], RBX;
MOV [R14+16], RBX;
MOV [R14+24], RBX;
MOV [R14+32], RBX;
MOV [R14+40], RBX;
MOV [R14+48], RBX;
MOV [R14+56], RBX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX;
MOV [R14+104], RAX;
MOV [R14+112], RAX;
MOV [R14+120], RAX;
MOVUPS XMM0, [R14];
MOVUPS XMM1, [R14+64];
MOVUPS XMM2, XMM1

Show nanoBench command
Results:
- Instructions retired: 2.02
- Core cycles: 3.0
- Reference cycles: 2.39
- UOPS_EXECUTED.THREAD: 2.26
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.2
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.17
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.08
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 5.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.05

Slow division

With unroll_count=500 and no inner loop

Code:

   0:	0f 10 d1             	movups xmm2,xmm1
   3:	41 0f 5e 16          	divps  xmm2,XMMWORD PTR [r14]

Init:

VZEROALL;
MOV RAX, 0x54ed392654ed3926;
MOV RBX, 0x3f99f4c03f99f4c0;
MOV [R14+0], RBX;
MOV [R14+8], RBX;
MOV [R14+16], RBX;
MOV [R14+24], RBX;
MOV [R14+32], RBX;
MOV [R14+40], RBX;
MOV [R14+48], RBX;
MOV [R14+56], RBX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX;
MOV [R14+104], RAX;
MOV [R14+112], RAX;
MOV [R14+120], RAX;
MOVUPS XMM0, [R14];
MOVUPS XMM1, [R14+64];
MOVUPS XMM2, XMM1

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.04
- Reference cycles: 2.43
- UOPS_EXECUTED.THREAD: 2.25
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.24
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.01
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 5.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.5

With unroll_count=500 and no inner loop

Code:

   0:	0f 10 d1             	movups xmm2,xmm1
   3:	41 0f 5e 16          	divps  xmm2,XMMWORD PTR [r14]
   7:	0f ae e8             	lfence

Init:

VZEROALL;
MOV RAX, 0x54ed392654ed3926;
MOV RBX, 0x3f99f4c03f99f4c0;
MOV [R14+0], RBX;
MOV [R14+8], RBX;
MOV [R14+16], RBX;
MOV [R14+24], RBX;
MOV [R14+32], RBX;
MOV [R14+40], RBX;
MOV [R14+48], RBX;
MOV [R14+56], RBX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX;
MOV [R14+104], RAX;
MOV [R14+112], RAX;
MOV [R14+120], RAX;
MOVUPS XMM0, [R14];
MOVUPS XMM1, [R14+64];
MOVUPS XMM2, XMM1

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 26.0
- Reference cycles: 20.63
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 2.0
- UOPS_MS: 2.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 5.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=10

Code:

   0:	0f 10 d1             	movups xmm2,xmm1
   3:	41 0f 5e 16          	divps  xmm2,XMMWORD PTR [r14]

Init:

VZEROALL;
MOV RAX, 0x54ed392654ed3926;
MOV RBX, 0x3f99f4c03f99f4c0;
MOV [R14+0], RBX;
MOV [R14+8], RBX;
MOV [R14+16], RBX;
MOV [R14+24], RBX;
MOV [R14+32], RBX;
MOV [R14+40], RBX;
MOV [R14+48], RBX;
MOV [R14+56], RBX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX;
MOV [R14+104], RAX;
MOV [R14+112], RAX;
MOV [R14+120], RAX;
MOVUPS XMM0, [R14];
MOVUPS XMM1, [R14+64];
MOVUPS XMM2, XMM1

Show nanoBench command
Results:
- Instructions retired: 2.2
- Core cycles: 3.0
- Reference cycles: 2.39
- UOPS_EXECUTED.THREAD: 2.33
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.14
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.09
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 5.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	0f 10 d1             	movups xmm2,xmm1
   3:	41 0f 5e 16          	divps  xmm2,XMMWORD PTR [r14]

Init:

VZEROALL;
MOV RAX, 0x54ed392654ed3926;
MOV RBX, 0x3f99f4c03f99f4c0;
MOV [R14+0], RBX;
MOV [R14+8], RBX;
MOV [R14+16], RBX;
MOV [R14+24], RBX;
MOV [R14+32], RBX;
MOV [R14+40], RBX;
MOV [R14+48], RBX;
MOV [R14+56], RBX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX;
MOV [R14+104], RAX;
MOV [R14+112], RAX;
MOV [R14+120], RAX;
MOVUPS XMM0, [R14];
MOVUPS XMM1, [R14+64];
MOVUPS XMM2, XMM1

Show nanoBench command
Results:
- Instructions retired: 2.02
- Core cycles: 3.0
- Reference cycles: 2.39
- UOPS_EXECUTED.THREAD: 2.26
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.2
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.17
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.08
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 5.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.05

DIVPS (XMM, M128) - Throughput and Uops

With a non-indexed addressing mode

Fast division

With unroll_count=500 and no inner loop

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

Slow division

With unroll_count=500 and no inner loop

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With an indexed addressing mode

Fast division

With unroll_count=500 and no inner loop

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

Slow division

With unroll_count=500 and no inner loop

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100