BSR (R64, R64) - Throughput and Uops (IACA 3.0)

With different registers for different operands

With 1 independent instruction

Throughput Analysis Report
--------------------------
Block Throughput: 0.98 Cycles       Throughput Bottleneck: Dependency chains
Loop Count:  60
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
|  Port  |   0   -  DV   |   1   |   2   -  D    |   3   -  D    |   4   |   5   |   6   |   7   |
--------------------------------------------------------------------------------------------------
| Cycles |  0.0     0.0  |  1.0  |  0.0     0.0  |  0.0     0.0  |  0.0  |  0.0  |  0.0  |  0.0  |
--------------------------------------------------------------------------------------------------

| Num Of   |                    Ports pressure in cycles                         |      |
|  Uops    |  0  - DV    |  1   |  2  -  D    |  3  -  D    |  4   |  5   |  6   |  7   |
-----------------------------------------------------------------------------------------
|   1      |             | 1.0  |             |             |      |      |      |      | bsr r8, r9
Total Num Of Uops: 1

With 12 independent instructions

Throughput Analysis Report
--------------------------
Block Throughput: 11.95 Cycles       Throughput Bottleneck: Backend
Loop Count:  22
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
|  Port  |   0   -  DV   |   1   |   2   -  D    |   3   -  D    |   4   |   5   |   6   |   7   |
--------------------------------------------------------------------------------------------------
| Cycles |  0.0     0.0  | 12.0  |  0.0     0.0  |  0.0     0.0  |  0.0  |  0.0  |  0.0  |  0.0  |
--------------------------------------------------------------------------------------------------

| Num Of   |                    Ports pressure in cycles                         |      |
|  Uops    |  0  - DV    |  1   |  2  -  D    |  3  -  D    |  4   |  5   |  6   |  7   |
-----------------------------------------------------------------------------------------
|   1      |             | 1.0  |             |             |      |      |      |      | bsr r8, r9
|   1      |             | 1.0  |             |             |      |      |      |      | bsr r10, r9
|   1      |             | 1.0  |             |             |      |      |      |      | bsr r11, r9
|   1      |             | 1.0  |             |             |      |      |      |      | bsr r12, r9
|   1      |             | 1.0  |             |             |      |      |      |      | bsr r13, r9
|   1      |             | 1.0  |             |             |      |      |      |      | bsr r14, r9
|   1      |             | 1.0  |             |             |      |      |      |      | bsr rbx, r9
|   1      |             | 1.0  |             |             |      |      |      |      | bsr rcx, r9
|   1      |             | 1.0  |             |             |      |      |      |      | bsr rdx, r9
|   1      |             | 1.0  |             |             |      |      |      |      | bsr rdi, r9
|   1      |             | 1.0  |             |             |      |      |      |      | bsr rsi, r9
|   1      |             | 1.0  |             |             |      |      |      |      | bsr rbp, r9
Total Num Of Uops: 12

With the same register for for different operands

With 1 independent instruction

Throughput Analysis Report
--------------------------
Block Throughput: 2.96 Cycles       Throughput Bottleneck: Backend
Loop Count:  81
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
|  Port  |   0   -  DV   |   1   |   2   -  D    |   3   -  D    |   4   |   5   |   6   |   7   |
--------------------------------------------------------------------------------------------------
| Cycles |  0.0     0.0  |  1.0  |  0.0     0.0  |  0.0     0.0  |  0.0  |  0.0  |  0.0  |  0.0  |
--------------------------------------------------------------------------------------------------

| Num Of   |                    Ports pressure in cycles                         |      |
|  Uops    |  0  - DV    |  1   |  2  -  D    |  3  -  D    |  4   |  5   |  6   |  7   |
-----------------------------------------------------------------------------------------
|   1      |             | 1.0  |             |             |      |      |      |      | bsr r8, r8
Total Num Of Uops: 1

With 13 independent instructions

Throughput Analysis Report
--------------------------
Block Throughput: 12.95 Cycles       Throughput Bottleneck: Backend
Loop Count:  22
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
|  Port  |   0   -  DV   |   1   |   2   -  D    |   3   -  D    |   4   |   5   |   6   |   7   |
--------------------------------------------------------------------------------------------------
| Cycles |  0.0     0.0  | 13.0  |  0.0     0.0  |  0.0     0.0  |  0.0  |  0.0  |  0.0  |  0.0  |
--------------------------------------------------------------------------------------------------

| Num Of   |                    Ports pressure in cycles                         |      |
|  Uops    |  0  - DV    |  1   |  2  -  D    |  3  -  D    |  4   |  5   |  6   |  7   |
-----------------------------------------------------------------------------------------
|   1      |             | 1.0  |             |             |      |      |      |      | bsr r8, r8
|   1      |             | 1.0  |             |             |      |      |      |      | bsr r9, r9
|   1      |             | 1.0  |             |             |      |      |      |      | bsr r10, r10
|   1      |             | 1.0  |             |             |      |      |      |      | bsr r11, r11
|   1      |             | 1.0  |             |             |      |      |      |      | bsr r12, r12
|   1      |             | 1.0  |             |             |      |      |      |      | bsr r13, r13
|   1      |             | 1.0  |             |             |      |      |      |      | bsr r14, r14
|   1      |             | 1.0  |             |             |      |      |      |      | bsr rbx, rbx
|   1      |             | 1.0  |             |             |      |      |      |      | bsr rcx, rcx
|   1      |             | 1.0  |             |             |      |      |      |      | bsr rdx, rdx
|   1      |             | 1.0  |             |             |      |      |      |      | bsr rdi, rdi
|   1      |             | 1.0  |             |             |      |      |      |      | bsr rsi, rsi
|   1      |             | 1.0  |             |             |      |      |      |      | bsr rbp, rbp
Total Num Of Uops: 13