VSQRTSS (XMM, XMM, XMM) - Throughput and Uops (IACA 2.3)
With 1 independent instruction
Throughput Analysis Report
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Block Throughput: 3.00 Cycles Throughput Bottleneck: FrontEnd
Port Binding In Cycles Per Iteration:
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| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
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| Cycles | 1.0 3.0 | 0.0 | 0.0 0.0 | 0.0 0.0 | 0.0 | 0.0 | 0.0 | 0.0 |
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| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
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| 1 | 1.0 3.0 | | | | | | | | CP | vsqrtss xmm2, xmm1, xmm0
Total Num Of Uops: 1
With 8 independent instructions
Throughput Analysis Report
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Block Throughput: 24.00 Cycles Throughput Bottleneck: Backend. Divider
Port Binding In Cycles Per Iteration:
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| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
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| Cycles | 8.0 24.0 | 0.0 | 0.0 0.0 | 0.0 0.0 | 0.0 | 0.0 | 0.0 | 0.0 |
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| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
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| 1 | 1.0 3.0 | | | | | | | | CP | vsqrtss xmm2, xmm1, xmm0
| 1 | 1.0 3.0 | | | | | | | | CP | vsqrtss xmm3, xmm1, xmm0
| 1 | 1.0 3.0 | | | | | | | | CP | vsqrtss xmm4, xmm1, xmm0
| 1 | 1.0 3.0 | | | | | | | | CP | vsqrtss xmm5, xmm1, xmm0
| 1 | 1.0 3.0 | | | | | | | | CP | vsqrtss xmm6, xmm1, xmm0
| 1 | 1.0 3.0 | | | | | | | | CP | vsqrtss xmm7, xmm1, xmm0
| 1 | 1.0 3.0 | | | | | | | | CP | vsqrtss xmm8, xmm1, xmm0
| 1 | 1.0 3.0 | | | | | | | | CP | vsqrtss xmm9, xmm1, xmm0
Total Num Of Uops: 8