VPHADDD (YMM, YMM, YMM)

With unroll_count=500 and no inner loop

Code:

   0:	c4 e2 75 02 c2       	vphaddd ymm0,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 2.0
- Reference cycles: 1.6
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 3.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	c4 e2 75 02 c2       	vphaddd ymm0,ymm1,ymm2
   5:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 2.0
- Reference cycles: 1.77
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.56
- UOPS_PORT_1: 0.44
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	c4 e2 75 02 c2       	vphaddd ymm0,ymm1,ymm2
   5:	90                   	nop
   6:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 2.0
- Reference cycles: 1.82
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	c4 e2 75 02 c2       	vphaddd ymm0,ymm1,ymm2
   5:	90                   	nop
   6:	90                   	nop
   7:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 2.0
- Reference cycles: 1.77
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 6.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.43
- UOPS_PORT_1: 0.57
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	c4 e2 75 02 c2       	vphaddd ymm0,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 2.0
- Reference cycles: 1.78
- UOPS_EXECUTED.THREAD: 3.1
- RETIRE_SLOTS: 3.1
- UOPS_MITE: 3.11
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000, unroll_count=10, and padding (long NOPs)

Code:

   0:	c4 e2 75 02 c2       	vphaddd ymm0,ymm1,ymm2
   5:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
   c:	0f 1f 84 00 00 00 00 
  13:	00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 2.2
- Core cycles: 2.0
- Reference cycles: 1.77
- UOPS_EXECUTED.THREAD: 3.1
- RETIRE_SLOTS: 4.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	c4 e2 75 02 c2       	vphaddd ymm0,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 2.0
- Reference cycles: 1.78
- UOPS_EXECUTED.THREAD: 3.01
- RETIRE_SLOTS: 3.01
- UOPS_MITE: 3.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=100, unroll_count=100, and padding (long NOPs)

Code:

   0:	c4 e2 75 02 c2       	vphaddd ymm0,ymm1,ymm2
   5:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
   c:	0f 1f 84 00 00 00 00 
  13:	00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 2.02
- Core cycles: 2.0
- Reference cycles: 1.78
- UOPS_EXECUTED.THREAD: 3.01
- RETIRE_SLOTS: 4.01
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.51
- UOPS_PORT_1: 0.49
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	c4 e2 75 02 c2       	vphaddd ymm0,ymm1,ymm2
   5:	c4 e2 75 02 da       	vphaddd ymm3,ymm1,ymm2
   a:	c4 e2 75 02 e2       	vphaddd ymm4,ymm1,ymm2
   f:	c4 e2 75 02 ea       	vphaddd ymm5,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 8.0
- Reference cycles: 6.76
- UOPS_EXECUTED.THREAD: 12.0
- RETIRE_SLOTS: 12.0
- UOPS_MITE: 12.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.99
- UOPS_PORT_1: 2.01
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	c4 e2 75 02 c2       	vphaddd ymm0,ymm1,ymm2
   5:	c4 e2 75 02 da       	vphaddd ymm3,ymm1,ymm2
   a:	c4 e2 75 02 e2       	vphaddd ymm4,ymm1,ymm2
   f:	c4 e2 75 02 ea       	vphaddd ymm5,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 8.01
- Reference cycles: 7.13
- UOPS_EXECUTED.THREAD: 12.5
- RETIRE_SLOTS: 12.5
- UOPS_MITE: 12.53
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.99
- UOPS_PORT_1: 2.01
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.01

With loop_count=1000, unroll_count=2, and padding (long NOPs)

Code:

   0:	c4 e2 75 02 c2       	vphaddd ymm0,ymm1,ymm2
   5:	c4 e2 75 02 da       	vphaddd ymm3,ymm1,ymm2
   a:	c4 e2 75 02 e2       	vphaddd ymm4,ymm1,ymm2
   f:	c4 e2 75 02 ea       	vphaddd ymm5,ymm1,ymm2
  14:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  1b:	0f 1f 84 00 00 00 00 
  22:	00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 8.01
- Reference cycles: 7.14
- UOPS_EXECUTED.THREAD: 12.5
- RETIRE_SLOTS: 13.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.98
- UOPS_PORT_1: 2.03
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	c4 e2 75 02 c2       	vphaddd ymm0,ymm1,ymm2
   5:	c4 e2 75 02 da       	vphaddd ymm3,ymm1,ymm2
   a:	c4 e2 75 02 e2       	vphaddd ymm4,ymm1,ymm2
   f:	c4 e2 75 02 ea       	vphaddd ymm5,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 8.01
- Reference cycles: 7.1
- UOPS_EXECUTED.THREAD: 12.05
- RETIRE_SLOTS: 12.05
- UOPS_MITE: 12.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 2.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.01

With loop_count=100, unroll_count=20, and padding (long NOPs)

Code:

   0:	c4 e2 75 02 c2       	vphaddd ymm0,ymm1,ymm2
   5:	c4 e2 75 02 da       	vphaddd ymm3,ymm1,ymm2
   a:	c4 e2 75 02 e2       	vphaddd ymm4,ymm1,ymm2
   f:	c4 e2 75 02 ea       	vphaddd ymm5,ymm1,ymm2
  14:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  1b:	0f 1f 84 00 00 00 00 
  22:	00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 5.1
- Core cycles: 8.01
- Reference cycles: 7.09
- UOPS_EXECUTED.THREAD: 12.05
- RETIRE_SLOTS: 13.05
- UOPS_MITE: 1.17
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.99
- UOPS_PORT_1: 2.01
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.34

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 e2 75 02 c2       	vphaddd ymm0,ymm1,ymm2
   5:	c4 e2 75 02 da       	vphaddd ymm3,ymm1,ymm2
   a:	c4 e2 75 02 e2       	vphaddd ymm4,ymm1,ymm2
   f:	c4 e2 75 02 ea       	vphaddd ymm5,ymm1,ymm2
  14:	c4 e2 75 02 f2       	vphaddd ymm6,ymm1,ymm2
  19:	c4 e2 75 02 fa       	vphaddd ymm7,ymm1,ymm2
  1e:	c4 62 75 02 c2       	vphaddd ymm8,ymm1,ymm2
  23:	c4 62 75 02 ca       	vphaddd ymm9,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 16.01
- Reference cycles: 13.74
- UOPS_EXECUTED.THREAD: 24.0
- RETIRE_SLOTS: 24.0
- UOPS_MITE: 24.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.99
- UOPS_PORT_1: 4.01
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 e2 75 02 c2       	vphaddd ymm0,ymm1,ymm2
   5:	c4 e2 75 02 da       	vphaddd ymm3,ymm1,ymm2
   a:	c4 e2 75 02 e2       	vphaddd ymm4,ymm1,ymm2
   f:	c4 e2 75 02 ea       	vphaddd ymm5,ymm1,ymm2
  14:	c4 e2 75 02 f2       	vphaddd ymm6,ymm1,ymm2
  19:	c4 e2 75 02 fa       	vphaddd ymm7,ymm1,ymm2
  1e:	c4 62 75 02 c2       	vphaddd ymm8,ymm1,ymm2
  23:	c4 62 75 02 ca       	vphaddd ymm9,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 16.01
- Reference cycles: 14.19
- UOPS_EXECUTED.THREAD: 25.0
- RETIRE_SLOTS: 25.0
- UOPS_MITE: 25.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.99
- UOPS_PORT_1: 4.01
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.02

With loop_count=1000, unroll_count=1, and padding (long NOPs)

Code:

   0:	c4 e2 75 02 c2       	vphaddd ymm0,ymm1,ymm2
   5:	c4 e2 75 02 da       	vphaddd ymm3,ymm1,ymm2
   a:	c4 e2 75 02 e2       	vphaddd ymm4,ymm1,ymm2
   f:	c4 e2 75 02 ea       	vphaddd ymm5,ymm1,ymm2
  14:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  1b:	0f 1f 84 00 00 00 00 
  22:	00 
  23:	c4 e2 75 02 f2       	vphaddd ymm6,ymm1,ymm2
  28:	c4 e2 75 02 fa       	vphaddd ymm7,ymm1,ymm2
  2d:	c4 62 75 02 c2       	vphaddd ymm8,ymm1,ymm2
  32:	c4 62 75 02 ca       	vphaddd ymm9,ymm1,ymm2
  37:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  3e:	0f 1f 84 00 00 00 00 
  45:	00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 16.01
- Reference cycles: 14.19
- UOPS_EXECUTED.THREAD: 25.0
- RETIRE_SLOTS: 27.0
- UOPS_MITE: 0.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.95
- UOPS_PORT_1: 4.05
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	c4 e2 75 02 c2       	vphaddd ymm0,ymm1,ymm2
   5:	c4 e2 75 02 da       	vphaddd ymm3,ymm1,ymm2
   a:	c4 e2 75 02 e2       	vphaddd ymm4,ymm1,ymm2
   f:	c4 e2 75 02 ea       	vphaddd ymm5,ymm1,ymm2
  14:	c4 e2 75 02 f2       	vphaddd ymm6,ymm1,ymm2
  19:	c4 e2 75 02 fa       	vphaddd ymm7,ymm1,ymm2
  1e:	c4 62 75 02 c2       	vphaddd ymm8,ymm1,ymm2
  23:	c4 62 75 02 ca       	vphaddd ymm9,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 16.01
- Reference cycles: 14.21
- UOPS_EXECUTED.THREAD: 24.1
- RETIRE_SLOTS: 24.1
- UOPS_MITE: 24.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.02

With loop_count=100, unroll_count=10, and padding (long NOPs)

Code:

   0:	c4 e2 75 02 c2       	vphaddd ymm0,ymm1,ymm2
   5:	c4 e2 75 02 da       	vphaddd ymm3,ymm1,ymm2
   a:	c4 e2 75 02 e2       	vphaddd ymm4,ymm1,ymm2
   f:	c4 e2 75 02 ea       	vphaddd ymm5,ymm1,ymm2
  14:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  1b:	0f 1f 84 00 00 00 00 
  22:	00 
  23:	c4 e2 75 02 f2       	vphaddd ymm6,ymm1,ymm2
  28:	c4 e2 75 02 fa       	vphaddd ymm7,ymm1,ymm2
  2d:	c4 62 75 02 c2       	vphaddd ymm8,ymm1,ymm2
  32:	c4 62 75 02 ca       	vphaddd ymm9,ymm1,ymm2
  37:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  3e:	0f 1f 84 00 00 00 00 
  45:	00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 10.2
- Core cycles: 16.01
- Reference cycles: 14.23
- UOPS_EXECUTED.THREAD: 24.1
- RETIRE_SLOTS: 26.1
- UOPS_MITE: 2.34
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.98
- UOPS_PORT_1: 4.02
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.67

With 11 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 e2 75 02 c2       	vphaddd ymm0,ymm1,ymm2
   5:	c4 e2 75 02 da       	vphaddd ymm3,ymm1,ymm2
   a:	c4 e2 75 02 e2       	vphaddd ymm4,ymm1,ymm2
   f:	c4 e2 75 02 ea       	vphaddd ymm5,ymm1,ymm2
  14:	c4 e2 75 02 f2       	vphaddd ymm6,ymm1,ymm2
  19:	c4 e2 75 02 fa       	vphaddd ymm7,ymm1,ymm2
  1e:	c4 62 75 02 c2       	vphaddd ymm8,ymm1,ymm2
  23:	c4 62 75 02 ca       	vphaddd ymm9,ymm1,ymm2
  28:	c4 62 75 02 d2       	vphaddd ymm10,ymm1,ymm2
  2d:	c4 62 75 02 da       	vphaddd ymm11,ymm1,ymm2
  32:	c4 62 75 02 e2       	vphaddd ymm12,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 22.01
- Reference cycles: 19.73
- UOPS_EXECUTED.THREAD: 33.0
- RETIRE_SLOTS: 33.0
- UOPS_MITE: 33.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 5.48
- UOPS_PORT_1: 5.52
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 22.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 11.0

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 e2 75 02 c2       	vphaddd ymm0,ymm1,ymm2
   5:	c4 e2 75 02 da       	vphaddd ymm3,ymm1,ymm2
   a:	c4 e2 75 02 e2       	vphaddd ymm4,ymm1,ymm2
   f:	c4 e2 75 02 ea       	vphaddd ymm5,ymm1,ymm2
  14:	c4 e2 75 02 f2       	vphaddd ymm6,ymm1,ymm2
  19:	c4 e2 75 02 fa       	vphaddd ymm7,ymm1,ymm2
  1e:	c4 62 75 02 c2       	vphaddd ymm8,ymm1,ymm2
  23:	c4 62 75 02 ca       	vphaddd ymm9,ymm1,ymm2
  28:	c4 62 75 02 d2       	vphaddd ymm10,ymm1,ymm2
  2d:	c4 62 75 02 da       	vphaddd ymm11,ymm1,ymm2
  32:	c4 62 75 02 e2       	vphaddd ymm12,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 22.01
- Reference cycles: 19.53
- UOPS_EXECUTED.THREAD: 34.0
- RETIRE_SLOTS: 34.0
- UOPS_MITE: 34.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 5.42
- UOPS_PORT_1: 5.58
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 22.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 11.02

With loop_count=1000, unroll_count=1, and padding (long NOPs)

Code:

   0:	c4 e2 75 02 c2       	vphaddd ymm0,ymm1,ymm2
   5:	c4 e2 75 02 da       	vphaddd ymm3,ymm1,ymm2
   a:	c4 e2 75 02 e2       	vphaddd ymm4,ymm1,ymm2
   f:	c4 e2 75 02 ea       	vphaddd ymm5,ymm1,ymm2
  14:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  1b:	0f 1f 84 00 00 00 00 
  22:	00 
  23:	c4 e2 75 02 f2       	vphaddd ymm6,ymm1,ymm2
  28:	c4 e2 75 02 fa       	vphaddd ymm7,ymm1,ymm2
  2d:	c4 62 75 02 c2       	vphaddd ymm8,ymm1,ymm2
  32:	c4 62 75 02 ca       	vphaddd ymm9,ymm1,ymm2
  37:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  3e:	0f 1f 84 00 00 00 00 
  45:	00 
  46:	c4 62 75 02 d2       	vphaddd ymm10,ymm1,ymm2
  4b:	c4 62 75 02 da       	vphaddd ymm11,ymm1,ymm2
  50:	c4 62 75 02 e2       	vphaddd ymm12,ymm1,ymm2
  55:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  5c:	0f 1f 84 00 00 00 00 
  63:	00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 22.01
- Reference cycles: 19.55
- UOPS_EXECUTED.THREAD: 34.0
- RETIRE_SLOTS: 37.0
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 5.47
- UOPS_PORT_1: 5.53
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 22.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	c4 e2 75 02 c2       	vphaddd ymm0,ymm1,ymm2
   5:	c4 e2 75 02 da       	vphaddd ymm3,ymm1,ymm2
   a:	c4 e2 75 02 e2       	vphaddd ymm4,ymm1,ymm2
   f:	c4 e2 75 02 ea       	vphaddd ymm5,ymm1,ymm2
  14:	c4 e2 75 02 f2       	vphaddd ymm6,ymm1,ymm2
  19:	c4 e2 75 02 fa       	vphaddd ymm7,ymm1,ymm2
  1e:	c4 62 75 02 c2       	vphaddd ymm8,ymm1,ymm2
  23:	c4 62 75 02 ca       	vphaddd ymm9,ymm1,ymm2
  28:	c4 62 75 02 d2       	vphaddd ymm10,ymm1,ymm2
  2d:	c4 62 75 02 da       	vphaddd ymm11,ymm1,ymm2
  32:	c4 62 75 02 e2       	vphaddd ymm12,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 11.2
- Core cycles: 22.01
- Reference cycles: 19.55
- UOPS_EXECUTED.THREAD: 33.1
- RETIRE_SLOTS: 33.1
- UOPS_MITE: 33.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 5.49
- UOPS_PORT_1: 5.51
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 22.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 11.02

With loop_count=100, unroll_count=10, and padding (long NOPs)

Code:

   0:	c4 e2 75 02 c2       	vphaddd ymm0,ymm1,ymm2
   5:	c4 e2 75 02 da       	vphaddd ymm3,ymm1,ymm2
   a:	c4 e2 75 02 e2       	vphaddd ymm4,ymm1,ymm2
   f:	c4 e2 75 02 ea       	vphaddd ymm5,ymm1,ymm2
  14:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  1b:	0f 1f 84 00 00 00 00 
  22:	00 
  23:	c4 e2 75 02 f2       	vphaddd ymm6,ymm1,ymm2
  28:	c4 e2 75 02 fa       	vphaddd ymm7,ymm1,ymm2
  2d:	c4 62 75 02 c2       	vphaddd ymm8,ymm1,ymm2
  32:	c4 62 75 02 ca       	vphaddd ymm9,ymm1,ymm2
  37:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  3e:	0f 1f 84 00 00 00 00 
  45:	00 
  46:	c4 62 75 02 d2       	vphaddd ymm10,ymm1,ymm2
  4b:	c4 62 75 02 da       	vphaddd ymm11,ymm1,ymm2
  50:	c4 62 75 02 e2       	vphaddd ymm12,ymm1,ymm2
  55:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  5c:	0f 1f 84 00 00 00 00 
  63:	00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 14.2
- Core cycles: 22.01
- Reference cycles: 19.55
- UOPS_EXECUTED.THREAD: 33.1
- RETIRE_SLOTS: 36.1
- UOPS_MITE: 0.36
- UOPS_MS: 0.0
- UOPS_PORT_0: 5.47
- UOPS_PORT_1: 5.53
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 22.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.11

With the same register for for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	c4 e2 7d 02 c0       	vphaddd ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 3.0
- Reference cycles: 2.66
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 3.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.46
- UOPS_PORT_1: 0.54
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	c4 e2 7d 02 c0       	vphaddd ymm0,ymm0,ymm0
   5:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.0
- Reference cycles: 2.7
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.55
- UOPS_PORT_1: 0.45
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	c4 e2 7d 02 c0       	vphaddd ymm0,ymm0,ymm0
   5:	90                   	nop
   6:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 3.0
- Reference cycles: 2.66
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.49
- UOPS_PORT_1: 0.51
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	c4 e2 7d 02 c0       	vphaddd ymm0,ymm0,ymm0
   5:	90                   	nop
   6:	90                   	nop
   7:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 3.0
- Reference cycles: 2.66
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 6.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.49
- UOPS_PORT_1: 0.51
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	c4 e2 7d 02 c0       	vphaddd ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 3.0
- Reference cycles: 2.66
- UOPS_EXECUTED.THREAD: 3.1
- RETIRE_SLOTS: 3.1
- UOPS_MITE: 3.11
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000, unroll_count=10, and padding (long NOPs)

Code:

   0:	c4 e2 7d 02 c0       	vphaddd ymm0,ymm0,ymm0
   5:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
   c:	0f 1f 84 00 00 00 00 
  13:	00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 2.2
- Core cycles: 3.0
- Reference cycles: 2.66
- UOPS_EXECUTED.THREAD: 3.1
- RETIRE_SLOTS: 4.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	c4 e2 7d 02 c0       	vphaddd ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 3.0
- Reference cycles: 2.66
- UOPS_EXECUTED.THREAD: 3.01
- RETIRE_SLOTS: 3.01
- UOPS_MITE: 3.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.48
- UOPS_PORT_1: 0.52
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=100, unroll_count=100, and padding (long NOPs)

Code:

   0:	c4 e2 7d 02 c0       	vphaddd ymm0,ymm0,ymm0
   5:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
   c:	0f 1f 84 00 00 00 00 
  13:	00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 2.02
- Core cycles: 3.0
- Reference cycles: 2.66
- UOPS_EXECUTED.THREAD: 3.01
- RETIRE_SLOTS: 4.01
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.51
- UOPS_PORT_1: 0.49
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	c4 e2 7d 02 c0       	vphaddd ymm0,ymm0,ymm0
   5:	c4 e2 75 02 c9       	vphaddd ymm1,ymm1,ymm1
   a:	c4 e2 6d 02 d2       	vphaddd ymm2,ymm2,ymm2
   f:	c4 e2 65 02 db       	vphaddd ymm3,ymm3,ymm3

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM3, YMM3, YMM3

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 8.0
- Reference cycles: 6.87
- UOPS_EXECUTED.THREAD: 12.0
- RETIRE_SLOTS: 12.0
- UOPS_MITE: 12.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.99
- UOPS_PORT_1: 2.01
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	c4 e2 7d 02 c0       	vphaddd ymm0,ymm0,ymm0
   5:	c4 e2 75 02 c9       	vphaddd ymm1,ymm1,ymm1
   a:	c4 e2 6d 02 d2       	vphaddd ymm2,ymm2,ymm2
   f:	c4 e2 65 02 db       	vphaddd ymm3,ymm3,ymm3

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM3, YMM3, YMM3

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 8.01
- Reference cycles: 7.13
- UOPS_EXECUTED.THREAD: 12.5
- RETIRE_SLOTS: 12.5
- UOPS_MITE: 12.53
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.99
- UOPS_PORT_1: 2.01
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.01

With loop_count=1000, unroll_count=2, and padding (long NOPs)

Code:

   0:	c4 e2 7d 02 c0       	vphaddd ymm0,ymm0,ymm0
   5:	c4 e2 75 02 c9       	vphaddd ymm1,ymm1,ymm1
   a:	c4 e2 6d 02 d2       	vphaddd ymm2,ymm2,ymm2
   f:	c4 e2 65 02 db       	vphaddd ymm3,ymm3,ymm3
  14:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  1b:	0f 1f 84 00 00 00 00 
  22:	00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM3, YMM3, YMM3

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 8.01
- Reference cycles: 7.13
- UOPS_EXECUTED.THREAD: 12.5
- RETIRE_SLOTS: 13.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.98
- UOPS_PORT_1: 2.03
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	c4 e2 7d 02 c0       	vphaddd ymm0,ymm0,ymm0
   5:	c4 e2 75 02 c9       	vphaddd ymm1,ymm1,ymm1
   a:	c4 e2 6d 02 d2       	vphaddd ymm2,ymm2,ymm2
   f:	c4 e2 65 02 db       	vphaddd ymm3,ymm3,ymm3

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM3, YMM3, YMM3

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 8.01
- Reference cycles: 7.14
- UOPS_EXECUTED.THREAD: 12.05
- RETIRE_SLOTS: 12.05
- UOPS_MITE: 12.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 2.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.01

With loop_count=100, unroll_count=20, and padding (long NOPs)

Code:

   0:	c4 e2 7d 02 c0       	vphaddd ymm0,ymm0,ymm0
   5:	c4 e2 75 02 c9       	vphaddd ymm1,ymm1,ymm1
   a:	c4 e2 6d 02 d2       	vphaddd ymm2,ymm2,ymm2
   f:	c4 e2 65 02 db       	vphaddd ymm3,ymm3,ymm3
  14:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  1b:	0f 1f 84 00 00 00 00 
  22:	00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM3, YMM3, YMM3

Show nanoBench command
Results:
- Instructions retired: 5.1
- Core cycles: 8.01
- Reference cycles: 7.13
- UOPS_EXECUTED.THREAD: 12.05
- RETIRE_SLOTS: 13.05
- UOPS_MITE: 1.17
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.99
- UOPS_PORT_1: 2.01
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.34

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 e2 7d 02 c0       	vphaddd ymm0,ymm0,ymm0
   5:	c4 e2 75 02 c9       	vphaddd ymm1,ymm1,ymm1
   a:	c4 e2 6d 02 d2       	vphaddd ymm2,ymm2,ymm2
   f:	c4 e2 65 02 db       	vphaddd ymm3,ymm3,ymm3
  14:	c4 e2 5d 02 e4       	vphaddd ymm4,ymm4,ymm4
  19:	c4 e2 55 02 ed       	vphaddd ymm5,ymm5,ymm5
  1e:	c4 e2 4d 02 f6       	vphaddd ymm6,ymm6,ymm6
  23:	c4 e2 45 02 ff       	vphaddd ymm7,ymm7,ymm7

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM3, YMM3, YMM3;
VXORPS YMM4, YMM4, YMM4;
VXORPS YMM5, YMM5, YMM5;
VXORPS YMM6, YMM6, YMM6;
VXORPS YMM7, YMM7, YMM7

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 16.0
- Reference cycles: 14.63
- UOPS_EXECUTED.THREAD: 24.0
- RETIRE_SLOTS: 24.0
- UOPS_MITE: 24.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.98
- UOPS_PORT_1: 4.02
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 e2 7d 02 c0       	vphaddd ymm0,ymm0,ymm0
   5:	c4 e2 75 02 c9       	vphaddd ymm1,ymm1,ymm1
   a:	c4 e2 6d 02 d2       	vphaddd ymm2,ymm2,ymm2
   f:	c4 e2 65 02 db       	vphaddd ymm3,ymm3,ymm3
  14:	c4 e2 5d 02 e4       	vphaddd ymm4,ymm4,ymm4
  19:	c4 e2 55 02 ed       	vphaddd ymm5,ymm5,ymm5
  1e:	c4 e2 4d 02 f6       	vphaddd ymm6,ymm6,ymm6
  23:	c4 e2 45 02 ff       	vphaddd ymm7,ymm7,ymm7

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM3, YMM3, YMM3;
VXORPS YMM4, YMM4, YMM4;
VXORPS YMM5, YMM5, YMM5;
VXORPS YMM6, YMM6, YMM6;
VXORPS YMM7, YMM7, YMM7

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 16.01
- Reference cycles: 14.21
- UOPS_EXECUTED.THREAD: 25.0
- RETIRE_SLOTS: 25.0
- UOPS_MITE: 25.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.99
- UOPS_PORT_1: 4.02
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.02

With loop_count=1000, unroll_count=1, and padding (long NOPs)

Code:

   0:	c4 e2 7d 02 c0       	vphaddd ymm0,ymm0,ymm0
   5:	c4 e2 75 02 c9       	vphaddd ymm1,ymm1,ymm1
   a:	c4 e2 6d 02 d2       	vphaddd ymm2,ymm2,ymm2
   f:	c4 e2 65 02 db       	vphaddd ymm3,ymm3,ymm3
  14:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  1b:	0f 1f 84 00 00 00 00 
  22:	00 
  23:	c4 e2 5d 02 e4       	vphaddd ymm4,ymm4,ymm4
  28:	c4 e2 55 02 ed       	vphaddd ymm5,ymm5,ymm5
  2d:	c4 e2 4d 02 f6       	vphaddd ymm6,ymm6,ymm6
  32:	c4 e2 45 02 ff       	vphaddd ymm7,ymm7,ymm7
  37:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  3e:	0f 1f 84 00 00 00 00 
  45:	00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM3, YMM3, YMM3;
VXORPS YMM4, YMM4, YMM4;
VXORPS YMM5, YMM5, YMM5;
VXORPS YMM6, YMM6, YMM6;
VXORPS YMM7, YMM7, YMM7

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 16.01
- Reference cycles: 14.25
- UOPS_EXECUTED.THREAD: 25.0
- RETIRE_SLOTS: 27.0
- UOPS_MITE: 0.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.95
- UOPS_PORT_1: 4.05
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	c4 e2 7d 02 c0       	vphaddd ymm0,ymm0,ymm0
   5:	c4 e2 75 02 c9       	vphaddd ymm1,ymm1,ymm1
   a:	c4 e2 6d 02 d2       	vphaddd ymm2,ymm2,ymm2
   f:	c4 e2 65 02 db       	vphaddd ymm3,ymm3,ymm3
  14:	c4 e2 5d 02 e4       	vphaddd ymm4,ymm4,ymm4
  19:	c4 e2 55 02 ed       	vphaddd ymm5,ymm5,ymm5
  1e:	c4 e2 4d 02 f6       	vphaddd ymm6,ymm6,ymm6
  23:	c4 e2 45 02 ff       	vphaddd ymm7,ymm7,ymm7

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM3, YMM3, YMM3;
VXORPS YMM4, YMM4, YMM4;
VXORPS YMM5, YMM5, YMM5;
VXORPS YMM6, YMM6, YMM6;
VXORPS YMM7, YMM7, YMM7

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 16.01
- Reference cycles: 14.23
- UOPS_EXECUTED.THREAD: 24.1
- RETIRE_SLOTS: 24.1
- UOPS_MITE: 24.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 4.01
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.02

With loop_count=100, unroll_count=10, and padding (long NOPs)

Code:

   0:	c4 e2 7d 02 c0       	vphaddd ymm0,ymm0,ymm0
   5:	c4 e2 75 02 c9       	vphaddd ymm1,ymm1,ymm1
   a:	c4 e2 6d 02 d2       	vphaddd ymm2,ymm2,ymm2
   f:	c4 e2 65 02 db       	vphaddd ymm3,ymm3,ymm3
  14:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  1b:	0f 1f 84 00 00 00 00 
  22:	00 
  23:	c4 e2 5d 02 e4       	vphaddd ymm4,ymm4,ymm4
  28:	c4 e2 55 02 ed       	vphaddd ymm5,ymm5,ymm5
  2d:	c4 e2 4d 02 f6       	vphaddd ymm6,ymm6,ymm6
  32:	c4 e2 45 02 ff       	vphaddd ymm7,ymm7,ymm7
  37:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  3e:	0f 1f 84 00 00 00 00 
  45:	00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM3, YMM3, YMM3;
VXORPS YMM4, YMM4, YMM4;
VXORPS YMM5, YMM5, YMM5;
VXORPS YMM6, YMM6, YMM6;
VXORPS YMM7, YMM7, YMM7

Show nanoBench command
Results:
- Instructions retired: 10.2
- Core cycles: 16.01
- Reference cycles: 14.28
- UOPS_EXECUTED.THREAD: 24.1
- RETIRE_SLOTS: 26.1
- UOPS_MITE: 2.34
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.98
- UOPS_PORT_1: 4.02
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.67

With 13 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 e2 7d 02 c0       	vphaddd ymm0,ymm0,ymm0
   5:	c4 e2 75 02 c9       	vphaddd ymm1,ymm1,ymm1
   a:	c4 e2 6d 02 d2       	vphaddd ymm2,ymm2,ymm2
   f:	c4 e2 65 02 db       	vphaddd ymm3,ymm3,ymm3
  14:	c4 e2 5d 02 e4       	vphaddd ymm4,ymm4,ymm4
  19:	c4 e2 55 02 ed       	vphaddd ymm5,ymm5,ymm5
  1e:	c4 e2 4d 02 f6       	vphaddd ymm6,ymm6,ymm6
  23:	c4 e2 45 02 ff       	vphaddd ymm7,ymm7,ymm7
  28:	c4 42 3d 02 c0       	vphaddd ymm8,ymm8,ymm8
  2d:	c4 42 35 02 c9       	vphaddd ymm9,ymm9,ymm9
  32:	c4 42 2d 02 d2       	vphaddd ymm10,ymm10,ymm10
  37:	c4 42 25 02 db       	vphaddd ymm11,ymm11,ymm11
  3c:	c4 42 1d 02 e4       	vphaddd ymm12,ymm12,ymm12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM3, YMM3, YMM3;
VXORPS YMM4, YMM4, YMM4;
VXORPS YMM5, YMM5, YMM5;
VXORPS YMM6, YMM6, YMM6;
VXORPS YMM7, YMM7, YMM7;
VXORPS YMM8, YMM8, YMM8;
VXORPS YMM9, YMM9, YMM9;
VXORPS YMM10, YMM10, YMM10;
VXORPS YMM11, YMM11, YMM11;
VXORPS YMM12, YMM12, YMM12

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 26.0
- Reference cycles: 23.05
- UOPS_EXECUTED.THREAD: 39.0
- RETIRE_SLOTS: 39.0
- UOPS_MITE: 39.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 6.48
- UOPS_PORT_1: 6.52
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 26.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 13.0

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 e2 7d 02 c0       	vphaddd ymm0,ymm0,ymm0
   5:	c4 e2 75 02 c9       	vphaddd ymm1,ymm1,ymm1
   a:	c4 e2 6d 02 d2       	vphaddd ymm2,ymm2,ymm2
   f:	c4 e2 65 02 db       	vphaddd ymm3,ymm3,ymm3
  14:	c4 e2 5d 02 e4       	vphaddd ymm4,ymm4,ymm4
  19:	c4 e2 55 02 ed       	vphaddd ymm5,ymm5,ymm5
  1e:	c4 e2 4d 02 f6       	vphaddd ymm6,ymm6,ymm6
  23:	c4 e2 45 02 ff       	vphaddd ymm7,ymm7,ymm7
  28:	c4 42 3d 02 c0       	vphaddd ymm8,ymm8,ymm8
  2d:	c4 42 35 02 c9       	vphaddd ymm9,ymm9,ymm9
  32:	c4 42 2d 02 d2       	vphaddd ymm10,ymm10,ymm10
  37:	c4 42 25 02 db       	vphaddd ymm11,ymm11,ymm11
  3c:	c4 42 1d 02 e4       	vphaddd ymm12,ymm12,ymm12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM3, YMM3, YMM3;
VXORPS YMM4, YMM4, YMM4;
VXORPS YMM5, YMM5, YMM5;
VXORPS YMM6, YMM6, YMM6;
VXORPS YMM7, YMM7, YMM7;
VXORPS YMM8, YMM8, YMM8;
VXORPS YMM9, YMM9, YMM9;
VXORPS YMM10, YMM10, YMM10;
VXORPS YMM11, YMM11, YMM11;
VXORPS YMM12, YMM12, YMM12

Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 26.01
- Reference cycles: 23.1
- UOPS_EXECUTED.THREAD: 40.0
- RETIRE_SLOTS: 40.0
- UOPS_MITE: 40.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 6.51
- UOPS_PORT_1: 6.49
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 26.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 13.02

With loop_count=1000, unroll_count=1, and padding (long NOPs)

Code:

   0:	c4 e2 7d 02 c0       	vphaddd ymm0,ymm0,ymm0
   5:	c4 e2 75 02 c9       	vphaddd ymm1,ymm1,ymm1
   a:	c4 e2 6d 02 d2       	vphaddd ymm2,ymm2,ymm2
   f:	c4 e2 65 02 db       	vphaddd ymm3,ymm3,ymm3
  14:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  1b:	0f 1f 84 00 00 00 00 
  22:	00 
  23:	c4 e2 5d 02 e4       	vphaddd ymm4,ymm4,ymm4
  28:	c4 e2 55 02 ed       	vphaddd ymm5,ymm5,ymm5
  2d:	c4 e2 4d 02 f6       	vphaddd ymm6,ymm6,ymm6
  32:	c4 e2 45 02 ff       	vphaddd ymm7,ymm7,ymm7
  37:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  3e:	0f 1f 84 00 00 00 00 
  45:	00 
  46:	c4 42 3d 02 c0       	vphaddd ymm8,ymm8,ymm8
  4b:	c4 42 35 02 c9       	vphaddd ymm9,ymm9,ymm9
  50:	c4 42 2d 02 d2       	vphaddd ymm10,ymm10,ymm10
  55:	c4 42 25 02 db       	vphaddd ymm11,ymm11,ymm11
  5a:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  61:	0f 1f 84 00 00 00 00 
  68:	00 
  69:	c4 42 1d 02 e4       	vphaddd ymm12,ymm12,ymm12
  6e:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  75:	0f 1f 84 00 00 00 00 
  7c:	00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM3, YMM3, YMM3;
VXORPS YMM4, YMM4, YMM4;
VXORPS YMM5, YMM5, YMM5;
VXORPS YMM6, YMM6, YMM6;
VXORPS YMM7, YMM7, YMM7;
VXORPS YMM8, YMM8, YMM8;
VXORPS YMM9, YMM9, YMM9;
VXORPS YMM10, YMM10, YMM10;
VXORPS YMM11, YMM11, YMM11;
VXORPS YMM12, YMM12, YMM12

Show nanoBench command
Results:
- Instructions retired: 19.0
- Core cycles: 26.01
- Reference cycles: 23.08
- UOPS_EXECUTED.THREAD: 41.0
- RETIRE_SLOTS: 45.0
- UOPS_MITE: 0.05
- UOPS_MS: 0.0
- UOPS_PORT_0: 6.47
- UOPS_PORT_1: 6.53
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 26.0
- UOPS_PORT_6: 2.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	c4 e2 7d 02 c0       	vphaddd ymm0,ymm0,ymm0
   5:	c4 e2 75 02 c9       	vphaddd ymm1,ymm1,ymm1
   a:	c4 e2 6d 02 d2       	vphaddd ymm2,ymm2,ymm2
   f:	c4 e2 65 02 db       	vphaddd ymm3,ymm3,ymm3
  14:	c4 e2 5d 02 e4       	vphaddd ymm4,ymm4,ymm4
  19:	c4 e2 55 02 ed       	vphaddd ymm5,ymm5,ymm5
  1e:	c4 e2 4d 02 f6       	vphaddd ymm6,ymm6,ymm6
  23:	c4 e2 45 02 ff       	vphaddd ymm7,ymm7,ymm7
  28:	c4 42 3d 02 c0       	vphaddd ymm8,ymm8,ymm8
  2d:	c4 42 35 02 c9       	vphaddd ymm9,ymm9,ymm9
  32:	c4 42 2d 02 d2       	vphaddd ymm10,ymm10,ymm10
  37:	c4 42 25 02 db       	vphaddd ymm11,ymm11,ymm11
  3c:	c4 42 1d 02 e4       	vphaddd ymm12,ymm12,ymm12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM3, YMM3, YMM3;
VXORPS YMM4, YMM4, YMM4;
VXORPS YMM5, YMM5, YMM5;
VXORPS YMM6, YMM6, YMM6;
VXORPS YMM7, YMM7, YMM7;
VXORPS YMM8, YMM8, YMM8;
VXORPS YMM9, YMM9, YMM9;
VXORPS YMM10, YMM10, YMM10;
VXORPS YMM11, YMM11, YMM11;
VXORPS YMM12, YMM12, YMM12

Show nanoBench command
Results:
- Instructions retired: 13.2
- Core cycles: 26.01
- Reference cycles: 23.78
- UOPS_EXECUTED.THREAD: 39.1
- RETIRE_SLOTS: 39.1
- UOPS_MITE: 39.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 6.5
- UOPS_PORT_1: 6.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 26.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 13.02

With loop_count=100, unroll_count=10, and padding (long NOPs)

Code:

   0:	c4 e2 7d 02 c0       	vphaddd ymm0,ymm0,ymm0
   5:	c4 e2 75 02 c9       	vphaddd ymm1,ymm1,ymm1
   a:	c4 e2 6d 02 d2       	vphaddd ymm2,ymm2,ymm2
   f:	c4 e2 65 02 db       	vphaddd ymm3,ymm3,ymm3
  14:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  1b:	0f 1f 84 00 00 00 00 
  22:	00 
  23:	c4 e2 5d 02 e4       	vphaddd ymm4,ymm4,ymm4
  28:	c4 e2 55 02 ed       	vphaddd ymm5,ymm5,ymm5
  2d:	c4 e2 4d 02 f6       	vphaddd ymm6,ymm6,ymm6
  32:	c4 e2 45 02 ff       	vphaddd ymm7,ymm7,ymm7
  37:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  3e:	0f 1f 84 00 00 00 00 
  45:	00 
  46:	c4 42 3d 02 c0       	vphaddd ymm8,ymm8,ymm8
  4b:	c4 42 35 02 c9       	vphaddd ymm9,ymm9,ymm9
  50:	c4 42 2d 02 d2       	vphaddd ymm10,ymm10,ymm10
  55:	c4 42 25 02 db       	vphaddd ymm11,ymm11,ymm11
  5a:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  61:	0f 1f 84 00 00 00 00 
  68:	00 
  69:	c4 42 1d 02 e4       	vphaddd ymm12,ymm12,ymm12
  6e:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  75:	0f 1f 84 00 00 00 00 
  7c:	00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM3, YMM3, YMM3;
VXORPS YMM4, YMM4, YMM4;
VXORPS YMM5, YMM5, YMM5;
VXORPS YMM6, YMM6, YMM6;
VXORPS YMM7, YMM7, YMM7;
VXORPS YMM8, YMM8, YMM8;
VXORPS YMM9, YMM9, YMM9;
VXORPS YMM10, YMM10, YMM10;
VXORPS YMM11, YMM11, YMM11;
VXORPS YMM12, YMM12, YMM12

Show nanoBench command
Results:
- Instructions retired: 17.2
- Core cycles: 26.01
- Reference cycles: 23.78
- UOPS_EXECUTED.THREAD: 39.1
- RETIRE_SLOTS: 43.1
- UOPS_MITE: 0.43
- UOPS_MS: 0.0
- UOPS_PORT_0: 6.44
- UOPS_PORT_1: 6.56
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 26.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.13

VPHADDD (YMM, YMM, YMM) - Throughput and Uops

With different registers for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=1000, unroll_count=10, and padding (long NOPs)

With loop_count=100 and unroll_count=100

With loop_count=100, unroll_count=100, and padding (long NOPs)

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=1000, unroll_count=2, and padding (long NOPs)

With loop_count=100 and unroll_count=20

With loop_count=100, unroll_count=20, and padding (long NOPs)

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (long NOPs)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (long NOPs)

With 11 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (long NOPs)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (long NOPs)

With the same register for for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=1000, unroll_count=10, and padding (long NOPs)

With loop_count=100 and unroll_count=100

With loop_count=100, unroll_count=100, and padding (long NOPs)

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=1000, unroll_count=2, and padding (long NOPs)

With loop_count=100 and unroll_count=20

With loop_count=100, unroll_count=20, and padding (long NOPs)

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (long NOPs)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (long NOPs)

With 13 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (long NOPs)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (long NOPs)