MOVSXD (R64, M32)

With unroll_count=500 and no inner loop

Code:

   0:	4d 63 06             	movsxd r8,DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 0.5
- Reference cycles: 0.4
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	4d 63 06             	movsxd r8,DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 0.5
- Reference cycles: 0.44
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 1.11
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.3

With loop_count=100 and unroll_count=100

Code:

   0:	4d 63 06             	movsxd r8,DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 0.5
- Reference cycles: 0.45
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	4d 63 06             	movsxd r8,DWORD PTR [r14]
   3:	4d 63 4e 04          	movsxd r9,DWORD PTR [r14+0x4]
   7:	4d 63 56 08          	movsxd r10,DWORD PTR [r14+0x8]
   b:	4d 63 5e 0c          	movsxd r11,DWORD PTR [r14+0xc]

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 2.0
- Reference cycles: 1.44
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	4d 63 06             	movsxd r8,DWORD PTR [r14]
   3:	4d 63 4e 04          	movsxd r9,DWORD PTR [r14+0x4]
   7:	4d 63 56 08          	movsxd r10,DWORD PTR [r14+0x8]
   b:	4d 63 5e 0c          	movsxd r11,DWORD PTR [r14+0xc]

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 2.01
- Reference cycles: 1.8
- UOPS_EXECUTED.THREAD: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 4.53
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.51

With loop_count=100 and unroll_count=20

Code:

   0:	4d 63 06             	movsxd r8,DWORD PTR [r14]
   3:	4d 63 4e 04          	movsxd r9,DWORD PTR [r14+0x4]
   7:	4d 63 56 08          	movsxd r10,DWORD PTR [r14+0x8]
   b:	4d 63 5e 0c          	movsxd r11,DWORD PTR [r14+0xc]

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 2.01
- Reference cycles: 1.8
- UOPS_EXECUTED.THREAD: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	4d 63 06             	movsxd r8,DWORD PTR [r14]
   3:	4d 63 4e 04          	movsxd r9,DWORD PTR [r14+0x4]
   7:	4d 63 56 08          	movsxd r10,DWORD PTR [r14+0x8]
   b:	4d 63 5e 0c          	movsxd r11,DWORD PTR [r14+0xc]
   f:	4d 63 66 10          	movsxd r12,DWORD PTR [r14+0x10]
  13:	49 63 5e 14          	movsxd rbx,DWORD PTR [r14+0x14]
  17:	49 63 4e 18          	movsxd rcx,DWORD PTR [r14+0x18]
  1b:	49 63 56 1c          	movsxd rdx,DWORD PTR [r14+0x1c]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 4.0
- Reference cycles: 3.77
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

Code:

   0:	4d 63 06             	movsxd r8,DWORD PTR [r14]
   3:	4d 63 4e 04          	movsxd r9,DWORD PTR [r14+0x4]
   7:	4d 63 56 08          	movsxd r10,DWORD PTR [r14+0x8]
   b:	4d 63 5e 0c          	movsxd r11,DWORD PTR [r14+0xc]
   f:	4d 63 66 10          	movsxd r12,DWORD PTR [r14+0x10]
  13:	49 63 5e 14          	movsxd rbx,DWORD PTR [r14+0x14]
  17:	49 63 4e 18          	movsxd rcx,DWORD PTR [r14+0x18]
  1b:	49 63 56 1c          	movsxd rdx,DWORD PTR [r14+0x1c]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 4.02
- Reference cycles: 3.61
- UOPS_EXECUTED.THREAD: 9.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 9.05
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 3.02

With loop_count=100 and unroll_count=10

Code:

   0:	4d 63 06             	movsxd r8,DWORD PTR [r14]
   3:	4d 63 4e 04          	movsxd r9,DWORD PTR [r14+0x4]
   7:	4d 63 56 08          	movsxd r10,DWORD PTR [r14+0x8]
   b:	4d 63 5e 0c          	movsxd r11,DWORD PTR [r14+0xc]
   f:	4d 63 66 10          	movsxd r12,DWORD PTR [r14+0x10]
  13:	49 63 5e 14          	movsxd rbx,DWORD PTR [r14+0x14]
  17:	49 63 4e 18          	movsxd rcx,DWORD PTR [r14+0x18]
  1b:	49 63 56 1c          	movsxd rdx,DWORD PTR [r14+0x1c]

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 4.02
- Reference cycles: 3.61
- UOPS_EXECUTED.THREAD: 8.1
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	4f 63 04 2e          	movsxd r8,DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 0.5
- Reference cycles: 0.31
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	4f 63 04 2e          	movsxd r8,DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 0.5
- Reference cycles: 0.45
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	4f 63 04 2e          	movsxd r8,DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 0.5
- Reference cycles: 0.44
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	4f 63 04 2e          	movsxd r8,DWORD PTR [r14+r13*1]
   4:	4f 63 4c 2e 04       	movsxd r9,DWORD PTR [r14+r13*1+0x4]
   9:	4f 63 54 2e 08       	movsxd r10,DWORD PTR [r14+r13*1+0x8]
   e:	4f 63 5c 2e 0c       	movsxd r11,DWORD PTR [r14+r13*1+0xc]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 2.0
- Reference cycles: 1.77
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	4f 63 04 2e          	movsxd r8,DWORD PTR [r14+r13*1]
   4:	4f 63 4c 2e 04       	movsxd r9,DWORD PTR [r14+r13*1+0x4]
   9:	4f 63 54 2e 08       	movsxd r10,DWORD PTR [r14+r13*1+0x8]
   e:	4f 63 5c 2e 0c       	movsxd r11,DWORD PTR [r14+r13*1+0xc]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 2.01
- Reference cycles: 1.75
- UOPS_EXECUTED.THREAD: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	4f 63 04 2e          	movsxd r8,DWORD PTR [r14+r13*1]
   4:	4f 63 4c 2e 04       	movsxd r9,DWORD PTR [r14+r13*1+0x4]
   9:	4f 63 54 2e 08       	movsxd r10,DWORD PTR [r14+r13*1+0x8]
   e:	4f 63 5c 2e 0c       	movsxd r11,DWORD PTR [r14+r13*1+0xc]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 2.01
- Reference cycles: 1.8
- UOPS_EXECUTED.THREAD: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.68
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.21

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	4f 63 04 2e          	movsxd r8,DWORD PTR [r14+r13*1]
   4:	4f 63 4c 2e 04       	movsxd r9,DWORD PTR [r14+r13*1+0x4]
   9:	4f 63 54 2e 08       	movsxd r10,DWORD PTR [r14+r13*1+0x8]
   e:	4f 63 5c 2e 0c       	movsxd r11,DWORD PTR [r14+r13*1+0xc]
  13:	4f 63 64 2e 10       	movsxd r12,DWORD PTR [r14+r13*1+0x10]
  18:	4b 63 5c 2e 14       	movsxd rbx,DWORD PTR [r14+r13*1+0x14]
  1d:	4b 63 4c 2e 18       	movsxd rcx,DWORD PTR [r14+r13*1+0x18]
  22:	4b 63 54 2e 1c       	movsxd rdx,DWORD PTR [r14+r13*1+0x1c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 3.99
- Reference cycles: 3.55
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

Code:

   0:	4f 63 04 2e          	movsxd r8,DWORD PTR [r14+r13*1]
   4:	4f 63 4c 2e 04       	movsxd r9,DWORD PTR [r14+r13*1+0x4]
   9:	4f 63 54 2e 08       	movsxd r10,DWORD PTR [r14+r13*1+0x8]
   e:	4f 63 5c 2e 0c       	movsxd r11,DWORD PTR [r14+r13*1+0xc]
  13:	4f 63 64 2e 10       	movsxd r12,DWORD PTR [r14+r13*1+0x10]
  18:	4b 63 5c 2e 14       	movsxd rbx,DWORD PTR [r14+r13*1+0x14]
  1d:	4b 63 4c 2e 18       	movsxd rcx,DWORD PTR [r14+r13*1+0x18]
  22:	4b 63 54 2e 1c       	movsxd rdx,DWORD PTR [r14+r13*1+0x1c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 4.02
- Reference cycles: 3.55
- UOPS_EXECUTED.THREAD: 9.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	4f 63 04 2e          	movsxd r8,DWORD PTR [r14+r13*1]
   4:	4f 63 4c 2e 04       	movsxd r9,DWORD PTR [r14+r13*1+0x4]
   9:	4f 63 54 2e 08       	movsxd r10,DWORD PTR [r14+r13*1+0x8]
   e:	4f 63 5c 2e 0c       	movsxd r11,DWORD PTR [r14+r13*1+0xc]
  13:	4f 63 64 2e 10       	movsxd r12,DWORD PTR [r14+r13*1+0x10]
  18:	4b 63 5c 2e 14       	movsxd rbx,DWORD PTR [r14+r13*1+0x14]
  1d:	4b 63 4c 2e 18       	movsxd rcx,DWORD PTR [r14+r13*1+0x18]
  22:	4b 63 54 2e 1c       	movsxd rdx,DWORD PTR [r14+r13*1+0x1c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 4.02
- Reference cycles: 3.61
- UOPS_EXECUTED.THREAD: 8.1
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

MOVSXD (R64, M32) - Throughput and Uops

With a non-indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10