IMUL (R64, R64) - Throughput and Uops

With unroll_count=500 and no inner loop

• Code:

     0:	4d 0f af c1          	imul   r8,r9
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.0
  • Core cycles: 3.0
  • Reference cycles: 2.66
  • UOPS_EXECUTED.THREAD: 1.0
  • RETIRE_SLOTS: 1.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

• Code:

     0:	4d 0f af c1          	imul   r8,r9
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.2
  • Core cycles: 3.0
  • Reference cycles: 2.66
  • UOPS_EXECUTED.THREAD: 1.1
  • RETIRE_SLOTS: 1.1
  • UOPS_MITE: 0.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.1
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

• Code:

     0:	4d 0f af c1          	imul   r8,r9
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.02
  • Core cycles: 3.0
  • Reference cycles: 2.66
  • UOPS_EXECUTED.THREAD: 1.01
  • RETIRE_SLOTS: 1.01
  • UOPS_MITE: 0.01
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.01
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With unroll_count=200 and no inner loop

• Code:

     0:	4d 0f af c1          	imul   r8,r9
     4:	4d 0f af d1          	imul   r10,r9
     8:	4d 0f af d9          	imul   r11,r9
     c:	4d 0f af e1          	imul   r12,r9
  

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 4.0
  • Reference cycles: 3.66
  • UOPS_EXECUTED.THREAD: 4.0
  • RETIRE_SLOTS: 4.0
  • UOPS_MITE: 4.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 4.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

• Code:

     0:	4d 0f af c1          	imul   r8,r9
     4:	4d 0f af d1          	imul   r10,r9
     8:	4d 0f af d9          	imul   r11,r9
     c:	4d 0f af e1          	imul   r12,r9
  

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 4.0
  • Reference cycles: 3.54
  • UOPS_EXECUTED.THREAD: 4.5
  • RETIRE_SLOTS: 4.5
  • UOPS_MITE: 0.04
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 4.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.5
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=20

• Code:

     0:	4d 0f af c1          	imul   r8,r9
     4:	4d 0f af d1          	imul   r10,r9
     8:	4d 0f af d9          	imul   r11,r9
     c:	4d 0f af e1          	imul   r12,r9
  

• Show nanoBench command
• Results:
  • Instructions retired: 4.1
  • Core cycles: 4.0
  • Reference cycles: 3.55
  • UOPS_EXECUTED.THREAD: 4.05
  • RETIRE_SLOTS: 4.05
  • UOPS_MITE: 0.04
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 4.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.05
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With unroll_count=100 and no inner loop

• Code:

     0:	4d 0f af c1          	imul   r8,r9
     4:	4d 0f af d1          	imul   r10,r9
     8:	4d 0f af d9          	imul   r11,r9
     c:	4d 0f af e1          	imul   r12,r9
    10:	4d 0f af e9          	imul   r13,r9
    14:	4d 0f af f1          	imul   r14,r9
    18:	49 0f af d9          	imul   rbx,r9
    1c:	49 0f af c9          	imul   rcx,r9
  

• Show nanoBench command
• Results:
  • Instructions retired: 8.0
  • Core cycles: 8.0
  • Reference cycles: 7.32
  • UOPS_EXECUTED.THREAD: 8.0
  • RETIRE_SLOTS: 8.0
  • UOPS_MITE: 8.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 8.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	4d 0f af c1          	imul   r8,r9
     4:	4d 0f af d1          	imul   r10,r9
     8:	4d 0f af d9          	imul   r11,r9
     c:	4d 0f af e1          	imul   r12,r9
    10:	4d 0f af e9          	imul   r13,r9
    14:	4d 0f af f1          	imul   r14,r9
    18:	49 0f af d9          	imul   rbx,r9
    1c:	49 0f af c9          	imul   rcx,r9
  

• Show nanoBench command
• Results:
  • Instructions retired: 10.0
  • Core cycles: 8.01
  • Reference cycles: 7.09
  • UOPS_EXECUTED.THREAD: 9.0
  • RETIRE_SLOTS: 9.0
  • UOPS_MITE: 0.09
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 8.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.03

With loop_count=100 and unroll_count=10

• Code:

     0:	4d 0f af c1          	imul   r8,r9
     4:	4d 0f af d1          	imul   r10,r9
     8:	4d 0f af d9          	imul   r11,r9
     c:	4d 0f af e1          	imul   r12,r9
    10:	4d 0f af e9          	imul   r13,r9
    14:	4d 0f af f1          	imul   r14,r9
    18:	49 0f af d9          	imul   rbx,r9
    1c:	49 0f af c9          	imul   rcx,r9
  

• Show nanoBench command
• Results:
  • Instructions retired: 8.2
  • Core cycles: 8.01
  • Reference cycles: 7.07
  • UOPS_EXECUTED.THREAD: 8.1
  • RETIRE_SLOTS: 8.1
  • UOPS_MITE: 0.08
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 8.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.1
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.02

With unroll_count=100 and no inner loop

• Code:

     0:	4d 0f af c1          	imul   r8,r9
     4:	4d 0f af d1          	imul   r10,r9
     8:	4d 0f af d9          	imul   r11,r9
     c:	4d 0f af e1          	imul   r12,r9
    10:	4d 0f af e9          	imul   r13,r9
    14:	4d 0f af f1          	imul   r14,r9
    18:	49 0f af d9          	imul   rbx,r9
    1c:	49 0f af c9          	imul   rcx,r9
    20:	49 0f af d1          	imul   rdx,r9
    24:	49 0f af f9          	imul   rdi,r9
    28:	49 0f af f1          	imul   rsi,r9
    2c:	49 0f af e9          	imul   rbp,r9
  

• Show nanoBench command
• Results:
  • Instructions retired: 12.0
  • Core cycles: 12.0
  • Reference cycles: 10.64
  • UOPS_EXECUTED.THREAD: 12.0
  • RETIRE_SLOTS: 12.0
  • UOPS_MITE: 12.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 12.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 3.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	4d 0f af c1          	imul   r8,r9
     4:	4d 0f af d1          	imul   r10,r9
     8:	4d 0f af d9          	imul   r11,r9
     c:	4d 0f af e1          	imul   r12,r9
    10:	4d 0f af e9          	imul   r13,r9
    14:	4d 0f af f1          	imul   r14,r9
    18:	49 0f af d9          	imul   rbx,r9
    1c:	49 0f af c9          	imul   rcx,r9
    20:	49 0f af d1          	imul   rdx,r9
    24:	49 0f af f9          	imul   rdi,r9
    28:	49 0f af f1          	imul   rsi,r9
    2c:	49 0f af e9          	imul   rbp,r9
  

• Show nanoBench command
• Results:
  • Instructions retired: 14.0
  • Core cycles: 12.01
  • Reference cycles: 10.66
  • UOPS_EXECUTED.THREAD: 13.0
  • RETIRE_SLOTS: 13.0
  • UOPS_MITE: 0.01
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 12.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

• Code:

     0:	4d 0f af c1          	imul   r8,r9
     4:	4d 0f af d1          	imul   r10,r9
     8:	4d 0f af d9          	imul   r11,r9
     c:	4d 0f af e1          	imul   r12,r9
    10:	4d 0f af e9          	imul   r13,r9
    14:	4d 0f af f1          	imul   r14,r9
    18:	49 0f af d9          	imul   rbx,r9
    1c:	49 0f af c9          	imul   rcx,r9
    20:	49 0f af d1          	imul   rdx,r9
    24:	49 0f af f9          	imul   rdi,r9
    28:	49 0f af f1          	imul   rsi,r9
    2c:	49 0f af e9          	imul   rbp,r9
  

• Show nanoBench command
• Results:
  • Instructions retired: 12.2
  • Core cycles: 12.01
  • Reference cycles: 10.64
  • UOPS_EXECUTED.THREAD: 12.1
  • RETIRE_SLOTS: 12.1
  • UOPS_MITE: 0.13
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 12.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.1
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.03

With unroll_count=500 and no inner loop

• Code:

     0:	4d 0f af c0          	imul   r8,r8
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.0
  • Core cycles: 3.0
  • Reference cycles: 2.66
  • UOPS_EXECUTED.THREAD: 1.0
  • RETIRE_SLOTS: 1.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

• Code:

     0:	4d 0f af c0          	imul   r8,r8
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.2
  • Core cycles: 3.0
  • Reference cycles: 2.67
  • UOPS_EXECUTED.THREAD: 1.1
  • RETIRE_SLOTS: 1.1
  • UOPS_MITE: 0.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.1
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

• Code:

     0:	4d 0f af c0          	imul   r8,r8
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.02
  • Core cycles: 3.0
  • Reference cycles: 2.67
  • UOPS_EXECUTED.THREAD: 1.01
  • RETIRE_SLOTS: 1.01
  • UOPS_MITE: 0.01
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.01
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With unroll_count=200 and no inner loop

• Code:

     0:	4d 0f af c0          	imul   r8,r8
     4:	4d 0f af c9          	imul   r9,r9
     8:	4d 0f af d2          	imul   r10,r10
     c:	4d 0f af db          	imul   r11,r11
  

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 4.0
  • Reference cycles: 3.66
  • UOPS_EXECUTED.THREAD: 4.0
  • RETIRE_SLOTS: 4.0
  • UOPS_MITE: 4.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 4.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

• Code:

     0:	4d 0f af c0          	imul   r8,r8
     4:	4d 0f af c9          	imul   r9,r9
     8:	4d 0f af d2          	imul   r10,r10
     c:	4d 0f af db          	imul   r11,r11
  

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 4.0
  • Reference cycles: 3.54
  • UOPS_EXECUTED.THREAD: 4.5
  • RETIRE_SLOTS: 4.5
  • UOPS_MITE: 0.04
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 4.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.5
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=20

• Code:

     0:	4d 0f af c0          	imul   r8,r8
     4:	4d 0f af c9          	imul   r9,r9
     8:	4d 0f af d2          	imul   r10,r10
     c:	4d 0f af db          	imul   r11,r11
  

• Show nanoBench command
• Results:
  • Instructions retired: 4.1
  • Core cycles: 4.0
  • Reference cycles: 3.54
  • UOPS_EXECUTED.THREAD: 4.05
  • RETIRE_SLOTS: 4.05
  • UOPS_MITE: 0.04
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 4.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.05
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With unroll_count=100 and no inner loop

• Code:

     0:	4d 0f af c0          	imul   r8,r8
     4:	4d 0f af c9          	imul   r9,r9
     8:	4d 0f af d2          	imul   r10,r10
     c:	4d 0f af db          	imul   r11,r11
    10:	4d 0f af e4          	imul   r12,r12
    14:	4d 0f af ed          	imul   r13,r13
    18:	4d 0f af f6          	imul   r14,r14
    1c:	48 0f af db          	imul   rbx,rbx
  

• Show nanoBench command
• Results:
  • Instructions retired: 8.0
  • Core cycles: 8.0
  • Reference cycles: 6.43
  • UOPS_EXECUTED.THREAD: 8.0
  • RETIRE_SLOTS: 8.0
  • UOPS_MITE: 8.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 8.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	4d 0f af c0          	imul   r8,r8
     4:	4d 0f af c9          	imul   r9,r9
     8:	4d 0f af d2          	imul   r10,r10
     c:	4d 0f af db          	imul   r11,r11
    10:	4d 0f af e4          	imul   r12,r12
    14:	4d 0f af ed          	imul   r13,r13
    18:	4d 0f af f6          	imul   r14,r14
    1c:	48 0f af db          	imul   rbx,rbx
  

• Show nanoBench command
• Results:
  • Instructions retired: 10.0
  • Core cycles: 8.01
  • Reference cycles: 7.07
  • UOPS_EXECUTED.THREAD: 9.0
  • RETIRE_SLOTS: 9.0
  • UOPS_MITE: 0.09
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 8.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.03

With loop_count=100 and unroll_count=10

• Code:

     0:	4d 0f af c0          	imul   r8,r8
     4:	4d 0f af c9          	imul   r9,r9
     8:	4d 0f af d2          	imul   r10,r10
     c:	4d 0f af db          	imul   r11,r11
    10:	4d 0f af e4          	imul   r12,r12
    14:	4d 0f af ed          	imul   r13,r13
    18:	4d 0f af f6          	imul   r14,r14
    1c:	48 0f af db          	imul   rbx,rbx
  

• Show nanoBench command
• Results:
  • Instructions retired: 8.2
  • Core cycles: 8.01
  • Reference cycles: 7.09
  • UOPS_EXECUTED.THREAD: 8.1
  • RETIRE_SLOTS: 8.1
  • UOPS_MITE: 0.08
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 8.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.1
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.02

With unroll_count=100 and no inner loop

• Code:

     0:	4d 0f af c0          	imul   r8,r8
     4:	4d 0f af c9          	imul   r9,r9
     8:	4d 0f af d2          	imul   r10,r10
     c:	4d 0f af db          	imul   r11,r11
    10:	4d 0f af e4          	imul   r12,r12
    14:	4d 0f af ed          	imul   r13,r13
    18:	4d 0f af f6          	imul   r14,r14
    1c:	48 0f af db          	imul   rbx,rbx
    20:	48 0f af c9          	imul   rcx,rcx
    24:	48 0f af d2          	imul   rdx,rdx
    28:	48 0f af ff          	imul   rdi,rdi
    2c:	48 0f af f6          	imul   rsi,rsi
    30:	48 0f af ed          	imul   rbp,rbp
  

• Show nanoBench command
• Results:
  • Instructions retired: 13.0
  • Core cycles: 13.0
  • Reference cycles: 11.53
  • UOPS_EXECUTED.THREAD: 13.0
  • RETIRE_SLOTS: 13.0
  • UOPS_MITE: 13.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 13.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 3.25

With loop_count=1000 and unroll_count=1

• Code:

     0:	4d 0f af c0          	imul   r8,r8
     4:	4d 0f af c9          	imul   r9,r9
     8:	4d 0f af d2          	imul   r10,r10
     c:	4d 0f af db          	imul   r11,r11
    10:	4d 0f af e4          	imul   r12,r12
    14:	4d 0f af ed          	imul   r13,r13
    18:	4d 0f af f6          	imul   r14,r14
    1c:	48 0f af db          	imul   rbx,rbx
    20:	48 0f af c9          	imul   rcx,rcx
    24:	48 0f af d2          	imul   rdx,rdx
    28:	48 0f af ff          	imul   rdi,rdi
    2c:	48 0f af f6          	imul   rsi,rsi
    30:	48 0f af ed          	imul   rbp,rbp
  

• Show nanoBench command
• Results:
  • Instructions retired: 15.0
  • Core cycles: 13.01
  • Reference cycles: 11.57
  • UOPS_EXECUTED.THREAD: 14.0
  • RETIRE_SLOTS: 14.0
  • UOPS_MITE: 0.01
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 13.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

• Code:

     0:	4d 0f af c0          	imul   r8,r8
     4:	4d 0f af c9          	imul   r9,r9
     8:	4d 0f af d2          	imul   r10,r10
     c:	4d 0f af db          	imul   r11,r11
    10:	4d 0f af e4          	imul   r12,r12
    14:	4d 0f af ed          	imul   r13,r13
    18:	4d 0f af f6          	imul   r14,r14
    1c:	48 0f af db          	imul   rbx,rbx
    20:	48 0f af c9          	imul   rcx,rcx
    24:	48 0f af d2          	imul   rdx,rdx
    28:	48 0f af ff          	imul   rdi,rdi
    2c:	48 0f af f6          	imul   rsi,rsi
    30:	48 0f af ed          	imul   rbp,rbp
  

• Show nanoBench command
• Results:
  • Instructions retired: 13.2
  • Core cycles: 13.01
  • Reference cycles: 11.53
  • UOPS_EXECUTED.THREAD: 13.1
  • RETIRE_SLOTS: 13.1
  • UOPS_MITE: 0.13
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 13.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.1
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.03

With JB (Rel32)

• Code:

     0:	4d 0f af c1          	imul   r8,r9
     4:	0f 82 00 00 00 00    	jb     0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 3.05
  • Reference cycles: 2.66
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.01
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.52

With JB (Rel8)

• Code:

     0:	4d 0f af c1          	imul   r8,r9
     4:	72 00                	jb     0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 3.05
  • Reference cycles: 2.88
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.01
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.5

With JBE (Rel32)

• Code:

     0:	4d 0f af c1          	imul   r8,r9
     4:	0f 86 00 00 00 00    	jbe    0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 3.06
  • Reference cycles: 2.66
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.01
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.52

With JBE (Rel8)

• Code:

     0:	4d 0f af c1          	imul   r8,r9
     4:	76 00                	jbe    0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 3.06
  • Reference cycles: 3.1
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.01
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.5

With JL (Rel32)

• Code:

     0:	4d 0f af c1          	imul   r8,r9
     4:	0f 8c 00 00 00 00    	jl     0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 3.05
  • Reference cycles: 3.1
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.01
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.52

With JL (Rel8)

• Code:

     0:	4d 0f af c1          	imul   r8,r9
     4:	7c 00                	jl     0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 3.05
  • Reference cycles: 2.66
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.01
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.5

With JLE (Rel32)

• Code:

     0:	4d 0f af c1          	imul   r8,r9
     4:	0f 8e 00 00 00 00    	jle    0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 3.05
  • Reference cycles: 2.66
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.01
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.52

With JLE (Rel8)

• Code:

     0:	4d 0f af c1          	imul   r8,r9
     4:	7e 00                	jle    0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 3.05
  • Reference cycles: 2.66
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.01
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.5

With JNB (Rel32)

• Code:

     0:	4d 0f af c1          	imul   r8,r9
     4:	0f 83 00 00 00 00    	jae    0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 3.05
  • Reference cycles: 3.1
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.52
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.01
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.98
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.69

With JNB (Rel8)

• Code:

     0:	4d 0f af c1          	imul   r8,r9
     4:	73 00                	jae    0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 3.06
  • Reference cycles: 2.66
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.74
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.01
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.99
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.88

With JNBE (Rel32)

• Code:

     0:	4d 0f af c1          	imul   r8,r9
     4:	0f 87 00 00 00 00    	ja     0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 3.06
  • Reference cycles: 2.66
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.39
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.02
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.98
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.74

With JNBE (Rel8)

• Code:

     0:	4d 0f af c1          	imul   r8,r9
     4:	77 00                	ja     0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 3.07
  • Reference cycles: 2.66
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.71
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.01
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.99
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.86

With JNL (Rel32)

• Code:

     0:	4d 0f af c1          	imul   r8,r9
     4:	0f 8d 00 00 00 00    	jge    0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 3.06
  • Reference cycles: 2.66
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.29
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.01
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.99
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.7

With JNL (Rel8)

• Code:

     0:	4d 0f af c1          	imul   r8,r9
     4:	7d 00                	jge    0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 3.05
  • Reference cycles: 2.66
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.73
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.01
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.99
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.84

With JNLE (Rel32)

• Code:

     0:	4d 0f af c1          	imul   r8,r9
     4:	0f 8f 00 00 00 00    	jg     0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 3.06
  • Reference cycles: 2.44
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.41
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.01
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.98
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.74

With JNLE (Rel8)

• Code:

     0:	4d 0f af c1          	imul   r8,r9
     4:	7f 00                	jg     0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 3.06
  • Reference cycles: 2.66
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.6
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.02
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.99
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.8

With JNO (Rel32)

• Code:

     0:	4d 0f af c1          	imul   r8,r9
     4:	0f 81 00 00 00 00    	jno    0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 3.06
  • Reference cycles: 2.66
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.32
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.01
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.99
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.72

With JNO (Rel8)

• Code:

     0:	4d 0f af c1          	imul   r8,r9
     4:	71 00                	jno    0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 3.05
  • Reference cycles: 2.88
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.6
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.01
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.99
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.81

With JNP (Rel32)

• Code:

     0:	4d 0f af c1          	imul   r8,r9
     4:	0f 8b 00 00 00 00    	jnp    0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 3.05
  • Reference cycles: 2.88
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.01
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.52

With JNP (Rel8)

• Code:

     0:	4d 0f af c1          	imul   r8,r9
     4:	7b 00                	jnp    0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 3.05
  • Reference cycles: 2.66
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.01
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.5

With JNS (Rel32)

• Code:

     0:	4d 0f af c1          	imul   r8,r9
     4:	0f 89 00 00 00 00    	jns    0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 3.05
  • Reference cycles: 2.66
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.38
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.01
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.99
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.73

With JNS (Rel8)

• Code:

     0:	4d 0f af c1          	imul   r8,r9
     4:	79 00                	jns    0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 3.06
  • Reference cycles: 2.66
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.76
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.01
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.99
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.89

With JNZ (Rel32)

• Code:

     0:	4d 0f af c1          	imul   r8,r9
     4:	0f 85 00 00 00 00    	jne    0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 3.06
  • Reference cycles: 2.66
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.35
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.02
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.99
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.74

With JNZ (Rel8)

• Code:

     0:	4d 0f af c1          	imul   r8,r9
     4:	75 00                	jne    0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 3.06
  • Reference cycles: 2.66
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.76
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.01
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.98
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.88

With JO (Rel32)

• Code:

     0:	4d 0f af c1          	imul   r8,r9
     4:	0f 80 00 00 00 00    	jo     0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 3.05
  • Reference cycles: 2.66
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.01
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.52

With JO (Rel8)

• Code:

     0:	4d 0f af c1          	imul   r8,r9
     4:	70 00                	jo     0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 3.05
  • Reference cycles: 2.66
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.01
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.5

With JP (Rel32)

• Code:

     0:	4d 0f af c1          	imul   r8,r9
     4:	0f 8a 00 00 00 00    	jp     0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 3.06
  • Reference cycles: 2.66
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.4
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.02
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.98
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.74

With JP (Rel8)

• Code:

     0:	4d 0f af c1          	imul   r8,r9
     4:	7a 00                	jp     0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 3.05
  • Reference cycles: 2.66
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.67
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.01
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.99
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.86

With JS (Rel32)

• Code:

     0:	4d 0f af c1          	imul   r8,r9
     4:	0f 88 00 00 00 00    	js     0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 3.05
  • Reference cycles: 2.66
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.01
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.52

With JS (Rel8)

• Code:

     0:	4d 0f af c1          	imul   r8,r9
     4:	78 00                	js     0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 3.05
  • Reference cycles: 2.66
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.01
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.5

With JZ (Rel32)

• Code:

     0:	4d 0f af c1          	imul   r8,r9
     4:	0f 84 00 00 00 00    	je     0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 3.05
  • Reference cycles: 2.88
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.01
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.52

With JZ (Rel8)

• Code:

     0:	4d 0f af c1          	imul   r8,r9
     4:	74 00                	je     0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 3.05
  • Reference cycles: 2.66
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.01
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.5