ADD (M16, 0) - Throughput and Uops

With unroll_count=500 and no inner loop

• Code:

     0:	66 41 83 06 00       	add    WORD PTR [r14],0x0
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.0
  • Core cycles: 5.53
  • Reference cycles: 4.83
  • UOPS_EXECUTED.THREAD: 4.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.52
  • UOPS_PORT_1: 1.51
  • UOPS_PORT_2: 0.97
  • UOPS_PORT_3: 0.97
  • UOPS_PORT_4: 4.88
  • UOPS_PORT_5: 1.51
  • UOPS_PORT_6: 1.81
  • UOPS_PORT_7: 0.06
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

• Code:

     0:	66 41 83 06 00       	add    WORD PTR [r14],0x0
     5:	90                   	nop
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 5.49
  • Reference cycles: 4.79
  • UOPS_EXECUTED.THREAD: 4.0
  • RETIRE_SLOTS: 3.0
  • UOPS_MITE: 3.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.57
  • UOPS_PORT_1: 1.67
  • UOPS_PORT_2: 0.76
  • UOPS_PORT_3: 0.81
  • UOPS_PORT_4: 4.93
  • UOPS_PORT_5: 1.6
  • UOPS_PORT_6: 1.65
  • UOPS_PORT_7: 0.43
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

• Code:

     0:	66 41 83 06 00       	add    WORD PTR [r14],0x0
     5:	90                   	nop
     6:	90                   	nop
  

• Show nanoBench command
• Results:
  • Instructions retired: 3.0
  • Core cycles: 5.54
  • Reference cycles: 4.88
  • UOPS_EXECUTED.THREAD: 4.0
  • RETIRE_SLOTS: 4.0
  • UOPS_MITE: 4.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.66
  • UOPS_PORT_1: 1.66
  • UOPS_PORT_2: 0.69
  • UOPS_PORT_3: 0.73
  • UOPS_PORT_4: 4.93
  • UOPS_PORT_5: 1.77
  • UOPS_PORT_6: 1.22
  • UOPS_PORT_7: 0.58
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

• Code:

     0:	66 41 83 06 00       	add    WORD PTR [r14],0x0
     5:	90                   	nop
     6:	90                   	nop
     7:	90                   	nop
  

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 5.48
  • Reference cycles: 4.79
  • UOPS_EXECUTED.THREAD: 4.0
  • RETIRE_SLOTS: 5.0
  • UOPS_MITE: 5.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.53
  • UOPS_PORT_1: 1.53
  • UOPS_PORT_2: 0.7
  • UOPS_PORT_3: 0.78
  • UOPS_PORT_4: 4.91
  • UOPS_PORT_5: 1.56
  • UOPS_PORT_6: 1.58
  • UOPS_PORT_7: 0.54
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 4 NOPs

• Code:

     0:	66 41 83 06 00       	add    WORD PTR [r14],0x0
     5:	90                   	nop
     6:	90                   	nop
     7:	90                   	nop
     8:	90                   	nop
  

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 5.58
  • Reference cycles: 4.97
  • UOPS_EXECUTED.THREAD: 4.0
  • RETIRE_SLOTS: 6.0
  • UOPS_MITE: 6.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.47
  • UOPS_PORT_1: 1.56
  • UOPS_PORT_2: 0.91
  • UOPS_PORT_3: 1.05
  • UOPS_PORT_4: 4.93
  • UOPS_PORT_5: 1.57
  • UOPS_PORT_6: 1.56
  • UOPS_PORT_7: 0.03
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

• Code:

     0:	66 41 83 06 00       	add    WORD PTR [r14],0x0
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.2
  • Core cycles: 5.45
  • Reference cycles: 4.85
  • UOPS_EXECUTED.THREAD: 4.1
  • RETIRE_SLOTS: 2.1
  • UOPS_MITE: 0.02
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.64
  • UOPS_PORT_1: 1.67
  • UOPS_PORT_2: 0.74
  • UOPS_PORT_3: 0.86
  • UOPS_PORT_4: 4.95
  • UOPS_PORT_5: 1.69
  • UOPS_PORT_6: 1.72
  • UOPS_PORT_7: 0.4
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=100

• Code:

     0:	66 41 83 06 00       	add    WORD PTR [r14],0x0
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.02
  • Core cycles: 5.5
  • Reference cycles: 4.89
  • UOPS_EXECUTED.THREAD: 4.01
  • RETIRE_SLOTS: 2.01
  • UOPS_MITE: 0.02
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.58
  • UOPS_PORT_1: 1.49
  • UOPS_PORT_2: 0.74
  • UOPS_PORT_3: 0.96
  • UOPS_PORT_4: 4.99
  • UOPS_PORT_5: 1.76
  • UOPS_PORT_6: 1.82
  • UOPS_PORT_7: 0.3
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With unroll_count=200 and no inner loop

• Code:

     0:	66 41 83 06 00       	add    WORD PTR [r14],0x0
     5:	66 41 83 46 02 00    	add    WORD PTR [r14+0x2],0x0
     b:	66 41 83 46 04 00    	add    WORD PTR [r14+0x4],0x0
    11:	66 41 83 46 06 00    	add    WORD PTR [r14+0x6],0x0
  

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 5.83
  • Reference cycles: 5.1
  • UOPS_EXECUTED.THREAD: 16.0
  • RETIRE_SLOTS: 8.0
  • UOPS_MITE: 8.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.47
  • UOPS_PORT_1: 2.52
  • UOPS_PORT_2: 3.01
  • UOPS_PORT_3: 3.1
  • UOPS_PORT_4: 5.51
  • UOPS_PORT_5: 2.6
  • UOPS_PORT_6: 2.55
  • UOPS_PORT_7: 1.9
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

• Code:

     0:	66 41 83 06 00       	add    WORD PTR [r14],0x0
     5:	66 41 83 46 02 00    	add    WORD PTR [r14+0x2],0x0
     b:	66 41 83 46 04 00    	add    WORD PTR [r14+0x4],0x0
    11:	66 41 83 46 06 00    	add    WORD PTR [r14+0x6],0x0
  

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 5.72
  • Reference cycles: 5.05
  • UOPS_EXECUTED.THREAD: 16.51
  • RETIRE_SLOTS: 8.5
  • UOPS_MITE: 0.01
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.51
  • UOPS_PORT_1: 2.57
  • UOPS_PORT_2: 2.95
  • UOPS_PORT_3: 3.03
  • UOPS_PORT_4: 5.47
  • UOPS_PORT_5: 2.61
  • UOPS_PORT_6: 2.93
  • UOPS_PORT_7: 2.04
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

• Code:

     0:	66 41 83 06 00       	add    WORD PTR [r14],0x0
     5:	66 41 83 46 02 00    	add    WORD PTR [r14+0x2],0x0
     b:	66 41 83 46 04 00    	add    WORD PTR [r14+0x4],0x0
    11:	66 41 83 46 06 00    	add    WORD PTR [r14+0x6],0x0
  

• Show nanoBench command
• Results:
  • Instructions retired: 4.1
  • Core cycles: 5.73
  • Reference cycles: 5.1
  • UOPS_EXECUTED.THREAD: 16.05
  • RETIRE_SLOTS: 8.05
  • UOPS_MITE: 0.08
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.5
  • UOPS_PORT_1: 2.55
  • UOPS_PORT_2: 2.93
  • UOPS_PORT_3: 3.02
  • UOPS_PORT_4: 5.49
  • UOPS_PORT_5: 2.57
  • UOPS_PORT_6: 2.54
  • UOPS_PORT_7: 2.05
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.04

With unroll_count=100 and no inner loop

• Code:

     0:	66 41 83 06 00       	add    WORD PTR [r14],0x0
     5:	66 41 83 46 02 00    	add    WORD PTR [r14+0x2],0x0
     b:	66 41 83 46 04 00    	add    WORD PTR [r14+0x4],0x0
    11:	66 41 83 46 06 00    	add    WORD PTR [r14+0x6],0x0
    17:	66 41 83 46 08 00    	add    WORD PTR [r14+0x8],0x0
    1d:	66 41 83 46 0a 00    	add    WORD PTR [r14+0xa],0x0
    23:	66 41 83 46 0c 00    	add    WORD PTR [r14+0xc],0x0
    29:	66 41 83 46 0e 00    	add    WORD PTR [r14+0xe],0x0
  

• Show nanoBench command
• Results:
  • Instructions retired: 8.0
  • Core cycles: 8.01
  • Reference cycles: 6.87
  • UOPS_EXECUTED.THREAD: 32.0
  • RETIRE_SLOTS: 16.0
  • UOPS_MITE: 16.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 3.7
  • UOPS_PORT_1: 4.02
  • UOPS_PORT_2: 6.33
  • UOPS_PORT_3: 5.79
  • UOPS_PORT_4: 7.99
  • UOPS_PORT_5: 3.99
  • UOPS_PORT_6: 4.11
  • UOPS_PORT_7: 4.25
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	66 41 83 06 00       	add    WORD PTR [r14],0x0
     5:	66 41 83 46 02 00    	add    WORD PTR [r14+0x2],0x0
     b:	66 41 83 46 04 00    	add    WORD PTR [r14+0x4],0x0
    11:	66 41 83 46 06 00    	add    WORD PTR [r14+0x6],0x0
    17:	66 41 83 46 08 00    	add    WORD PTR [r14+0x8],0x0
    1d:	66 41 83 46 0a 00    	add    WORD PTR [r14+0xa],0x0
    23:	66 41 83 46 0c 00    	add    WORD PTR [r14+0xc],0x0
    29:	66 41 83 46 0e 00    	add    WORD PTR [r14+0xe],0x0
  

• Show nanoBench command
• Results:
  • Instructions retired: 10.0
  • Core cycles: 8.02
  • Reference cycles: 7.12
  • UOPS_EXECUTED.THREAD: 33.01
  • RETIRE_SLOTS: 17.0
  • UOPS_MITE: 0.02
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 3.94
  • UOPS_PORT_1: 4.01
  • UOPS_PORT_2: 5.79
  • UOPS_PORT_3: 5.96
  • UOPS_PORT_4: 8.0
  • UOPS_PORT_5: 4.1
  • UOPS_PORT_6: 4.62
  • UOPS_PORT_7: 4.26
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

• Code:

     0:	66 41 83 06 00       	add    WORD PTR [r14],0x0
     5:	66 41 83 46 02 00    	add    WORD PTR [r14+0x2],0x0
     b:	66 41 83 46 04 00    	add    WORD PTR [r14+0x4],0x0
    11:	66 41 83 46 06 00    	add    WORD PTR [r14+0x6],0x0
    17:	66 41 83 46 08 00    	add    WORD PTR [r14+0x8],0x0
    1d:	66 41 83 46 0a 00    	add    WORD PTR [r14+0xa],0x0
    23:	66 41 83 46 0c 00    	add    WORD PTR [r14+0xc],0x0
    29:	66 41 83 46 0e 00    	add    WORD PTR [r14+0xe],0x0
  

• Show nanoBench command
• Results:
  • Instructions retired: 8.2
  • Core cycles: 8.02
  • Reference cycles: 7.09
  • UOPS_EXECUTED.THREAD: 32.11
  • RETIRE_SLOTS: 16.1
  • UOPS_MITE: 0.16
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 3.94
  • UOPS_PORT_1: 4.0
  • UOPS_PORT_2: 5.83
  • UOPS_PORT_3: 6.01
  • UOPS_PORT_4: 8.0
  • UOPS_PORT_5: 4.02
  • UOPS_PORT_6: 3.83
  • UOPS_PORT_7: 4.19
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.08

With unroll_count=100 and no inner loop

• Code:

     0:	66 41 83 06 00       	add    WORD PTR [r14],0x0
     5:	66 41 83 46 02 00    	add    WORD PTR [r14+0x2],0x0
     b:	66 41 83 46 04 00    	add    WORD PTR [r14+0x4],0x0
    11:	66 41 83 46 06 00    	add    WORD PTR [r14+0x6],0x0
    17:	66 41 83 46 08 00    	add    WORD PTR [r14+0x8],0x0
    1d:	66 41 83 46 0a 00    	add    WORD PTR [r14+0xa],0x0
    23:	66 41 83 46 0c 00    	add    WORD PTR [r14+0xc],0x0
    29:	66 41 83 46 0e 00    	add    WORD PTR [r14+0xe],0x0
    2f:	66 41 83 46 10 00    	add    WORD PTR [r14+0x10],0x0
    35:	66 41 83 46 12 00    	add    WORD PTR [r14+0x12],0x0
    3b:	66 41 83 46 14 00    	add    WORD PTR [r14+0x14],0x0
    41:	66 41 83 46 16 00    	add    WORD PTR [r14+0x16],0x0
    47:	66 41 83 46 18 00    	add    WORD PTR [r14+0x18],0x0
    4d:	66 41 83 46 1a 00    	add    WORD PTR [r14+0x1a],0x0
    53:	66 41 83 46 1c 00    	add    WORD PTR [r14+0x1c],0x0
    59:	66 41 83 46 1e 00    	add    WORD PTR [r14+0x1e],0x0
  

• Show nanoBench command
• Results:
  • Instructions retired: 16.0
  • Core cycles: 16.13
  • Reference cycles: 14.19
  • UOPS_EXECUTED.THREAD: 64.0
  • RETIRE_SLOTS: 32.0
  • UOPS_MITE: 32.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 4.01
  • UOPS_PORT_1: 4.0
  • UOPS_PORT_2: 12.31
  • UOPS_PORT_3: 10.67
  • UOPS_PORT_4: 16.0
  • UOPS_PORT_5: 4.02
  • UOPS_PORT_6: 4.1
  • UOPS_PORT_7: 9.03
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 16.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	66 41 83 06 00       	add    WORD PTR [r14],0x0
     5:	66 41 83 46 02 00    	add    WORD PTR [r14+0x2],0x0
     b:	66 41 83 46 04 00    	add    WORD PTR [r14+0x4],0x0
    11:	66 41 83 46 06 00    	add    WORD PTR [r14+0x6],0x0
    17:	66 41 83 46 08 00    	add    WORD PTR [r14+0x8],0x0
    1d:	66 41 83 46 0a 00    	add    WORD PTR [r14+0xa],0x0
    23:	66 41 83 46 0c 00    	add    WORD PTR [r14+0xc],0x0
    29:	66 41 83 46 0e 00    	add    WORD PTR [r14+0xe],0x0
    2f:	66 41 83 46 10 00    	add    WORD PTR [r14+0x10],0x0
    35:	66 41 83 46 12 00    	add    WORD PTR [r14+0x12],0x0
    3b:	66 41 83 46 14 00    	add    WORD PTR [r14+0x14],0x0
    41:	66 41 83 46 16 00    	add    WORD PTR [r14+0x16],0x0
    47:	66 41 83 46 18 00    	add    WORD PTR [r14+0x18],0x0
    4d:	66 41 83 46 1a 00    	add    WORD PTR [r14+0x1a],0x0
    53:	66 41 83 46 1c 00    	add    WORD PTR [r14+0x1c],0x0
    59:	66 41 83 46 1e 00    	add    WORD PTR [r14+0x1e],0x0
  

• Show nanoBench command
• Results:
  • Instructions retired: 18.0
  • Core cycles: 16.01
  • Reference cycles: 14.21
  • UOPS_EXECUTED.THREAD: 65.01
  • RETIRE_SLOTS: 33.0
  • UOPS_MITE: 11.03
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 7.77
  • UOPS_PORT_1: 7.9
  • UOPS_PORT_2: 11.53
  • UOPS_PORT_3: 11.87
  • UOPS_PORT_4: 16.0
  • UOPS_PORT_5: 8.08
  • UOPS_PORT_6: 8.51
  • UOPS_PORT_7: 8.63
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 5.02

With loop_count=100 and unroll_count=10

• Code:

     0:	66 41 83 06 00       	add    WORD PTR [r14],0x0
     5:	66 41 83 46 02 00    	add    WORD PTR [r14+0x2],0x0
     b:	66 41 83 46 04 00    	add    WORD PTR [r14+0x4],0x0
    11:	66 41 83 46 06 00    	add    WORD PTR [r14+0x6],0x0
    17:	66 41 83 46 08 00    	add    WORD PTR [r14+0x8],0x0
    1d:	66 41 83 46 0a 00    	add    WORD PTR [r14+0xa],0x0
    23:	66 41 83 46 0c 00    	add    WORD PTR [r14+0xc],0x0
    29:	66 41 83 46 0e 00    	add    WORD PTR [r14+0xe],0x0
    2f:	66 41 83 46 10 00    	add    WORD PTR [r14+0x10],0x0
    35:	66 41 83 46 12 00    	add    WORD PTR [r14+0x12],0x0
    3b:	66 41 83 46 14 00    	add    WORD PTR [r14+0x14],0x0
    41:	66 41 83 46 16 00    	add    WORD PTR [r14+0x16],0x0
    47:	66 41 83 46 18 00    	add    WORD PTR [r14+0x18],0x0
    4d:	66 41 83 46 1a 00    	add    WORD PTR [r14+0x1a],0x0
    53:	66 41 83 46 1c 00    	add    WORD PTR [r14+0x1c],0x0
    59:	66 41 83 46 1e 00    	add    WORD PTR [r14+0x1e],0x0
  

• Show nanoBench command
• Results:
  • Instructions retired: 16.2
  • Core cycles: 16.01
  • Reference cycles: 14.23
  • UOPS_EXECUTED.THREAD: 64.11
  • RETIRE_SLOTS: 32.1
  • UOPS_MITE: 0.32
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 7.54
  • UOPS_PORT_1: 7.81
  • UOPS_PORT_2: 11.7
  • UOPS_PORT_3: 12.0
  • UOPS_PORT_4: 16.0
  • UOPS_PORT_5: 8.16
  • UOPS_PORT_6: 7.72
  • UOPS_PORT_7: 8.31
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.16

With unroll_count=500 and no inner loop

• Code:

     0:	66 43 83 04 2e 00    	add    WORD PTR [r14+r13*1],0x0
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 1.0
  • Core cycles: 5.57
  • Reference cycles: 4.97
  • UOPS_EXECUTED.THREAD: 4.0
  • RETIRE_SLOTS: 3.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.6
  • UOPS_PORT_1: 1.6
  • UOPS_PORT_2: 0.91
  • UOPS_PORT_3: 1.1
  • UOPS_PORT_4: 4.89
  • UOPS_PORT_5: 1.08
  • UOPS_PORT_6: 1.6
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

• Code:

     0:	66 43 83 04 2e 00    	add    WORD PTR [r14+r13*1],0x0
     6:	90                   	nop
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 5.54
  • Reference cycles: 4.97
  • UOPS_EXECUTED.THREAD: 4.0
  • RETIRE_SLOTS: 4.0
  • UOPS_MITE: 3.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.5
  • UOPS_PORT_1: 1.55
  • UOPS_PORT_2: 1.19
  • UOPS_PORT_3: 0.81
  • UOPS_PORT_4: 4.96
  • UOPS_PORT_5: 1.49
  • UOPS_PORT_6: 1.51
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

• Code:

     0:	66 43 83 04 2e 00    	add    WORD PTR [r14+r13*1],0x0
     6:	90                   	nop
     7:	90                   	nop
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 3.0
  • Core cycles: 5.57
  • Reference cycles: 4.83
  • UOPS_EXECUTED.THREAD: 4.0
  • RETIRE_SLOTS: 5.0
  • UOPS_MITE: 4.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.49
  • UOPS_PORT_1: 1.48
  • UOPS_PORT_2: 0.95
  • UOPS_PORT_3: 1.05
  • UOPS_PORT_4: 4.96
  • UOPS_PORT_5: 1.5
  • UOPS_PORT_6: 1.62
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

• Code:

     0:	66 43 83 04 2e 00    	add    WORD PTR [r14+r13*1],0x0
     6:	90                   	nop
     7:	90                   	nop
     8:	90                   	nop
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 5.48
  • Reference cycles: 4.88
  • UOPS_EXECUTED.THREAD: 4.0
  • RETIRE_SLOTS: 6.0
  • UOPS_MITE: 5.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.62
  • UOPS_PORT_1: 1.66
  • UOPS_PORT_2: 0.94
  • UOPS_PORT_3: 1.06
  • UOPS_PORT_4: 4.82
  • UOPS_PORT_5: 1.27
  • UOPS_PORT_6: 1.67
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 4 NOPs

• Code:

     0:	66 43 83 04 2e 00    	add    WORD PTR [r14+r13*1],0x0
     6:	90                   	nop
     7:	90                   	nop
     8:	90                   	nop
     9:	90                   	nop
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 5.62
  • Reference cycles: 4.97
  • UOPS_EXECUTED.THREAD: 4.0
  • RETIRE_SLOTS: 7.0
  • UOPS_MITE: 6.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.63
  • UOPS_PORT_1: 1.62
  • UOPS_PORT_2: 0.92
  • UOPS_PORT_3: 1.08
  • UOPS_PORT_4: 4.98
  • UOPS_PORT_5: 1.21
  • UOPS_PORT_6: 1.8
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

• Code:

     0:	66 43 83 04 2e 00    	add    WORD PTR [r14+r13*1],0x0
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 1.2
  • Core cycles: 5.58
  • Reference cycles: 4.96
  • UOPS_EXECUTED.THREAD: 4.1
  • RETIRE_SLOTS: 3.1
  • UOPS_MITE: 2.11
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.68
  • UOPS_PORT_1: 1.67
  • UOPS_PORT_2: 0.91
  • UOPS_PORT_3: 1.09
  • UOPS_PORT_4: 5.02
  • UOPS_PORT_5: 1.58
  • UOPS_PORT_6: 1.38
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=100 and unroll_count=100

• Code:

     0:	66 43 83 04 2e 00    	add    WORD PTR [r14+r13*1],0x0
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 1.02
  • Core cycles: 5.57
  • Reference cycles: 4.95
  • UOPS_EXECUTED.THREAD: 4.01
  • RETIRE_SLOTS: 3.01
  • UOPS_MITE: 0.11
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.61
  • UOPS_PORT_1: 1.62
  • UOPS_PORT_2: 0.9
  • UOPS_PORT_3: 1.1
  • UOPS_PORT_4: 4.99
  • UOPS_PORT_5: 1.55
  • UOPS_PORT_6: 1.14
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.05

With unroll_count=200 and no inner loop

• Code:

     0:	66 43 83 04 2e 00    	add    WORD PTR [r14+r13*1],0x0
     6:	66 43 83 44 2e 02 00 	add    WORD PTR [r14+r13*1+0x2],0x0
     d:	66 43 83 44 2e 04 00 	add    WORD PTR [r14+r13*1+0x4],0x0
    14:	66 43 83 44 2e 06 00 	add    WORD PTR [r14+r13*1+0x6],0x0
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 4.11
  • Reference cycles: 3.33
  • UOPS_EXECUTED.THREAD: 16.0
  • RETIRE_SLOTS: 12.0
  • UOPS_MITE: 8.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.04
  • UOPS_PORT_1: 2.37
  • UOPS_PORT_2: 4.0
  • UOPS_PORT_3: 4.0
  • UOPS_PORT_4: 4.04
  • UOPS_PORT_5: 1.17
  • UOPS_PORT_6: 2.19
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

• Code:

     0:	66 43 83 04 2e 00    	add    WORD PTR [r14+r13*1],0x0
     6:	66 43 83 44 2e 02 00 	add    WORD PTR [r14+r13*1+0x2],0x0
     d:	66 43 83 44 2e 04 00 	add    WORD PTR [r14+r13*1+0x4],0x0
    14:	66 43 83 44 2e 06 00 	add    WORD PTR [r14+r13*1+0x6],0x0
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 4.01
  • Reference cycles: 3.57
  • UOPS_EXECUTED.THREAD: 16.5
  • RETIRE_SLOTS: 12.5
  • UOPS_MITE: 0.01
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.2
  • UOPS_PORT_1: 2.4
  • UOPS_PORT_2: 4.0
  • UOPS_PORT_3: 4.0
  • UOPS_PORT_4: 4.0
  • UOPS_PORT_5: 1.3
  • UOPS_PORT_6: 2.63
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

• Code:

     0:	66 43 83 04 2e 00    	add    WORD PTR [r14+r13*1],0x0
     6:	66 43 83 44 2e 02 00 	add    WORD PTR [r14+r13*1+0x2],0x0
     d:	66 43 83 44 2e 04 00 	add    WORD PTR [r14+r13*1+0x4],0x0
    14:	66 43 83 44 2e 06 00 	add    WORD PTR [r14+r13*1+0x6],0x0
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 4.1
  • Core cycles: 4.01
  • Reference cycles: 3.56
  • UOPS_EXECUTED.THREAD: 16.06
  • RETIRE_SLOTS: 12.05
  • UOPS_MITE: 0.53
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.09
  • UOPS_PORT_1: 2.36
  • UOPS_PORT_2: 4.0
  • UOPS_PORT_3: 4.0
  • UOPS_PORT_4: 4.0
  • UOPS_PORT_5: 1.2
  • UOPS_PORT_6: 2.27
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.24

With unroll_count=100 and no inner loop

• Code:

     0:	66 43 83 04 2e 00    	add    WORD PTR [r14+r13*1],0x0
     6:	66 43 83 44 2e 02 00 	add    WORD PTR [r14+r13*1+0x2],0x0
     d:	66 43 83 44 2e 04 00 	add    WORD PTR [r14+r13*1+0x4],0x0
    14:	66 43 83 44 2e 06 00 	add    WORD PTR [r14+r13*1+0x6],0x0
    1b:	66 43 83 44 2e 08 00 	add    WORD PTR [r14+r13*1+0x8],0x0
    22:	66 43 83 44 2e 0a 00 	add    WORD PTR [r14+r13*1+0xa],0x0
    29:	66 43 83 44 2e 0c 00 	add    WORD PTR [r14+r13*1+0xc],0x0
    30:	66 43 83 44 2e 0e 00 	add    WORD PTR [r14+r13*1+0xe],0x0
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 8.0
  • Core cycles: 8.0
  • Reference cycles: 7.98
  • UOPS_EXECUTED.THREAD: 32.0
  • RETIRE_SLOTS: 24.0
  • UOPS_MITE: 16.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.29
  • UOPS_PORT_1: 2.41
  • UOPS_PORT_2: 8.0
  • UOPS_PORT_3: 8.0
  • UOPS_PORT_4: 8.0
  • UOPS_PORT_5: 0.67
  • UOPS_PORT_6: 2.63
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	66 43 83 04 2e 00    	add    WORD PTR [r14+r13*1],0x0
     6:	66 43 83 44 2e 02 00 	add    WORD PTR [r14+r13*1+0x2],0x0
     d:	66 43 83 44 2e 04 00 	add    WORD PTR [r14+r13*1+0x4],0x0
    14:	66 43 83 44 2e 06 00 	add    WORD PTR [r14+r13*1+0x6],0x0
    1b:	66 43 83 44 2e 08 00 	add    WORD PTR [r14+r13*1+0x8],0x0
    22:	66 43 83 44 2e 0a 00 	add    WORD PTR [r14+r13*1+0xa],0x0
    29:	66 43 83 44 2e 0c 00 	add    WORD PTR [r14+r13*1+0xc],0x0
    30:	66 43 83 44 2e 0e 00 	add    WORD PTR [r14+r13*1+0xe],0x0
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 10.0
  • Core cycles: 8.03
  • Reference cycles: 7.16
  • UOPS_EXECUTED.THREAD: 33.01
  • RETIRE_SLOTS: 25.0
  • UOPS_MITE: 17.04
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.32
  • UOPS_PORT_1: 2.52
  • UOPS_PORT_2: 8.0
  • UOPS_PORT_3: 8.0
  • UOPS_PORT_4: 8.0
  • UOPS_PORT_5: 1.0
  • UOPS_PORT_6: 3.2
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 8.02

With loop_count=100 and unroll_count=10

• Code:

     0:	66 43 83 04 2e 00    	add    WORD PTR [r14+r13*1],0x0
     6:	66 43 83 44 2e 02 00 	add    WORD PTR [r14+r13*1+0x2],0x0
     d:	66 43 83 44 2e 04 00 	add    WORD PTR [r14+r13*1+0x4],0x0
    14:	66 43 83 44 2e 06 00 	add    WORD PTR [r14+r13*1+0x6],0x0
    1b:	66 43 83 44 2e 08 00 	add    WORD PTR [r14+r13*1+0x8],0x0
    22:	66 43 83 44 2e 0a 00 	add    WORD PTR [r14+r13*1+0xa],0x0
    29:	66 43 83 44 2e 0c 00 	add    WORD PTR [r14+r13*1+0xc],0x0
    30:	66 43 83 44 2e 0e 00 	add    WORD PTR [r14+r13*1+0xe],0x0
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 8.2
  • Core cycles: 8.03
  • Reference cycles: 7.12
  • UOPS_EXECUTED.THREAD: 32.11
  • RETIRE_SLOTS: 24.1
  • UOPS_MITE: 0.16
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.3
  • UOPS_PORT_1: 2.4
  • UOPS_PORT_2: 8.0
  • UOPS_PORT_3: 8.0
  • UOPS_PORT_4: 8.0
  • UOPS_PORT_5: 0.71
  • UOPS_PORT_6: 2.66
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.08

With unroll_count=100 and no inner loop

• Code:

     0:	66 43 83 04 2e 00    	add    WORD PTR [r14+r13*1],0x0
     6:	66 43 83 44 2e 02 00 	add    WORD PTR [r14+r13*1+0x2],0x0
     d:	66 43 83 44 2e 04 00 	add    WORD PTR [r14+r13*1+0x4],0x0
    14:	66 43 83 44 2e 06 00 	add    WORD PTR [r14+r13*1+0x6],0x0
    1b:	66 43 83 44 2e 08 00 	add    WORD PTR [r14+r13*1+0x8],0x0
    22:	66 43 83 44 2e 0a 00 	add    WORD PTR [r14+r13*1+0xa],0x0
    29:	66 43 83 44 2e 0c 00 	add    WORD PTR [r14+r13*1+0xc],0x0
    30:	66 43 83 44 2e 0e 00 	add    WORD PTR [r14+r13*1+0xe],0x0
    37:	66 43 83 44 2e 10 00 	add    WORD PTR [r14+r13*1+0x10],0x0
    3e:	66 43 83 44 2e 12 00 	add    WORD PTR [r14+r13*1+0x12],0x0
    45:	66 43 83 44 2e 14 00 	add    WORD PTR [r14+r13*1+0x14],0x0
    4c:	66 43 83 44 2e 16 00 	add    WORD PTR [r14+r13*1+0x16],0x0
    53:	66 43 83 44 2e 18 00 	add    WORD PTR [r14+r13*1+0x18],0x0
    5a:	66 43 83 44 2e 1a 00 	add    WORD PTR [r14+r13*1+0x1a],0x0
    61:	66 43 83 44 2e 1c 00 	add    WORD PTR [r14+r13*1+0x1c],0x0
    68:	66 43 83 44 2e 1e 00 	add    WORD PTR [r14+r13*1+0x1e],0x0
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 16.0
  • Core cycles: 16.0
  • Reference cycles: 13.97
  • UOPS_EXECUTED.THREAD: 64.0
  • RETIRE_SLOTS: 48.0
  • UOPS_MITE: 32.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 4.49
  • UOPS_PORT_1: 4.79
  • UOPS_PORT_2: 16.0
  • UOPS_PORT_3: 16.0
  • UOPS_PORT_4: 16.0
  • UOPS_PORT_5: 1.67
  • UOPS_PORT_6: 5.1
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 16.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	66 43 83 04 2e 00    	add    WORD PTR [r14+r13*1],0x0
     6:	66 43 83 44 2e 02 00 	add    WORD PTR [r14+r13*1+0x2],0x0
     d:	66 43 83 44 2e 04 00 	add    WORD PTR [r14+r13*1+0x4],0x0
    14:	66 43 83 44 2e 06 00 	add    WORD PTR [r14+r13*1+0x6],0x0
    1b:	66 43 83 44 2e 08 00 	add    WORD PTR [r14+r13*1+0x8],0x0
    22:	66 43 83 44 2e 0a 00 	add    WORD PTR [r14+r13*1+0xa],0x0
    29:	66 43 83 44 2e 0c 00 	add    WORD PTR [r14+r13*1+0xc],0x0
    30:	66 43 83 44 2e 0e 00 	add    WORD PTR [r14+r13*1+0xe],0x0
    37:	66 43 83 44 2e 10 00 	add    WORD PTR [r14+r13*1+0x10],0x0
    3e:	66 43 83 44 2e 12 00 	add    WORD PTR [r14+r13*1+0x12],0x0
    45:	66 43 83 44 2e 14 00 	add    WORD PTR [r14+r13*1+0x14],0x0
    4c:	66 43 83 44 2e 16 00 	add    WORD PTR [r14+r13*1+0x16],0x0
    53:	66 43 83 44 2e 18 00 	add    WORD PTR [r14+r13*1+0x18],0x0
    5a:	66 43 83 44 2e 1a 00 	add    WORD PTR [r14+r13*1+0x1a],0x0
    61:	66 43 83 44 2e 1c 00 	add    WORD PTR [r14+r13*1+0x1c],0x0
    68:	66 43 83 44 2e 1e 00 	add    WORD PTR [r14+r13*1+0x1e],0x0
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 18.0
  • Core cycles: 16.02
  • Reference cycles: 14.23
  • UOPS_EXECUTED.THREAD: 65.01
  • RETIRE_SLOTS: 49.0
  • UOPS_MITE: 0.03
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 4.7
  • UOPS_PORT_1: 4.8
  • UOPS_PORT_2: 16.0
  • UOPS_PORT_3: 16.0
  • UOPS_PORT_4: 16.0
  • UOPS_PORT_5: 2.0
  • UOPS_PORT_6: 5.57
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.02

With loop_count=100 and unroll_count=10

• Code:

     0:	66 43 83 04 2e 00    	add    WORD PTR [r14+r13*1],0x0
     6:	66 43 83 44 2e 02 00 	add    WORD PTR [r14+r13*1+0x2],0x0
     d:	66 43 83 44 2e 04 00 	add    WORD PTR [r14+r13*1+0x4],0x0
    14:	66 43 83 44 2e 06 00 	add    WORD PTR [r14+r13*1+0x6],0x0
    1b:	66 43 83 44 2e 08 00 	add    WORD PTR [r14+r13*1+0x8],0x0
    22:	66 43 83 44 2e 0a 00 	add    WORD PTR [r14+r13*1+0xa],0x0
    29:	66 43 83 44 2e 0c 00 	add    WORD PTR [r14+r13*1+0xc],0x0
    30:	66 43 83 44 2e 0e 00 	add    WORD PTR [r14+r13*1+0xe],0x0
    37:	66 43 83 44 2e 10 00 	add    WORD PTR [r14+r13*1+0x10],0x0
    3e:	66 43 83 44 2e 12 00 	add    WORD PTR [r14+r13*1+0x12],0x0
    45:	66 43 83 44 2e 14 00 	add    WORD PTR [r14+r13*1+0x14],0x0
    4c:	66 43 83 44 2e 16 00 	add    WORD PTR [r14+r13*1+0x16],0x0
    53:	66 43 83 44 2e 18 00 	add    WORD PTR [r14+r13*1+0x18],0x0
    5a:	66 43 83 44 2e 1a 00 	add    WORD PTR [r14+r13*1+0x1a],0x0
    61:	66 43 83 44 2e 1c 00 	add    WORD PTR [r14+r13*1+0x1c],0x0
    68:	66 43 83 44 2e 1e 00 	add    WORD PTR [r14+r13*1+0x1e],0x0
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 16.2
  • Core cycles: 16.03
  • Reference cycles: 14.23
  • UOPS_EXECUTED.THREAD: 64.11
  • RETIRE_SLOTS: 48.1
  • UOPS_MITE: 0.32
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 4.4
  • UOPS_PORT_1: 4.8
  • UOPS_PORT_2: 16.0
  • UOPS_PORT_3: 16.0
  • UOPS_PORT_4: 16.0
  • UOPS_PORT_5: 2.35
  • UOPS_PORT_6: 4.53
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.16