ADD_LOCK (M32, I8) - Throughput and Uops (IACA 2.3)


With a non-indexed addressing mode

With 1 independent instruction

Throughput Analysis Report
--------------------------
Block Throughput: 1.48 Cycles       Throughput Bottleneck: FrontEnd

Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |  6   |  7   |
---------------------------------------------------------------------------------------
| Cycles | 1.2    0.0  | 1.2  | 0.6    0.5  | 0.7    0.5  | 1.0  | 1.2  | 1.3  | 0.6  |
---------------------------------------------------------------------------------------


| Num Of |                    Ports pressure in cycles                     |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |  6  |  7  |    |
---------------------------------------------------------------------------------
|   8^   | 1.2       | 1.2 | 0.6   0.5 | 0.7   0.5 | 1.0 | 1.2 | 1.3 | 0.6 |    | lock add dword ptr [r14], 0x2
Total Num Of Uops: 8

With 16 independent instructions


Throughput Analysis Report
--------------------------
Block Throughput: 24.00 Cycles       Throughput Bottleneck: FrontEnd

Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |  6   |  7   |
---------------------------------------------------------------------------------------
| Cycles | 19.9   0.0  | 19.9 | 10.7   8.0  | 10.6   8.0  | 16.0 | 19.9 | 20.4 | 10.6 |
---------------------------------------------------------------------------------------


| Num Of |                    Ports pressure in cycles                     |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |  6  |  7  |    |
---------------------------------------------------------------------------------
|   8^   | 1.2       | 1.3 | 1.0   1.0 | 0.3       | 1.0 | 1.2 | 1.2 | 0.6 |    | lock add dword ptr [r14], 0x2
|   8^   | 1.3       | 1.2 | 0.3       | 1.0   1.0 | 1.0 | 1.2 | 1.2 | 0.6 |    | lock add dword ptr [r14+0x4], 0x2
|   8^   | 1.2       | 1.2 | 1.0   1.0 | 0.3       | 1.0 | 1.2 | 1.4 | 0.7 |    | lock add dword ptr [r14+0x8], 0x2
|   8^   | 1.2       | 1.2 | 0.3       | 1.0   1.0 | 1.0 | 1.3 | 1.2 | 0.6 |    | lock add dword ptr [r14+0xc], 0x2
|   8^   | 1.2       | 1.2 | 1.0   1.0 | 0.3       | 1.0 | 1.2 | 1.3 | 0.6 |    | lock add dword ptr [r14+0x10], 0x2
|   8^   | 1.2       | 1.2 | 0.3       | 1.0   1.0 | 1.0 | 1.2 | 1.3 | 0.7 |    | lock add dword ptr [r14+0x14], 0x2
|   8^   | 1.2       | 1.2 | 1.0   1.0 | 0.3       | 1.0 | 1.2 | 1.2 | 0.6 |    | lock add dword ptr [r14+0x18], 0x2
|   8^   | 1.3       | 1.2 | 0.3       | 1.0   1.0 | 1.0 | 1.2 | 1.2 | 0.6 |    | lock add dword ptr [r14+0x1c], 0x2
|   8^   | 1.2       | 1.2 | 1.0   1.0 | 0.3       | 1.0 | 1.2 | 1.3 | 0.7 |    | lock add dword ptr [r14+0x20], 0x2
|   8^   | 1.2       | 1.2 | 0.3       | 1.0   1.0 | 1.0 | 1.3 | 1.2 | 0.6 |    | lock add dword ptr [r14+0x24], 0x2
|   8^   | 1.2       | 1.3 | 1.0   1.0 | 0.3       | 1.0 | 1.2 | 1.3 | 0.6 |    | lock add dword ptr [r14+0x28], 0x2
|   8^   | 1.2       | 1.2 | 0.3       | 1.0   1.0 | 1.0 | 1.2 | 1.3 | 0.7 |    | lock add dword ptr [r14+0x2c], 0x2
|   8^   | 1.2       | 1.2 | 1.0   1.0 | 0.3       | 1.0 | 1.2 | 1.3 | 0.6 |    | lock add dword ptr [r14+0x30], 0x2
|   8^   | 1.2       | 1.2 | 0.3       | 1.0   1.0 | 1.0 | 1.2 | 1.2 | 0.6 |    | lock add dword ptr [r14+0x34], 0x2
|   8^   | 1.2       | 1.2 | 1.0   1.0 | 0.3       | 1.0 | 1.2 | 1.3 | 0.7 |    | lock add dword ptr [r14+0x38], 0x2
|   8^   | 1.2       | 1.2 | 0.3       | 1.0   1.0 | 1.0 | 1.3 | 1.2 | 0.6 |    | lock add dword ptr [r14+0x3c], 0x2
Total Num Of Uops: 128

With an indexed addressing mode

With 1 independent instruction

Throughput Analysis Report
--------------------------
Block Throughput: 2.00 Cycles       Throughput Bottleneck: FrontEnd

Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |  6   |  7   |
---------------------------------------------------------------------------------------
| Cycles | 1.2    0.0  | 1.2  | 1.0    0.5  | 1.0    0.5  | 1.0  | 1.2  | 1.2  | 0.0  |
---------------------------------------------------------------------------------------


| Num Of |                    Ports pressure in cycles                     |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |  6  |  7  |    |
---------------------------------------------------------------------------------
|   8    | 1.2       | 1.2 | 1.0   0.5 | 1.0   0.5 | 1.0 | 1.2 | 1.2 |     |    | lock add dword ptr [r14+r13*1], 0x2
Total Num Of Uops: 8

With 16 independent instructions


Throughput Analysis Report
--------------------------
Block Throughput: 32.00 Cycles       Throughput Bottleneck: FrontEnd

Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |  6   |  7   |
---------------------------------------------------------------------------------------
| Cycles | 20.0   0.0  | 20.0 | 16.0   8.0  | 16.0   8.0  | 16.0 | 20.0 | 20.0 | 0.0  |
---------------------------------------------------------------------------------------


| Num Of |                    Ports pressure in cycles                     |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |  6  |  7  |    |
---------------------------------------------------------------------------------
|   8    | 2.0       | 1.0 | 1.0   1.0 | 1.0       | 1.0 | 1.0 | 1.0 |     |    | lock add dword ptr [r14+r13*1], 0x2
|   8    | 1.0       | 1.0 | 1.0       | 1.0   1.0 | 1.0 | 1.0 | 2.0 |     |    | lock add dword ptr [r14+r13*1+0x4], 0x2
|   8    | 1.0       | 2.0 | 1.0   1.0 | 1.0       | 1.0 | 1.0 | 1.0 |     |    | lock add dword ptr [r14+r13*1+0x8], 0x2
|   8    | 1.0       | 1.0 | 1.0       | 1.0   1.0 | 1.0 | 2.0 | 1.0 |     |    | lock add dword ptr [r14+r13*1+0xc], 0x2
|   8    | 2.0       | 1.0 | 1.0   1.0 | 1.0       | 1.0 | 1.0 | 1.0 |     |    | lock add dword ptr [r14+r13*1+0x10], 0x2
|   8    | 1.0       | 1.0 | 1.0       | 1.0   1.0 | 1.0 | 1.0 | 2.0 |     |    | lock add dword ptr [r14+r13*1+0x14], 0x2
|   8    | 1.0       | 2.0 | 1.0   1.0 | 1.0       | 1.0 | 1.0 | 1.0 |     |    | lock add dword ptr [r14+r13*1+0x18], 0x2
|   8    | 1.0       | 1.0 | 1.0       | 1.0   1.0 | 1.0 | 2.0 | 1.0 |     |    | lock add dword ptr [r14+r13*1+0x1c], 0x2
|   8    | 2.0       | 1.0 | 1.0   1.0 | 1.0       | 1.0 | 1.0 | 1.0 |     |    | lock add dword ptr [r14+r13*1+0x20], 0x2
|   8    | 1.0       | 1.0 | 1.0       | 1.0   1.0 | 1.0 | 1.0 | 2.0 |     |    | lock add dword ptr [r14+r13*1+0x24], 0x2
|   8    | 1.0       | 2.0 | 1.0   1.0 | 1.0       | 1.0 | 1.0 | 1.0 |     |    | lock add dword ptr [r14+r13*1+0x28], 0x2
|   8    | 1.0       | 1.0 | 1.0       | 1.0   1.0 | 1.0 | 2.0 | 1.0 |     |    | lock add dword ptr [r14+r13*1+0x2c], 0x2
|   8    | 2.0       | 1.0 | 1.0   1.0 | 1.0       | 1.0 | 1.0 | 1.0 |     |    | lock add dword ptr [r14+r13*1+0x30], 0x2
|   8    | 1.0       | 1.0 | 1.0       | 1.0   1.0 | 1.0 | 1.0 | 2.0 |     |    | lock add dword ptr [r14+r13*1+0x34], 0x2
|   8    | 1.0       | 2.0 | 1.0   1.0 | 1.0       | 1.0 | 1.0 | 1.0 |     |    | lock add dword ptr [r14+r13*1+0x38], 0x2
|   8    | 1.0       | 1.0 | 1.0       | 1.0   1.0 | 1.0 | 2.0 | 1.0 |     |    | lock add dword ptr [r14+r13*1+0x3c], 0x2
Total Num Of Uops: 128