VPCOMPRESSD_Z (ZMM, K, ZMM)

With unroll_count=500 and no inner loop

Code:

   0:	62 f2 7d c9 8b c8    	vpcompressd zmm0{k1}{z},zmm1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 2.0
- Reference cycles: 1.14
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	62 f2 7d c9 8b c8    	vpcompressd zmm0{k1}{z},zmm1
   6:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 2.0
- Reference cycles: 0.94
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 2.99
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	62 f2 7d c9 8b c8    	vpcompressd zmm0{k1}{z},zmm1
   6:	90                   	nop
   7:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 2.0
- Reference cycles: 0.97
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	62 f2 7d c9 8b c8    	vpcompressd zmm0{k1}{z},zmm1
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 2.0
- Reference cycles: 0.97
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.01

With unroll_count=500, no inner loop, and 4 NOPs

Code:

   0:	62 f2 7d c9 8b c8    	vpcompressd zmm0{k1}{z},zmm1
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 2.0
- Reference cycles: 0.97
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 5.99
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	62 f2 7d c9 8b c8    	vpcompressd zmm0{k1}{z},zmm1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 2.0
- Reference cycles: 1.03
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 f2 7d c9 8b c8    	vpcompressd zmm0{k1}{z},zmm1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 2.0
- Reference cycles: 1.03
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 f2 7d c9 8b c8    	vpcompressd zmm0{k1}{z},zmm1
   6:	62 f2 7d c9 8b ca    	vpcompressd zmm2{k1}{z},zmm1
   c:	62 f2 7d c9 8b cb    	vpcompressd zmm3{k1}{z},zmm1
  12:	62 f2 7d c9 8b cc    	vpcompressd zmm4{k1}{z},zmm1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 8.0
- Reference cycles: 4.07
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 3.99

With loop_count=1000 and unroll_count=2

Code:

   0:	62 f2 7d c9 8b c8    	vpcompressd zmm0{k1}{z},zmm1
   6:	62 f2 7d c9 8b ca    	vpcompressd zmm2{k1}{z},zmm1
   c:	62 f2 7d c9 8b cb    	vpcompressd zmm3{k1}{z},zmm1
  12:	62 f2 7d c9 8b cc    	vpcompressd zmm4{k1}{z},zmm1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 8.01
- Reference cycles: 4.06
- UOPS_EXECUTED.THREAD: 8.5
- RETIRE_SLOTS: 8.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=20

Code:

   0:	62 f2 7d c9 8b c8    	vpcompressd zmm0{k1}{z},zmm1
   6:	62 f2 7d c9 8b ca    	vpcompressd zmm2{k1}{z},zmm1
   c:	62 f2 7d c9 8b cb    	vpcompressd zmm3{k1}{z},zmm1
  12:	62 f2 7d c9 8b cc    	vpcompressd zmm4{k1}{z},zmm1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 8.01
- Reference cycles: 4.06
- UOPS_EXECUTED.THREAD: 8.05
- RETIRE_SLOTS: 8.05
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f2 7d c9 8b c8    	vpcompressd zmm0{k1}{z},zmm1
   6:	62 f2 7d c9 8b ca    	vpcompressd zmm2{k1}{z},zmm1
   c:	62 f2 7d c9 8b cb    	vpcompressd zmm3{k1}{z},zmm1
  12:	62 f2 7d c9 8b cc    	vpcompressd zmm4{k1}{z},zmm1
  18:	62 f2 7d c9 8b cd    	vpcompressd zmm5{k1}{z},zmm1
  1e:	62 f2 7d c9 8b ce    	vpcompressd zmm6{k1}{z},zmm1
  24:	62 f2 7d c9 8b cf    	vpcompressd zmm7{k1}{z},zmm1
  2a:	62 d2 7d c9 8b c8    	vpcompressd zmm8{k1}{z},zmm1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 16.0
- Reference cycles: 8.32
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 7.98

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f2 7d c9 8b c8    	vpcompressd zmm0{k1}{z},zmm1
   6:	62 f2 7d c9 8b ca    	vpcompressd zmm2{k1}{z},zmm1
   c:	62 f2 7d c9 8b cb    	vpcompressd zmm3{k1}{z},zmm1
  12:	62 f2 7d c9 8b cc    	vpcompressd zmm4{k1}{z},zmm1
  18:	62 f2 7d c9 8b cd    	vpcompressd zmm5{k1}{z},zmm1
  1e:	62 f2 7d c9 8b ce    	vpcompressd zmm6{k1}{z},zmm1
  24:	62 f2 7d c9 8b cf    	vpcompressd zmm7{k1}{z},zmm1
  2a:	62 d2 7d c9 8b c8    	vpcompressd zmm8{k1}{z},zmm1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 16.01
- Reference cycles: 8.11
- UOPS_EXECUTED.THREAD: 17.0
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	62 f2 7d c9 8b c8    	vpcompressd zmm0{k1}{z},zmm1
   6:	62 f2 7d c9 8b ca    	vpcompressd zmm2{k1}{z},zmm1
   c:	62 f2 7d c9 8b cb    	vpcompressd zmm3{k1}{z},zmm1
  12:	62 f2 7d c9 8b cc    	vpcompressd zmm4{k1}{z},zmm1
  18:	62 f2 7d c9 8b cd    	vpcompressd zmm5{k1}{z},zmm1
  1e:	62 f2 7d c9 8b ce    	vpcompressd zmm6{k1}{z},zmm1
  24:	62 f2 7d c9 8b cf    	vpcompressd zmm7{k1}{z},zmm1
  2a:	62 d2 7d c9 8b c8    	vpcompressd zmm8{k1}{z},zmm1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 16.01
- Reference cycles: 8.11
- UOPS_EXECUTED.THREAD: 16.1
- RETIRE_SLOTS: 16.11
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f2 7d c9 8b c8    	vpcompressd zmm0{k1}{z},zmm1
   6:	62 f2 7d c9 8b ca    	vpcompressd zmm2{k1}{z},zmm1
   c:	62 f2 7d c9 8b cb    	vpcompressd zmm3{k1}{z},zmm1
  12:	62 f2 7d c9 8b cc    	vpcompressd zmm4{k1}{z},zmm1
  18:	62 f2 7d c9 8b cd    	vpcompressd zmm5{k1}{z},zmm1
  1e:	62 f2 7d c9 8b ce    	vpcompressd zmm6{k1}{z},zmm1
  24:	62 f2 7d c9 8b cf    	vpcompressd zmm7{k1}{z},zmm1
  2a:	62 d2 7d c9 8b c8    	vpcompressd zmm8{k1}{z},zmm1
  30:	62 d2 7d c9 8b c9    	vpcompressd zmm9{k1}{z},zmm1
  36:	62 d2 7d c9 8b ca    	vpcompressd zmm10{k1}{z},zmm1
  3c:	62 d2 7d c9 8b cb    	vpcompressd zmm11{k1}{z},zmm1
  42:	62 d2 7d c9 8b cc    	vpcompressd zmm12{k1}{z},zmm1
  48:	62 b2 7d c9 8b c8    	vpcompressd zmm16{k1}{z},zmm1
  4e:	62 b2 7d c9 8b c9    	vpcompressd zmm17{k1}{z},zmm1
  54:	62 b2 7d c9 8b ca    	vpcompressd zmm18{k1}{z},zmm1
  5a:	62 b2 7d c9 8b cb    	vpcompressd zmm19{k1}{z},zmm1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 32.0
- Reference cycles: 16.12
- UOPS_EXECUTED.THREAD: 32.0
- RETIRE_SLOTS: 32.0
- UOPS_MITE: 32.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 32.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.01

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f2 7d c9 8b c8    	vpcompressd zmm0{k1}{z},zmm1
   6:	62 f2 7d c9 8b ca    	vpcompressd zmm2{k1}{z},zmm1
   c:	62 f2 7d c9 8b cb    	vpcompressd zmm3{k1}{z},zmm1
  12:	62 f2 7d c9 8b cc    	vpcompressd zmm4{k1}{z},zmm1
  18:	62 f2 7d c9 8b cd    	vpcompressd zmm5{k1}{z},zmm1
  1e:	62 f2 7d c9 8b ce    	vpcompressd zmm6{k1}{z},zmm1
  24:	62 f2 7d c9 8b cf    	vpcompressd zmm7{k1}{z},zmm1
  2a:	62 d2 7d c9 8b c8    	vpcompressd zmm8{k1}{z},zmm1
  30:	62 d2 7d c9 8b c9    	vpcompressd zmm9{k1}{z},zmm1
  36:	62 d2 7d c9 8b ca    	vpcompressd zmm10{k1}{z},zmm1
  3c:	62 d2 7d c9 8b cb    	vpcompressd zmm11{k1}{z},zmm1
  42:	62 d2 7d c9 8b cc    	vpcompressd zmm12{k1}{z},zmm1
  48:	62 b2 7d c9 8b c8    	vpcompressd zmm16{k1}{z},zmm1
  4e:	62 b2 7d c9 8b c9    	vpcompressd zmm17{k1}{z},zmm1
  54:	62 b2 7d c9 8b ca    	vpcompressd zmm18{k1}{z},zmm1
  5a:	62 b2 7d c9 8b cb    	vpcompressd zmm19{k1}{z},zmm1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 32.01
- Reference cycles: 16.28
- UOPS_EXECUTED.THREAD: 33.0
- RETIRE_SLOTS: 33.01
- UOPS_MITE: 0.04
- UOPS_MS: 0.01
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 32.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With loop_count=100 and unroll_count=10

Code:

   0:	62 f2 7d c9 8b c8    	vpcompressd zmm0{k1}{z},zmm1
   6:	62 f2 7d c9 8b ca    	vpcompressd zmm2{k1}{z},zmm1
   c:	62 f2 7d c9 8b cb    	vpcompressd zmm3{k1}{z},zmm1
  12:	62 f2 7d c9 8b cc    	vpcompressd zmm4{k1}{z},zmm1
  18:	62 f2 7d c9 8b cd    	vpcompressd zmm5{k1}{z},zmm1
  1e:	62 f2 7d c9 8b ce    	vpcompressd zmm6{k1}{z},zmm1
  24:	62 f2 7d c9 8b cf    	vpcompressd zmm7{k1}{z},zmm1
  2a:	62 d2 7d c9 8b c8    	vpcompressd zmm8{k1}{z},zmm1
  30:	62 d2 7d c9 8b c9    	vpcompressd zmm9{k1}{z},zmm1
  36:	62 d2 7d c9 8b ca    	vpcompressd zmm10{k1}{z},zmm1
  3c:	62 d2 7d c9 8b cb    	vpcompressd zmm11{k1}{z},zmm1
  42:	62 d2 7d c9 8b cc    	vpcompressd zmm12{k1}{z},zmm1
  48:	62 b2 7d c9 8b c8    	vpcompressd zmm16{k1}{z},zmm1
  4e:	62 b2 7d c9 8b c9    	vpcompressd zmm17{k1}{z},zmm1
  54:	62 b2 7d c9 8b ca    	vpcompressd zmm18{k1}{z},zmm1
  5a:	62 b2 7d c9 8b cb    	vpcompressd zmm19{k1}{z},zmm1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 32.01
- Reference cycles: 16.33
- UOPS_EXECUTED.THREAD: 32.1
- RETIRE_SLOTS: 32.1
- UOPS_MITE: 0.32
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 32.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.16

With the same register for for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	62 f2 7d c9 8b c0    	vpcompressd zmm0{k1}{z},zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 3.0
- Reference cycles: 1.59
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	62 f2 7d c9 8b c0    	vpcompressd zmm0{k1}{z},zmm0
   6:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.0
- Reference cycles: 1.59
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 2.99
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	62 f2 7d c9 8b c0    	vpcompressd zmm0{k1}{z},zmm0
   6:	90                   	nop
   7:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 3.0
- Reference cycles: 1.56
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	62 f2 7d c9 8b c0    	vpcompressd zmm0{k1}{z},zmm0
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 3.0
- Reference cycles: 1.53
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 4 NOPs

Code:

   0:	62 f2 7d c9 8b c0    	vpcompressd zmm0{k1}{z},zmm0
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 3.0
- Reference cycles: 1.53
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 5.99
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	62 f2 7d c9 8b c0    	vpcompressd zmm0{k1}{z},zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 3.0
- Reference cycles: 1.53
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 f2 7d c9 8b c0    	vpcompressd zmm0{k1}{z},zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 3.0
- Reference cycles: 1.53
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 f2 7d c9 8b c0    	vpcompressd zmm0{k1}{z},zmm0
   6:	62 f2 7d c9 8b c9    	vpcompressd zmm1{k1}{z},zmm1
   c:	62 f2 7d c9 8b d2    	vpcompressd zmm2{k1}{z},zmm2
  12:	62 f2 7d c9 8b db    	vpcompressd zmm3{k1}{z},zmm3

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 8.0
- Reference cycles: 4.16
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.01

With loop_count=1000 and unroll_count=2

Code:

   0:	62 f2 7d c9 8b c0    	vpcompressd zmm0{k1}{z},zmm0
   6:	62 f2 7d c9 8b c9    	vpcompressd zmm1{k1}{z},zmm1
   c:	62 f2 7d c9 8b d2    	vpcompressd zmm2{k1}{z},zmm2
  12:	62 f2 7d c9 8b db    	vpcompressd zmm3{k1}{z},zmm3

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 8.01
- Reference cycles: 4.06
- UOPS_EXECUTED.THREAD: 8.5
- RETIRE_SLOTS: 8.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=20

Code:

   0:	62 f2 7d c9 8b c0    	vpcompressd zmm0{k1}{z},zmm0
   6:	62 f2 7d c9 8b c9    	vpcompressd zmm1{k1}{z},zmm1
   c:	62 f2 7d c9 8b d2    	vpcompressd zmm2{k1}{z},zmm2
  12:	62 f2 7d c9 8b db    	vpcompressd zmm3{k1}{z},zmm3

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 8.01
- Reference cycles: 4.06
- UOPS_EXECUTED.THREAD: 8.05
- RETIRE_SLOTS: 8.05
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f2 7d c9 8b c0    	vpcompressd zmm0{k1}{z},zmm0
   6:	62 f2 7d c9 8b c9    	vpcompressd zmm1{k1}{z},zmm1
   c:	62 f2 7d c9 8b d2    	vpcompressd zmm2{k1}{z},zmm2
  12:	62 f2 7d c9 8b db    	vpcompressd zmm3{k1}{z},zmm3
  18:	62 f2 7d c9 8b e4    	vpcompressd zmm4{k1}{z},zmm4
  1e:	62 f2 7d c9 8b ed    	vpcompressd zmm5{k1}{z},zmm5
  24:	62 f2 7d c9 8b f6    	vpcompressd zmm6{k1}{z},zmm6
  2a:	62 f2 7d c9 8b ff    	vpcompressd zmm7{k1}{z},zmm7

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 16.0
- Reference cycles: 7.97
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 15.99
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.02

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f2 7d c9 8b c0    	vpcompressd zmm0{k1}{z},zmm0
   6:	62 f2 7d c9 8b c9    	vpcompressd zmm1{k1}{z},zmm1
   c:	62 f2 7d c9 8b d2    	vpcompressd zmm2{k1}{z},zmm2
  12:	62 f2 7d c9 8b db    	vpcompressd zmm3{k1}{z},zmm3
  18:	62 f2 7d c9 8b e4    	vpcompressd zmm4{k1}{z},zmm4
  1e:	62 f2 7d c9 8b ed    	vpcompressd zmm5{k1}{z},zmm5
  24:	62 f2 7d c9 8b f6    	vpcompressd zmm6{k1}{z},zmm6
  2a:	62 f2 7d c9 8b ff    	vpcompressd zmm7{k1}{z},zmm7

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 16.01
- Reference cycles: 8.2
- UOPS_EXECUTED.THREAD: 17.0
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	62 f2 7d c9 8b c0    	vpcompressd zmm0{k1}{z},zmm0
   6:	62 f2 7d c9 8b c9    	vpcompressd zmm1{k1}{z},zmm1
   c:	62 f2 7d c9 8b d2    	vpcompressd zmm2{k1}{z},zmm2
  12:	62 f2 7d c9 8b db    	vpcompressd zmm3{k1}{z},zmm3
  18:	62 f2 7d c9 8b e4    	vpcompressd zmm4{k1}{z},zmm4
  1e:	62 f2 7d c9 8b ed    	vpcompressd zmm5{k1}{z},zmm5
  24:	62 f2 7d c9 8b f6    	vpcompressd zmm6{k1}{z},zmm6
  2a:	62 f2 7d c9 8b ff    	vpcompressd zmm7{k1}{z},zmm7

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 16.01
- Reference cycles: 8.11
- UOPS_EXECUTED.THREAD: 16.1
- RETIRE_SLOTS: 16.11
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f2 7d c9 8b c0    	vpcompressd zmm0{k1}{z},zmm0
   6:	62 f2 7d c9 8b c9    	vpcompressd zmm1{k1}{z},zmm1
   c:	62 f2 7d c9 8b d2    	vpcompressd zmm2{k1}{z},zmm2
  12:	62 f2 7d c9 8b db    	vpcompressd zmm3{k1}{z},zmm3
  18:	62 f2 7d c9 8b e4    	vpcompressd zmm4{k1}{z},zmm4
  1e:	62 f2 7d c9 8b ed    	vpcompressd zmm5{k1}{z},zmm5
  24:	62 f2 7d c9 8b f6    	vpcompressd zmm6{k1}{z},zmm6
  2a:	62 f2 7d c9 8b ff    	vpcompressd zmm7{k1}{z},zmm7
  30:	62 52 7d c9 8b c0    	vpcompressd zmm8{k1}{z},zmm8
  36:	62 52 7d c9 8b c9    	vpcompressd zmm9{k1}{z},zmm9
  3c:	62 52 7d c9 8b d2    	vpcompressd zmm10{k1}{z},zmm10
  42:	62 52 7d c9 8b db    	vpcompressd zmm11{k1}{z},zmm11
  48:	62 52 7d c9 8b e4    	vpcompressd zmm12{k1}{z},zmm12
  4e:	62 a2 7d c9 8b c0    	vpcompressd zmm16{k1}{z},zmm16
  54:	62 a2 7d c9 8b c9    	vpcompressd zmm17{k1}{z},zmm17
  5a:	62 a2 7d c9 8b d2    	vpcompressd zmm18{k1}{z},zmm18

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7;
VXORPS ZMM8, ZMM8, ZMM8;
VXORPS ZMM9, ZMM9, ZMM9;
VXORPS ZMM10, ZMM10, ZMM10;
VXORPS ZMM11, ZMM11, ZMM11;
VXORPS ZMM12, ZMM12, ZMM12;
VXORPS ZMM16, ZMM16, ZMM16;
VXORPS ZMM17, ZMM17, ZMM17;
VXORPS ZMM18, ZMM18, ZMM18

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 32.0
- Reference cycles: 16.12
- UOPS_EXECUTED.THREAD: 32.0
- RETIRE_SLOTS: 32.0
- UOPS_MITE: 32.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 32.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.01

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f2 7d c9 8b c0    	vpcompressd zmm0{k1}{z},zmm0
   6:	62 f2 7d c9 8b c9    	vpcompressd zmm1{k1}{z},zmm1
   c:	62 f2 7d c9 8b d2    	vpcompressd zmm2{k1}{z},zmm2
  12:	62 f2 7d c9 8b db    	vpcompressd zmm3{k1}{z},zmm3
  18:	62 f2 7d c9 8b e4    	vpcompressd zmm4{k1}{z},zmm4
  1e:	62 f2 7d c9 8b ed    	vpcompressd zmm5{k1}{z},zmm5
  24:	62 f2 7d c9 8b f6    	vpcompressd zmm6{k1}{z},zmm6
  2a:	62 f2 7d c9 8b ff    	vpcompressd zmm7{k1}{z},zmm7
  30:	62 52 7d c9 8b c0    	vpcompressd zmm8{k1}{z},zmm8
  36:	62 52 7d c9 8b c9    	vpcompressd zmm9{k1}{z},zmm9
  3c:	62 52 7d c9 8b d2    	vpcompressd zmm10{k1}{z},zmm10
  42:	62 52 7d c9 8b db    	vpcompressd zmm11{k1}{z},zmm11
  48:	62 52 7d c9 8b e4    	vpcompressd zmm12{k1}{z},zmm12
  4e:	62 a2 7d c9 8b c0    	vpcompressd zmm16{k1}{z},zmm16
  54:	62 a2 7d c9 8b c9    	vpcompressd zmm17{k1}{z},zmm17
  5a:	62 a2 7d c9 8b d2    	vpcompressd zmm18{k1}{z},zmm18

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7;
VXORPS ZMM8, ZMM8, ZMM8;
VXORPS ZMM9, ZMM9, ZMM9;
VXORPS ZMM10, ZMM10, ZMM10;
VXORPS ZMM11, ZMM11, ZMM11;
VXORPS ZMM12, ZMM12, ZMM12;
VXORPS ZMM16, ZMM16, ZMM16;
VXORPS ZMM17, ZMM17, ZMM17;
VXORPS ZMM18, ZMM18, ZMM18

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 32.01
- Reference cycles: 16.29
- UOPS_EXECUTED.THREAD: 33.0
- RETIRE_SLOTS: 33.01
- UOPS_MITE: 0.04
- UOPS_MS: 0.01
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 32.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With loop_count=100 and unroll_count=10

Code:

   0:	62 f2 7d c9 8b c0    	vpcompressd zmm0{k1}{z},zmm0
   6:	62 f2 7d c9 8b c9    	vpcompressd zmm1{k1}{z},zmm1
   c:	62 f2 7d c9 8b d2    	vpcompressd zmm2{k1}{z},zmm2
  12:	62 f2 7d c9 8b db    	vpcompressd zmm3{k1}{z},zmm3
  18:	62 f2 7d c9 8b e4    	vpcompressd zmm4{k1}{z},zmm4
  1e:	62 f2 7d c9 8b ed    	vpcompressd zmm5{k1}{z},zmm5
  24:	62 f2 7d c9 8b f6    	vpcompressd zmm6{k1}{z},zmm6
  2a:	62 f2 7d c9 8b ff    	vpcompressd zmm7{k1}{z},zmm7
  30:	62 52 7d c9 8b c0    	vpcompressd zmm8{k1}{z},zmm8
  36:	62 52 7d c9 8b c9    	vpcompressd zmm9{k1}{z},zmm9
  3c:	62 52 7d c9 8b d2    	vpcompressd zmm10{k1}{z},zmm10
  42:	62 52 7d c9 8b db    	vpcompressd zmm11{k1}{z},zmm11
  48:	62 52 7d c9 8b e4    	vpcompressd zmm12{k1}{z},zmm12
  4e:	62 a2 7d c9 8b c0    	vpcompressd zmm16{k1}{z},zmm16
  54:	62 a2 7d c9 8b c9    	vpcompressd zmm17{k1}{z},zmm17
  5a:	62 a2 7d c9 8b d2    	vpcompressd zmm18{k1}{z},zmm18

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7;
VXORPS ZMM8, ZMM8, ZMM8;
VXORPS ZMM9, ZMM9, ZMM9;
VXORPS ZMM10, ZMM10, ZMM10;
VXORPS ZMM11, ZMM11, ZMM11;
VXORPS ZMM12, ZMM12, ZMM12;
VXORPS ZMM16, ZMM16, ZMM16;
VXORPS ZMM17, ZMM17, ZMM17;
VXORPS ZMM18, ZMM18, ZMM18

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 32.01
- Reference cycles: 16.26
- UOPS_EXECUTED.THREAD: 32.1
- RETIRE_SLOTS: 32.1
- UOPS_MITE: 0.33
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 32.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.16

VPCOMPRESSD_Z (ZMM, K, ZMM) - Throughput and Uops

With different registers for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With unroll_count=500, no inner loop, and 4 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With the same register for for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With unroll_count=500, no inner loop, and 4 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10