SHLX (R64, R64, R64)

With unroll_count=500 and no inner loop

Code:

   0:	c4 42 a9 f7 c1       	shlx   r8,r9,r10

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 0.5
- Reference cycles: 0.21
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 0.99
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	c4 42 a9 f7 c1       	shlx   r8,r9,r10

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 0.55
- Reference cycles: 0.28
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.55
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.55
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	c4 42 a9 f7 c1       	shlx   r8,r9,r10

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 0.51
- Reference cycles: 0.25
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.51
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	c4 42 a9 f7 c1       	shlx   r8,r9,r10
   5:	c4 42 a9 f7 d9       	shlx   r11,r9,r10
   a:	c4 42 a9 f7 e1       	shlx   r12,r9,r10
   f:	c4 42 a9 f7 e9       	shlx   r13,r9,r10

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 2.0
- Reference cycles: 1.13
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 2.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	c4 42 a9 f7 c1       	shlx   r8,r9,r10
   5:	c4 42 a9 f7 d9       	shlx   r11,r9,r10
   a:	c4 42 a9 f7 e1       	shlx   r12,r9,r10
   f:	c4 42 a9 f7 e9       	shlx   r13,r9,r10

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 2.27
- Reference cycles: 1.15
- UOPS_EXECUTED.THREAD: 4.51
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.25
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 2.26
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	c4 42 a9 f7 c1       	shlx   r8,r9,r10
   5:	c4 42 a9 f7 d9       	shlx   r11,r9,r10
   a:	c4 42 a9 f7 e1       	shlx   r12,r9,r10
   f:	c4 42 a9 f7 e9       	shlx   r13,r9,r10

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 2.03
- Reference cycles: 1.01
- UOPS_EXECUTED.THREAD: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.03
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 2.03
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 42 a9 f7 c1       	shlx   r8,r9,r10
   5:	c4 42 a9 f7 d9       	shlx   r11,r9,r10
   a:	c4 42 a9 f7 e1       	shlx   r12,r9,r10
   f:	c4 42 a9 f7 e9       	shlx   r13,r9,r10
  14:	c4 42 a9 f7 f1       	shlx   r14,r9,r10
  19:	c4 c2 a9 f7 d9       	shlx   rbx,r9,r10
  1e:	c4 c2 a9 f7 c9       	shlx   rcx,r9,r10
  23:	c4 c2 a9 f7 d1       	shlx   rdx,r9,r10

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 4.0
- Reference cycles: 2.08
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 4.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 42 a9 f7 c1       	shlx   r8,r9,r10
   5:	c4 42 a9 f7 d9       	shlx   r11,r9,r10
   a:	c4 42 a9 f7 e1       	shlx   r12,r9,r10
   f:	c4 42 a9 f7 e9       	shlx   r13,r9,r10
  14:	c4 42 a9 f7 f1       	shlx   r14,r9,r10
  19:	c4 c2 a9 f7 d9       	shlx   rbx,r9,r10
  1e:	c4 c2 a9 f7 c9       	shlx   rcx,r9,r10
  23:	c4 c2 a9 f7 d1       	shlx   rdx,r9,r10

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 4.53
- Reference cycles: 2.22
- UOPS_EXECUTED.THREAD: 9.02
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 4.51
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	c4 42 a9 f7 c1       	shlx   r8,r9,r10
   5:	c4 42 a9 f7 d9       	shlx   r11,r9,r10
   a:	c4 42 a9 f7 e1       	shlx   r12,r9,r10
   f:	c4 42 a9 f7 e9       	shlx   r13,r9,r10
  14:	c4 42 a9 f7 f1       	shlx   r14,r9,r10
  19:	c4 c2 a9 f7 d9       	shlx   rbx,r9,r10
  1e:	c4 c2 a9 f7 c9       	shlx   rcx,r9,r10
  23:	c4 c2 a9 f7 d1       	shlx   rdx,r9,r10

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 4.07
- Reference cycles: 2.03
- UOPS_EXECUTED.THREAD: 8.11
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.05
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 4.05
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 11 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 42 a9 f7 c1       	shlx   r8,r9,r10
   5:	c4 42 a9 f7 d9       	shlx   r11,r9,r10
   a:	c4 42 a9 f7 e1       	shlx   r12,r9,r10
   f:	c4 42 a9 f7 e9       	shlx   r13,r9,r10
  14:	c4 42 a9 f7 f1       	shlx   r14,r9,r10
  19:	c4 c2 a9 f7 d9       	shlx   rbx,r9,r10
  1e:	c4 c2 a9 f7 c9       	shlx   rcx,r9,r10
  23:	c4 c2 a9 f7 d1       	shlx   rdx,r9,r10
  28:	c4 c2 a9 f7 f9       	shlx   rdi,r9,r10
  2d:	c4 c2 a9 f7 f1       	shlx   rsi,r9,r10
  32:	c4 c2 a9 f7 e9       	shlx   rbp,r9,r10

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 5.51
- Reference cycles: 3.12
- UOPS_EXECUTED.THREAD: 11.0
- RETIRE_SLOTS: 11.0
- UOPS_MITE: 11.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 5.51
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 5.49
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.73

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 42 a9 f7 c1       	shlx   r8,r9,r10
   5:	c4 42 a9 f7 d9       	shlx   r11,r9,r10
   a:	c4 42 a9 f7 e1       	shlx   r12,r9,r10
   f:	c4 42 a9 f7 e9       	shlx   r13,r9,r10
  14:	c4 42 a9 f7 f1       	shlx   r14,r9,r10
  19:	c4 c2 a9 f7 d9       	shlx   rbx,r9,r10
  1e:	c4 c2 a9 f7 c9       	shlx   rcx,r9,r10
  23:	c4 c2 a9 f7 d1       	shlx   rdx,r9,r10
  28:	c4 c2 a9 f7 f9       	shlx   rdi,r9,r10
  2d:	c4 c2 a9 f7 f1       	shlx   rsi,r9,r10
  32:	c4 c2 a9 f7 e9       	shlx   rbp,r9,r10

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 6.03
- Reference cycles: 3.0
- UOPS_EXECUTED.THREAD: 12.01
- RETIRE_SLOTS: 12.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 6.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 6.01
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	c4 42 a9 f7 c1       	shlx   r8,r9,r10
   5:	c4 42 a9 f7 d9       	shlx   r11,r9,r10
   a:	c4 42 a9 f7 e1       	shlx   r12,r9,r10
   f:	c4 42 a9 f7 e9       	shlx   r13,r9,r10
  14:	c4 42 a9 f7 f1       	shlx   r14,r9,r10
  19:	c4 c2 a9 f7 d9       	shlx   rbx,r9,r10
  1e:	c4 c2 a9 f7 c9       	shlx   rcx,r9,r10
  23:	c4 c2 a9 f7 d1       	shlx   rdx,r9,r10
  28:	c4 c2 a9 f7 f9       	shlx   rdi,r9,r10
  2d:	c4 c2 a9 f7 f1       	shlx   rsi,r9,r10
  32:	c4 c2 a9 f7 e9       	shlx   rbp,r9,r10

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 11.2
- Core cycles: 5.56
- Reference cycles: 2.76
- UOPS_EXECUTED.THREAD: 11.1
- RETIRE_SLOTS: 11.1
- UOPS_MITE: 0.11
- UOPS_MS: 0.0
- UOPS_PORT_0: 5.55
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 5.55
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.03

With the same register for for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	c4 42 b9 f7 c0       	shlx   r8,r8,r8

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.52
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	c4 42 b9 f7 c0       	shlx   r8,r8,r8

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 0.5
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.6
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	c4 42 b9 f7 c0       	shlx   r8,r8,r8

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 0.5
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.51
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	c4 42 b9 f7 c0       	shlx   r8,r8,r8
   5:	c4 42 b1 f7 c9       	shlx   r9,r9,r9
   a:	c4 42 a9 f7 d2       	shlx   r10,r10,r10
   f:	c4 42 a1 f7 db       	shlx   r11,r11,r11

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 2.0
- Reference cycles: 0.95
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 2.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	c4 42 b9 f7 c0       	shlx   r8,r8,r8
   5:	c4 42 b1 f7 c9       	shlx   r9,r9,r9
   a:	c4 42 a9 f7 d2       	shlx   r10,r10,r10
   f:	c4 42 a1 f7 db       	shlx   r11,r11,r11

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 2.31
- Reference cycles: 1.14
- UOPS_EXECUTED.THREAD: 4.51
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.21
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 2.29
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	c4 42 b9 f7 c0       	shlx   r8,r8,r8
   5:	c4 42 b1 f7 c9       	shlx   r9,r9,r9
   a:	c4 42 a9 f7 d2       	shlx   r10,r10,r10
   f:	c4 42 a1 f7 db       	shlx   r11,r11,r11

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 2.04
- Reference cycles: 0.99
- UOPS_EXECUTED.THREAD: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.02
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 2.03
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 42 b9 f7 c0       	shlx   r8,r8,r8
   5:	c4 42 b1 f7 c9       	shlx   r9,r9,r9
   a:	c4 42 a9 f7 d2       	shlx   r10,r10,r10
   f:	c4 42 a1 f7 db       	shlx   r11,r11,r11
  14:	c4 42 99 f7 e4       	shlx   r12,r12,r12
  19:	c4 42 91 f7 ed       	shlx   r13,r13,r13
  1e:	c4 42 89 f7 f6       	shlx   r14,r14,r14
  23:	c4 e2 e1 f7 db       	shlx   rbx,rbx,rbx

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 4.0
- Reference cycles: 1.73
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 4.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 42 b9 f7 c0       	shlx   r8,r8,r8
   5:	c4 42 b1 f7 c9       	shlx   r9,r9,r9
   a:	c4 42 a9 f7 d2       	shlx   r10,r10,r10
   f:	c4 42 a1 f7 db       	shlx   r11,r11,r11
  14:	c4 42 99 f7 e4       	shlx   r12,r12,r12
  19:	c4 42 91 f7 ed       	shlx   r13,r13,r13
  1e:	c4 42 89 f7 f6       	shlx   r14,r14,r14
  23:	c4 e2 e1 f7 db       	shlx   rbx,rbx,rbx

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 4.53
- Reference cycles: 2.25
- UOPS_EXECUTED.THREAD: 9.01
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 4.51
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	c4 42 b9 f7 c0       	shlx   r8,r8,r8
   5:	c4 42 b1 f7 c9       	shlx   r9,r9,r9
   a:	c4 42 a9 f7 d2       	shlx   r10,r10,r10
   f:	c4 42 a1 f7 db       	shlx   r11,r11,r11
  14:	c4 42 99 f7 e4       	shlx   r12,r12,r12
  19:	c4 42 91 f7 ed       	shlx   r13,r13,r13
  1e:	c4 42 89 f7 f6       	shlx   r14,r14,r14
  23:	c4 e2 e1 f7 db       	shlx   rbx,rbx,rbx

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 4.07
- Reference cycles: 1.99
- UOPS_EXECUTED.THREAD: 8.11
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.05
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 4.05
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 13 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 42 b9 f7 c0       	shlx   r8,r8,r8
   5:	c4 42 b1 f7 c9       	shlx   r9,r9,r9
   a:	c4 42 a9 f7 d2       	shlx   r10,r10,r10
   f:	c4 42 a1 f7 db       	shlx   r11,r11,r11
  14:	c4 42 99 f7 e4       	shlx   r12,r12,r12
  19:	c4 42 91 f7 ed       	shlx   r13,r13,r13
  1e:	c4 42 89 f7 f6       	shlx   r14,r14,r14
  23:	c4 e2 e1 f7 db       	shlx   rbx,rbx,rbx
  28:	c4 e2 f1 f7 c9       	shlx   rcx,rcx,rcx
  2d:	c4 e2 e9 f7 d2       	shlx   rdx,rdx,rdx
  32:	c4 e2 c1 f7 ff       	shlx   rdi,rdi,rdi
  37:	c4 e2 c9 f7 f6       	shlx   rsi,rsi,rsi
  3c:	c4 e2 d1 f7 ed       	shlx   rbp,rbp,rbp

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 6.5
- Reference cycles: 3.12
- UOPS_EXECUTED.THREAD: 13.0
- RETIRE_SLOTS: 13.0
- UOPS_MITE: 12.96
- UOPS_MS: 0.0
- UOPS_PORT_0: 6.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 6.5
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 3.25

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 42 b9 f7 c0       	shlx   r8,r8,r8
   5:	c4 42 b1 f7 c9       	shlx   r9,r9,r9
   a:	c4 42 a9 f7 d2       	shlx   r10,r10,r10
   f:	c4 42 a1 f7 db       	shlx   r11,r11,r11
  14:	c4 42 99 f7 e4       	shlx   r12,r12,r12
  19:	c4 42 91 f7 ed       	shlx   r13,r13,r13
  1e:	c4 42 89 f7 f6       	shlx   r14,r14,r14
  23:	c4 e2 e1 f7 db       	shlx   rbx,rbx,rbx
  28:	c4 e2 f1 f7 c9       	shlx   rcx,rcx,rcx
  2d:	c4 e2 e9 f7 d2       	shlx   rdx,rdx,rdx
  32:	c4 e2 c1 f7 ff       	shlx   rdi,rdi,rdi
  37:	c4 e2 c9 f7 f6       	shlx   rsi,rsi,rsi
  3c:	c4 e2 d1 f7 ed       	shlx   rbp,rbp,rbp

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 7.03
- Reference cycles: 3.45
- UOPS_EXECUTED.THREAD: 14.01
- RETIRE_SLOTS: 14.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 7.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 7.01
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	c4 42 b9 f7 c0       	shlx   r8,r8,r8
   5:	c4 42 b1 f7 c9       	shlx   r9,r9,r9
   a:	c4 42 a9 f7 d2       	shlx   r10,r10,r10
   f:	c4 42 a1 f7 db       	shlx   r11,r11,r11
  14:	c4 42 99 f7 e4       	shlx   r12,r12,r12
  19:	c4 42 91 f7 ed       	shlx   r13,r13,r13
  1e:	c4 42 89 f7 f6       	shlx   r14,r14,r14
  23:	c4 e2 e1 f7 db       	shlx   rbx,rbx,rbx
  28:	c4 e2 f1 f7 c9       	shlx   rcx,rcx,rcx
  2d:	c4 e2 e9 f7 d2       	shlx   rdx,rdx,rdx
  32:	c4 e2 c1 f7 ff       	shlx   rdi,rdi,rdi
  37:	c4 e2 c9 f7 f6       	shlx   rsi,rsi,rsi
  3c:	c4 e2 d1 f7 ed       	shlx   rbp,rbp,rbp

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 13.2
- Core cycles: 6.57
- Reference cycles: 3.24
- UOPS_EXECUTED.THREAD: 13.1
- RETIRE_SLOTS: 13.1
- UOPS_MITE: 0.14
- UOPS_MS: 0.0
- UOPS_PORT_0: 6.55
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 6.55
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

SHLX (R64, R64, R64) - Throughput and Uops

With different registers for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 11 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With the same register for for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 13 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10