RDMSR - Throughput and Uops
With unroll_count=500 and no inner loop
- Code:
0: 0f 32 rdmsr
- Init:
MOV RCX, 0xE7
- Show nanoBench command
- Results:
- Instructions retired: 1.0
- Core cycles: 91.0
- Reference cycles: 45.48
- UOPS_EXECUTED.THREAD: 62.0
- RETIRE_SLOTS: 71.0
- UOPS_MITE: 0.0
- UOPS_MS: 71.0
- UOPS_PORT_0: 13.0
- UOPS_PORT_1: 12.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 21.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0
With unroll_count=500, no inner loop, and 1 NOP
- Code:
0: 0f 32 rdmsr
2: 90 nop
- Init:
MOV RCX, 0xE7
- Show nanoBench command
- Results:
- Instructions retired: 2.0
- Core cycles: 92.0
- Reference cycles: 45.9
- UOPS_EXECUTED.THREAD: 62.0
- RETIRE_SLOTS: 72.0
- UOPS_MITE: 1.0
- UOPS_MS: 71.0
- UOPS_PORT_0: 13.0
- UOPS_PORT_1: 12.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 21.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0
With loop_count=1000 and unroll_count=10
- Code:
0: 0f 32 rdmsr
- Init:
MOV RCX, 0xE7
- Show nanoBench command
- Results:
- Instructions retired: 1.2
- Core cycles: 92.3
- Reference cycles: 46.08
- UOPS_EXECUTED.THREAD: 62.1
- RETIRE_SLOTS: 71.1
- UOPS_MITE: 0.1
- UOPS_MS: 71.0
- UOPS_PORT_0: 12.8
- UOPS_PORT_1: 12.1
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 21.2
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.1
With loop_count=100 and unroll_count=100
- Code:
0: 0f 32 rdmsr
- Init:
MOV RCX, 0xE7
- Show nanoBench command
- Results:
- Instructions retired: 1.02
- Core cycles: 91.08
- Reference cycles: 45.47
- UOPS_EXECUTED.THREAD: 62.01
- RETIRE_SLOTS: 71.01
- UOPS_MITE: 0.01
- UOPS_MS: 71.0
- UOPS_PORT_0: 12.98
- UOPS_PORT_1: 12.01
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 21.02
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01