ADD (AL, I8) - Throughput and Uops

With unroll_count=500 and no inner loop

• Code:

     0:	04 02                	add    al,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.0
  • Core cycles: 1.0
  • Reference cycles: 0.52
  • UOPS_EXECUTED.THREAD: 1.0
  • RETIRE_SLOTS: 1.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.25
  • UOPS_PORT_1: 0.25
  • UOPS_PORT_5: 0.25
  • UOPS_PORT_6: 0.25
  • UOPS_PORT_23: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

• Code:

     0:	04 02                	add    al,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.2
  • Core cycles: 1.0
  • Reference cycles: 0.49
  • UOPS_EXECUTED.THREAD: 1.1
  • RETIRE_SLOTS: 1.1
  • UOPS_MITE: 0.03
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.25
  • UOPS_PORT_1: 0.25
  • UOPS_PORT_5: 0.25
  • UOPS_PORT_6: 0.35
  • UOPS_PORT_23: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=100

• Code:

     0:	04 02                	add    al,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.02
  • Core cycles: 1.0
  • Reference cycles: 0.5
  • UOPS_EXECUTED.THREAD: 1.01
  • RETIRE_SLOTS: 1.01
  • UOPS_MITE: 0.01
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.25
  • UOPS_PORT_1: 0.25
  • UOPS_PORT_5: 0.25
  • UOPS_PORT_6: 0.27
  • UOPS_PORT_23: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With additional dependency-breaking instructions

With unroll_count=500 and no inner loop

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	04 02                	add    al,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 0.62
  • Reference cycles: 0.42
  • UOPS_EXECUTED.THREAD: 1.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.23
  • UOPS_PORT_1: 0.22
  • UOPS_PORT_5: 0.26
  • UOPS_PORT_6: 0.29
  • UOPS_PORT_23: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.63

With loop_count=1000 and unroll_count=10

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	04 02                	add    al,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.2
  • Core cycles: 0.45
  • Reference cycles: 0.23
  • UOPS_EXECUTED.THREAD: 1.1
  • RETIRE_SLOTS: 2.1
  • UOPS_MITE: 0.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.25
  • UOPS_PORT_1: 0.27
  • UOPS_PORT_5: 0.27
  • UOPS_PORT_6: 0.31
  • UOPS_PORT_23: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	04 02                	add    al,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.02
  • Core cycles: 0.4
  • Reference cycles: 0.2
  • UOPS_EXECUTED.THREAD: 1.01
  • RETIRE_SLOTS: 2.01
  • UOPS_MITE: 0.02
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.25
  • UOPS_PORT_1: 0.25
  • UOPS_PORT_5: 0.25
  • UOPS_PORT_6: 0.26
  • UOPS_PORT_23: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With JB (Rel32)

• Code:

     0:	04 02                	add    al,0x2
     2:	0f 82 00 00 00 00    	jb     0x8
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.06
  • Reference cycles: 0.0
  • UOPS_EXECUTED.THREAD: 1.0
  • RETIRE_SLOTS: 1.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.33
  • UOPS_PORT_1: 0.01
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.67
  • UOPS_PORT_23: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.5

With JB (Rel8)

• Code:

     0:	04 02                	add    al,0x2
     2:	72 00                	jb     0x4
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.06
  • Reference cycles: 1.56
  • UOPS_EXECUTED.THREAD: 1.0
  • RETIRE_SLOTS: 1.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.33
  • UOPS_PORT_1: 0.01
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.67
  • UOPS_PORT_23: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.5

With JBE (Rel32)

• Code:

     0:	04 02                	add    al,0x2
     2:	0f 86 00 00 00 00    	jbe    0x8
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.06
  • Reference cycles: 0.0
  • UOPS_EXECUTED.THREAD: 1.0
  • RETIRE_SLOTS: 1.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.33
  • UOPS_PORT_1: 0.01
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.67
  • UOPS_PORT_23: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.5

With JBE (Rel8)

• Code:

     0:	04 02                	add    al,0x2
     2:	76 00                	jbe    0x4
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.06
  • Reference cycles: 0.0
  • UOPS_EXECUTED.THREAD: 1.0
  • RETIRE_SLOTS: 1.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.33
  • UOPS_PORT_1: 0.01
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.67
  • UOPS_PORT_23: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.5

With JL (Rel32)

• Code:

     0:	04 02                	add    al,0x2
     2:	0f 8c 00 00 00 00    	jl     0x8
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.13
  • Reference cycles: 1.39
  • UOPS_EXECUTED.THREAD: 1.04
  • RETIRE_SLOTS: 1.16
  • UOPS_MITE: 0.68
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.32
  • UOPS_PORT_1: 0.01
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.69
  • UOPS_PORT_23: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.43

With JL (Rel8)

• Code:

     0:	04 02                	add    al,0x2
     2:	7c 00                	jl     0x4
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.08
  • Reference cycles: 1.56
  • UOPS_EXECUTED.THREAD: 1.0
  • RETIRE_SLOTS: 1.0
  • UOPS_MITE: 0.9
  • UOPS_MS: 0.01
  • UOPS_PORT_0: 0.33
  • UOPS_PORT_1: 0.01
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.67
  • UOPS_PORT_23: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.45

With JLE (Rel32)

• Code:

     0:	04 02                	add    al,0x2
     2:	0f 8e 00 00 00 00    	jle    0x8
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.12
  • Reference cycles: 1.39
  • UOPS_EXECUTED.THREAD: 1.02
  • RETIRE_SLOTS: 1.08
  • UOPS_MITE: 0.73
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.32
  • UOPS_PORT_1: 0.01
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.69
  • UOPS_PORT_23: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.41

With JLE (Rel8)

• Code:

     0:	04 02                	add    al,0x2
     2:	7e 00                	jle    0x4
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.08
  • Reference cycles: 1.04
  • UOPS_EXECUTED.THREAD: 1.0
  • RETIRE_SLOTS: 1.0
  • UOPS_MITE: 0.88
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.33
  • UOPS_PORT_1: 0.01
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.67
  • UOPS_PORT_23: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.44

With JNB (Rel32)

• Code:

     0:	04 02                	add    al,0x2
     2:	0f 83 00 00 00 00    	jae    0x8
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.09
  • Reference cycles: 0.0
  • UOPS_EXECUTED.THREAD: 1.04
  • RETIRE_SLOTS: 1.16
  • UOPS_MITE: 0.37
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.34
  • UOPS_PORT_1: 0.01
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.67
  • UOPS_PORT_23: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.28

With JNB (Rel8)

• Code:

     0:	04 02                	add    al,0x2
     2:	73 00                	jae    0x4
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.08
  • Reference cycles: 0.52
  • UOPS_EXECUTED.THREAD: 1.0
  • RETIRE_SLOTS: 1.0
  • UOPS_MITE: 0.73
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.33
  • UOPS_PORT_1: 0.01
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.67
  • UOPS_PORT_23: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.4

With JNBE (Rel32)

• Code:

     0:	04 02                	add    al,0x2
     2:	0f 87 00 00 00 00    	ja     0x8
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.1
  • Reference cycles: 0.87
  • UOPS_EXECUTED.THREAD: 1.01
  • RETIRE_SLOTS: 1.05
  • UOPS_MITE: 0.4
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.33
  • UOPS_PORT_1: 0.01
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.68
  • UOPS_PORT_23: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.28

With JNBE (Rel8)

• Code:

     0:	04 02                	add    al,0x2
     2:	77 00                	ja     0x4
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.08
  • Reference cycles: 0.52
  • UOPS_EXECUTED.THREAD: 1.0
  • RETIRE_SLOTS: 1.0
  • UOPS_MITE: 0.71
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.36
  • UOPS_PORT_1: 0.01
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.64
  • UOPS_PORT_23: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.4

With JNL (Rel32)

• Code:

     0:	04 02                	add    al,0x2
     2:	0f 8d 00 00 00 00    	jge    0x8
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.08
  • Reference cycles: 0.87
  • UOPS_EXECUTED.THREAD: 1.0
  • RETIRE_SLOTS: 1.0
  • UOPS_MITE: 0.28
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.33
  • UOPS_PORT_1: 0.01
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.67
  • UOPS_PORT_23: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.2

With JNL (Rel8)

• Code:

     0:	04 02                	add    al,0x2
     2:	7d 00                	jge    0x4
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.06
  • Reference cycles: 1.04
  • UOPS_EXECUTED.THREAD: 1.0
  • RETIRE_SLOTS: 1.0
  • UOPS_MITE: 0.82
  • UOPS_MS: 0.01
  • UOPS_PORT_0: 0.33
  • UOPS_PORT_1: 0.01
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.67
  • UOPS_PORT_23: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.43

With JNLE (Rel32)

• Code:

     0:	04 02                	add    al,0x2
     2:	0f 8f 00 00 00 00    	jg     0x8
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.06
  • Reference cycles: 0.52
  • UOPS_EXECUTED.THREAD: 1.0
  • RETIRE_SLOTS: 1.0
  • UOPS_MITE: 0.29
  • UOPS_MS: 0.02
  • UOPS_PORT_0: 0.33
  • UOPS_PORT_1: 0.01
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.67
  • UOPS_PORT_23: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.2

With JNLE (Rel8)

• Code:

     0:	04 02                	add    al,0x2
     2:	7f 00                	jg     0x4
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.05
  • Reference cycles: 0.69
  • UOPS_EXECUTED.THREAD: 1.0
  • RETIRE_SLOTS: 1.0
  • UOPS_MITE: 0.75
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.33
  • UOPS_PORT_1: 0.01
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.67
  • UOPS_PORT_23: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.43

With JNO (Rel32)

• Code:

     0:	04 02                	add    al,0x2
     2:	0f 81 00 00 00 00    	jno    0x8
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.35
  • Reference cycles: 0.35
  • UOPS_EXECUTED.THREAD: 2.01
  • RETIRE_SLOTS: 2.03
  • UOPS_MITE: 1.2
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.51
  • UOPS_PORT_1: 0.38
  • UOPS_PORT_5: 0.37
  • UOPS_PORT_6: 0.76
  • UOPS_PORT_23: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.34

With JNO (Rel8)

• Code:

     0:	04 02                	add    al,0x2
     2:	71 00                	jno    0x4
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.3
  • Reference cycles: 0.17
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.6
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.52
  • UOPS_PORT_1: 0.37
  • UOPS_PORT_5: 0.39
  • UOPS_PORT_6: 0.74
  • UOPS_PORT_23: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.43

With JNP (Rel32)

• Code:

     0:	04 02                	add    al,0x2
     2:	0f 8b 00 00 00 00    	jnp    0x8
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.15
  • Reference cycles: 0.17
  • UOPS_EXECUTED.THREAD: 2.04
  • RETIRE_SLOTS: 2.16
  • UOPS_MITE: 0.12
  • UOPS_MS: 0.02
  • UOPS_PORT_0: 0.5
  • UOPS_PORT_1: 0.4
  • UOPS_PORT_5: 0.38
  • UOPS_PORT_6: 0.72
  • UOPS_PORT_23: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.08

With JNP (Rel8)

• Code:

     0:	04 02                	add    al,0x2
     2:	7b 00                	jnp    0x4
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.13
  • Reference cycles: 0.87
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.8
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.5
  • UOPS_PORT_1: 0.39
  • UOPS_PORT_5: 0.38
  • UOPS_PORT_6: 0.73
  • UOPS_PORT_23: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.36

With JNS (Rel32)

• Code:

     0:	04 02                	add    al,0x2
     2:	0f 89 00 00 00 00    	jns    0x8
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.17
  • Reference cycles: 0.0
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.29
  • UOPS_MS: 0.01
  • UOPS_PORT_0: 0.49
  • UOPS_PORT_1: 0.39
  • UOPS_PORT_5: 0.39
  • UOPS_PORT_6: 0.73
  • UOPS_PORT_23: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.4

With JNS (Rel8)

• Code:

     0:	04 02                	add    al,0x2
     2:	79 00                	jns    0x4
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.15
  • Reference cycles: 0.0
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.68
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.55
  • UOPS_PORT_1: 0.37
  • UOPS_PORT_5: 0.37
  • UOPS_PORT_6: 0.7
  • UOPS_PORT_23: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.44

With JNZ (Rel32)

• Code:

     0:	04 02                	add    al,0x2
     2:	0f 85 00 00 00 00    	jne    0x8
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.09
  • Reference cycles: 0.87
  • UOPS_EXECUTED.THREAD: 1.03
  • RETIRE_SLOTS: 1.13
  • UOPS_MITE: 0.36
  • UOPS_MS: 0.02
  • UOPS_PORT_0: 0.34
  • UOPS_PORT_1: 0.01
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.66
  • UOPS_PORT_23: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.3

With JNZ (Rel8)

• Code:

     0:	04 02                	add    al,0x2
     2:	75 00                	jne    0x4
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.08
  • Reference cycles: 0.87
  • UOPS_EXECUTED.THREAD: 1.0
  • RETIRE_SLOTS: 1.0
  • UOPS_MITE: 0.7
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.33
  • UOPS_PORT_1: 0.01
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.67
  • UOPS_PORT_23: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.39

With JO (Rel32)

• Code:

     0:	04 02                	add    al,0x2
     2:	0f 80 00 00 00 00    	jo     0x8
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.12
  • Reference cycles: 0.17
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.32
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.56
  • UOPS_PORT_1: 0.36
  • UOPS_PORT_5: 0.36
  • UOPS_PORT_6: 0.72
  • UOPS_PORT_23: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.32

With JO (Rel8)

• Code:

     0:	04 02                	add    al,0x2
     2:	70 00                	jo     0x4
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.12
  • Reference cycles: 0.87
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.56
  • UOPS_PORT_1: 0.36
  • UOPS_PORT_5: 0.36
  • UOPS_PORT_6: 0.71
  • UOPS_PORT_23: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.5

With JP (Rel32)

• Code:

     0:	04 02                	add    al,0x2
     2:	0f 8a 00 00 00 00    	jp     0x8
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.11
  • Reference cycles: 0.17
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 0.27
  • UOPS_MS: 0.02
  • UOPS_PORT_0: 0.54
  • UOPS_PORT_1: 0.38
  • UOPS_PORT_5: 0.38
  • UOPS_PORT_6: 0.71
  • UOPS_PORT_23: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.09

With JP (Rel8)

• Code:

     0:	04 02                	add    al,0x2
     2:	7a 00                	jp     0x4
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.12
  • Reference cycles: 0.17
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.54
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.52
  • UOPS_PORT_1: 0.39
  • UOPS_PORT_5: 0.38
  • UOPS_PORT_6: 0.71
  • UOPS_PORT_23: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.5

With JS (Rel32)

• Code:

     0:	04 02                	add    al,0x2
     2:	0f 88 00 00 00 00    	js     0x8
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.18
  • Reference cycles: 0.0
  • UOPS_EXECUTED.THREAD: 2.04
  • RETIRE_SLOTS: 2.16
  • UOPS_MITE: 1.56
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.55
  • UOPS_PORT_1: 0.37
  • UOPS_PORT_5: 0.37
  • UOPS_PORT_6: 0.73
  • UOPS_PORT_23: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.41

With JS (Rel8)

• Code:

     0:	04 02                	add    al,0x2
     2:	78 00                	js     0x4
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.18
  • Reference cycles: 0.0
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.88
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.52
  • UOPS_PORT_1: 0.39
  • UOPS_PORT_5: 0.4
  • UOPS_PORT_6: 0.7
  • UOPS_PORT_23: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.58

With JZ (Rel32)

• Code:

     0:	04 02                	add    al,0x2
     2:	0f 84 00 00 00 00    	je     0x8
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.06
  • Reference cycles: 0.0
  • UOPS_EXECUTED.THREAD: 1.0
  • RETIRE_SLOTS: 1.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.33
  • UOPS_PORT_1: 0.01
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.67
  • UOPS_PORT_23: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.5

With JZ (Rel8)

• Code:

     0:	04 02                	add    al,0x2
     2:	74 00                	je     0x4
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.06
  • Reference cycles: 0.52
  • UOPS_EXECUTED.THREAD: 1.0
  • RETIRE_SLOTS: 1.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.33
  • UOPS_PORT_1: 0.01
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.67
  • UOPS_PORT_23: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.5