ADD (M8, I8) - Throughput and Uops (IACA 2.1)


With a non-indexed addressing mode

With 1 independent instruction

Throughput Analysis Report
--------------------------
Block Throughput: 1.00 Cycles       Throughput Bottleneck: PORT2_AGU, Port2_DATA, PORT3_AGU, Port4

Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |
-------------------------------------------------------------------------
| Cycles | 0.3    0.0  | 0.3  | 1.0    1.0  | 1.0    0.0  | 1.0  | 0.3  |
-------------------------------------------------------------------------


| Num Of |              Ports pressure in cycles               |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |    |
---------------------------------------------------------------------
|   4^   | 0.3       | 0.3 | 1.0   1.0 | 1.0       | 1.0 | 0.3 | CP | add byte ptr [r14], 0x2
Total Num Of Uops: 4

With 16 independent instructions


Throughput Analysis Report
--------------------------
Block Throughput: 16.00 Cycles       Throughput Bottleneck: PORT2_AGU, Port2_DATA, PORT3_AGU, Port4

Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |
-------------------------------------------------------------------------
| Cycles | 5.3    0.0  | 5.3  | 16.0   16.0 | 16.0   0.0  | 16.0 | 5.3  |
-------------------------------------------------------------------------


| Num Of |              Ports pressure in cycles               |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |    |
---------------------------------------------------------------------
|   4^   | 0.3       | 0.3 | 1.0   1.0 | 1.0       | 1.0 | 0.3 | CP | add byte ptr [r14], 0x2
|   4^   | 0.3       | 0.3 | 1.0   1.0 | 1.0       | 1.0 | 0.3 | CP | add byte ptr [r14+0x1], 0x2
|   4^   | 0.3       | 0.3 | 1.0   1.0 | 1.0       | 1.0 | 0.3 | CP | add byte ptr [r14+0x2], 0x2
|   4^   | 0.3       | 0.3 | 1.0   1.0 | 1.0       | 1.0 | 0.3 | CP | add byte ptr [r14+0x3], 0x2
|   4^   | 0.3       | 0.3 | 1.0   1.0 | 1.0       | 1.0 | 0.3 | CP | add byte ptr [r14+0x4], 0x2
|   4^   | 0.3       | 0.3 | 1.0   1.0 | 1.0       | 1.0 | 0.3 | CP | add byte ptr [r14+0x5], 0x2
|   4^   | 0.3       | 0.3 | 1.0   1.0 | 1.0       | 1.0 | 0.3 | CP | add byte ptr [r14+0x6], 0x2
|   4^   | 0.3       | 0.3 | 1.0   1.0 | 1.0       | 1.0 | 0.3 | CP | add byte ptr [r14+0x7], 0x2
|   4^   | 0.3       | 0.3 | 1.0   1.0 | 1.0       | 1.0 | 0.3 | CP | add byte ptr [r14+0x8], 0x2
|   4^   | 0.3       | 0.3 | 1.0   1.0 | 1.0       | 1.0 | 0.3 | CP | add byte ptr [r14+0x9], 0x2
|   4^   | 0.3       | 0.3 | 1.0   1.0 | 1.0       | 1.0 | 0.3 | CP | add byte ptr [r14+0xa], 0x2
|   4^   | 0.3       | 0.3 | 1.0   1.0 | 1.0       | 1.0 | 0.3 | CP | add byte ptr [r14+0xb], 0x2
|   4^   | 0.3       | 0.3 | 1.0   1.0 | 1.0       | 1.0 | 0.3 | CP | add byte ptr [r14+0xc], 0x2
|   4^   | 0.3       | 0.3 | 1.0   1.0 | 1.0       | 1.0 | 0.3 | CP | add byte ptr [r14+0xd], 0x2
|   4^   | 0.3       | 0.3 | 1.0   1.0 | 1.0       | 1.0 | 0.3 | CP | add byte ptr [r14+0xe], 0x2
|   4^   | 0.3       | 0.3 | 1.0   1.0 | 1.0       | 1.0 | 0.3 | CP | add byte ptr [r14+0xf], 0x2
Total Num Of Uops: 64

With an indexed addressing mode

With 1 independent instruction

Throughput Analysis Report
--------------------------
Block Throughput: 1.00 Cycles       Throughput Bottleneck: FrontEnd, PORT2_AGU, Port2_DATA, PORT3_AGU, Port4

Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |
-------------------------------------------------------------------------
| Cycles | 0.3    0.0  | 0.3  | 1.0    1.0  | 1.0    0.0  | 1.0  | 0.3  |
-------------------------------------------------------------------------


| Num Of |              Ports pressure in cycles               |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |    |
---------------------------------------------------------------------
|   4    | 0.3       | 0.3 | 1.0   1.0 | 1.0       | 1.0 | 0.3 | CP | add byte ptr [r14+r13*1], 0x2
Total Num Of Uops: 4

With 16 independent instructions


Throughput Analysis Report
--------------------------
Block Throughput: 16.00 Cycles       Throughput Bottleneck: FrontEnd, PORT2_AGU, Port2_DATA, PORT3_AGU, Port4

Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |
-------------------------------------------------------------------------
| Cycles | 5.3    0.0  | 5.3  | 16.0   16.0 | 16.0   0.0  | 16.0 | 5.3  |
-------------------------------------------------------------------------


| Num Of |              Ports pressure in cycles               |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |    |
---------------------------------------------------------------------
|   4    | 0.3       | 0.3 | 1.0   1.0 | 1.0       | 1.0 | 0.3 | CP | add byte ptr [r14+r13*1], 0x2
|   4    | 0.3       | 0.3 | 1.0   1.0 | 1.0       | 1.0 | 0.3 | CP | add byte ptr [r14+r13*1+0x1], 0x2
|   4    | 0.3       | 0.3 | 1.0   1.0 | 1.0       | 1.0 | 0.3 | CP | add byte ptr [r14+r13*1+0x2], 0x2
|   4    | 0.3       | 0.3 | 1.0   1.0 | 1.0       | 1.0 | 0.3 | CP | add byte ptr [r14+r13*1+0x3], 0x2
|   4    | 0.3       | 0.3 | 1.0   1.0 | 1.0       | 1.0 | 0.3 | CP | add byte ptr [r14+r13*1+0x4], 0x2
|   4    | 0.3       | 0.3 | 1.0   1.0 | 1.0       | 1.0 | 0.3 | CP | add byte ptr [r14+r13*1+0x5], 0x2
|   4    | 0.3       | 0.3 | 1.0   1.0 | 1.0       | 1.0 | 0.3 | CP | add byte ptr [r14+r13*1+0x6], 0x2
|   4    | 0.3       | 0.3 | 1.0   1.0 | 1.0       | 1.0 | 0.3 | CP | add byte ptr [r14+r13*1+0x7], 0x2
|   4    | 0.3       | 0.3 | 1.0   1.0 | 1.0       | 1.0 | 0.3 | CP | add byte ptr [r14+r13*1+0x8], 0x2
|   4    | 0.3       | 0.3 | 1.0   1.0 | 1.0       | 1.0 | 0.3 | CP | add byte ptr [r14+r13*1+0x9], 0x2
|   4    | 0.3       | 0.3 | 1.0   1.0 | 1.0       | 1.0 | 0.3 | CP | add byte ptr [r14+r13*1+0xa], 0x2
|   4    | 0.3       | 0.3 | 1.0   1.0 | 1.0       | 1.0 | 0.3 | CP | add byte ptr [r14+r13*1+0xb], 0x2
|   4    | 0.3       | 0.3 | 1.0   1.0 | 1.0       | 1.0 | 0.3 | CP | add byte ptr [r14+r13*1+0xc], 0x2
|   4    | 0.3       | 0.3 | 1.0   1.0 | 1.0       | 1.0 | 0.3 | CP | add byte ptr [r14+r13*1+0xd], 0x2
|   4    | 0.3       | 0.3 | 1.0   1.0 | 1.0       | 1.0 | 0.3 | CP | add byte ptr [r14+r13*1+0xe], 0x2
|   4    | 0.3       | 0.3 | 1.0   1.0 | 1.0       | 1.0 | 0.3 | CP | add byte ptr [r14+r13*1+0xf], 0x2
Total Num Of Uops: 64

With the -no_interiteration flag

Throughput Analysis Report
--------------------------
Block Throughput: 1.00 Cycles       Throughput Bottleneck: PORT2_AGU, Port2_DATA, PORT3_AGU, Port4

Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |
-------------------------------------------------------------------------
| Cycles | 0.3    0.0  | 0.3  | 1.0    1.0  | 1.0    0.0  | 1.0  | 0.3  |
-------------------------------------------------------------------------


| Num Of |              Ports pressure in cycles               |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |    |
---------------------------------------------------------------------
|   4^   | 0.3       | 0.3 | 1.0   1.0 | 1.0       | 1.0 | 0.3 | CP | add byte ptr [r14], 0x2
Total Num Of Uops: 4