ADD (AL, I8) - Throughput and Uops

With unroll_count=500 and no inner loop

• Code:

     0:	04 02                	add    al,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.0
  • Core cycles: 1.0
  • Reference cycles: 0.84
  • UOPS_RETIRED.ANY: 1.0
  • RETIRE_SLOTS: 1.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.29
  • UOPS_PORT_1: 0.35
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • INST_DECODED.DEC0: 0.0

With loop_count=1000 and unroll_count=10

• Code:

     0:	04 02                	add    al,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.2
  • Core cycles: 1.0
  • Reference cycles: 0.83
  • UOPS_RETIRED.ANY: 1.2
  • RETIRE_SLOTS: 1.2
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.35
  • UOPS_PORT_1: 0.37
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • INST_DECODED.DEC0: 0.0

With loop_count=100 and unroll_count=100

• Code:

     0:	04 02                	add    al,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.02
  • Core cycles: 1.0
  • Reference cycles: 0.83
  • UOPS_RETIRED.ANY: 1.02
  • RETIRE_SLOTS: 1.02
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.3
  • UOPS_PORT_1: 0.36
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • INST_DECODED.DEC0: 0.0

With additional dependency-breaking instructions

With unroll_count=500 and no inner loop

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	04 02                	add    al,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 0.67
  • Reference cycles: 0.56
  • UOPS_RETIRED.ANY: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.66
  • UOPS_PORT_1: 0.66
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.67
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • INST_DECODED.DEC0: 0.0

With loop_count=1000 and unroll_count=10

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	04 02                	add    al,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.2
  • Core cycles: 0.74
  • Reference cycles: 0.61
  • UOPS_RETIRED.ANY: 2.2
  • RETIRE_SLOTS: 2.2
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.73
  • UOPS_PORT_1: 0.73
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.74
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • INST_DECODED.DEC0: 0.0

With loop_count=100 and unroll_count=100

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	04 02                	add    al,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.02
  • Core cycles: 0.68
  • Reference cycles: 0.56
  • UOPS_RETIRED.ANY: 2.02
  • RETIRE_SLOTS: 2.02
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.67
  • UOPS_PORT_1: 0.67
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.68
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • INST_DECODED.DEC0: 0.0

With JB (Rel32)

• Code:

     0:	04 02                	add    al,0x2
     2:	0f 82 00 00 00 00    	jb     0x8
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.0
  • Reference cycles: 0.8
  • UOPS_RETIRED.ANY: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.46
  • UOPS_PORT_1: 0.48
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • INST_DECODED.DEC0: 0.0

With JB (Rel8)

• Code:

     0:	04 02                	add    al,0x2
     2:	72 00                	jb     0x4
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.0
  • Reference cycles: 0.8
  • UOPS_RETIRED.ANY: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.46
  • UOPS_PORT_1: 0.48
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • INST_DECODED.DEC0: 0.0

With JBE (Rel32)

• Code:

     0:	04 02                	add    al,0x2
     2:	0f 86 00 00 00 00    	jbe    0x8
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.0
  • Reference cycles: 0.8
  • UOPS_RETIRED.ANY: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.46
  • UOPS_PORT_1: 0.48
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.99
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • INST_DECODED.DEC0: 0.0

With JBE (Rel8)

• Code:

     0:	04 02                	add    al,0x2
     2:	76 00                	jbe    0x4
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.0
  • Reference cycles: 0.8
  • UOPS_RETIRED.ANY: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.46
  • UOPS_PORT_1: 0.48
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.99
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • INST_DECODED.DEC0: 0.0

With JL (Rel32)

• Code:

     0:	04 02                	add    al,0x2
     2:	0f 8c 00 00 00 00    	jl     0x8
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.14
  • Reference cycles: 1.0
  • UOPS_RETIRED.ANY: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.45
  • UOPS_PORT_1: 0.49
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 1.13
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • INST_DECODED.DEC0: 0.0

With JL (Rel8)

• Code:

     0:	04 02                	add    al,0x2
     2:	7c 00                	jl     0x4
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.19
  • Reference cycles: 1.0
  • UOPS_RETIRED.ANY: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.45
  • UOPS_PORT_1: 0.49
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • INST_DECODED.DEC0: 0.0

With JLE (Rel32)

• Code:

     0:	04 02                	add    al,0x2
     2:	0f 8e 00 00 00 00    	jle    0x8
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.14
  • Reference cycles: 0.97
  • UOPS_RETIRED.ANY: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.45
  • UOPS_PORT_1: 0.49
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 1.13
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • INST_DECODED.DEC0: 0.0

With JLE (Rel8)

• Code:

     0:	04 02                	add    al,0x2
     2:	7e 00                	jle    0x4
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.19
  • Reference cycles: 1.0
  • UOPS_RETIRED.ANY: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.45
  • UOPS_PORT_1: 0.49
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 1.18
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • INST_DECODED.DEC0: 0.0

With JNB (Rel32)

• Code:

     0:	04 02                	add    al,0x2
     2:	0f 83 00 00 00 00    	jae    0x8
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.52
  • Reference cycles: 1.27
  • UOPS_RETIRED.ANY: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.4
  • UOPS_PORT_1: 0.54
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • INST_DECODED.DEC0: 0.0

With JNB (Rel8)

• Code:

     0:	04 02                	add    al,0x2
     2:	73 00                	jae    0x4
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 2.42
  • Reference cycles: 1.97
  • UOPS_RETIRED.ANY: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.41
  • UOPS_PORT_1: 0.53
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 1.67
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • INST_DECODED.DEC0: 0.0

With JNBE (Rel32)

• Code:

     0:	04 02                	add    al,0x2
     2:	0f 87 00 00 00 00    	ja     0x8
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.52
  • Reference cycles: 1.33
  • UOPS_RETIRED.ANY: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.4
  • UOPS_PORT_1: 0.54
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • INST_DECODED.DEC0: 0.0

With JNBE (Rel8)

• Code:

     0:	04 02                	add    al,0x2
     2:	77 00                	ja     0x4
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 2.42
  • Reference cycles: 2.0
  • UOPS_RETIRED.ANY: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.42
  • UOPS_PORT_1: 0.53
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • INST_DECODED.DEC0: 0.0

With JNL (Rel32)

• Code:

     0:	04 02                	add    al,0x2
     2:	0f 8d 00 00 00 00    	jge    0x8
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.16
  • Reference cycles: 1.0
  • UOPS_RETIRED.ANY: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.42
  • UOPS_PORT_1: 0.52
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • INST_DECODED.DEC0: 0.0

With JNL (Rel8)

• Code:

     0:	04 02                	add    al,0x2
     2:	7d 00                	jge    0x4
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.23
  • Reference cycles: 1.0
  • UOPS_RETIRED.ANY: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.42
  • UOPS_PORT_1: 0.52
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • INST_DECODED.DEC0: 0.0

With JNLE (Rel32)

• Code:

     0:	04 02                	add    al,0x2
     2:	0f 8f 00 00 00 00    	jg     0x8
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.16
  • Reference cycles: 1.0
  • UOPS_RETIRED.ANY: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.42
  • UOPS_PORT_1: 0.52
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • INST_DECODED.DEC0: 0.0

With JNLE (Rel8)

• Code:

     0:	04 02                	add    al,0x2
     2:	7f 00                	jg     0x4
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.97
  • Reference cycles: 1.57
  • UOPS_RETIRED.ANY: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.42
  • UOPS_PORT_1: 0.52
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • INST_DECODED.DEC0: 0.0

With JNO (Rel32)

• Code:

     0:	04 02                	add    al,0x2
     2:	0f 81 00 00 00 00    	jno    0x8
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.51
  • Reference cycles: 1.27
  • UOPS_RETIRED.ANY: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.41
  • UOPS_PORT_1: 0.53
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 1.5
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • INST_DECODED.DEC0: 0.0

With JNO (Rel8)

• Code:

     0:	04 02                	add    al,0x2
     2:	71 00                	jno    0x4
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.66
  • Reference cycles: 1.4
  • UOPS_RETIRED.ANY: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.42
  • UOPS_PORT_1: 0.52
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • INST_DECODED.DEC0: 0.0

With JNP (Rel32)

• Code:

     0:	04 02                	add    al,0x2
     2:	0f 8b 00 00 00 00    	jnp    0x8
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.0
  • Reference cycles: 0.8
  • UOPS_RETIRED.ANY: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.46
  • UOPS_PORT_1: 0.48
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • INST_DECODED.DEC0: 0.0

With JNP (Rel8)

• Code:

     0:	04 02                	add    al,0x2
     2:	7b 00                	jnp    0x4
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.0
  • Reference cycles: 0.8
  • UOPS_RETIRED.ANY: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.46
  • UOPS_PORT_1: 0.48
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.99
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • INST_DECODED.DEC0: 0.0

With JNS (Rel32)

• Code:

     0:	04 02                	add    al,0x2
     2:	0f 89 00 00 00 00    	jns    0x8
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.15
  • Reference cycles: 1.0
  • UOPS_RETIRED.ANY: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.42
  • UOPS_PORT_1: 0.52
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • INST_DECODED.DEC0: 0.0

With JNS (Rel8)

• Code:

     0:	04 02                	add    al,0x2
     2:	79 00                	jns    0x4
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.95
  • Reference cycles: 1.57
  • UOPS_RETIRED.ANY: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.43
  • UOPS_PORT_1: 0.51
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • INST_DECODED.DEC0: 0.0

With JNZ (Rel32)

• Code:

     0:	04 02                	add    al,0x2
     2:	0f 85 00 00 00 00    	jne    0x8
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.52
  • Reference cycles: 1.2
  • UOPS_RETIRED.ANY: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.4
  • UOPS_PORT_1: 0.54
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • INST_DECODED.DEC0: 0.0

With JNZ (Rel8)

• Code:

     0:	04 02                	add    al,0x2
     2:	75 00                	jne    0x4
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.68
  • Reference cycles: 1.4
  • UOPS_RETIRED.ANY: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.4
  • UOPS_PORT_1: 0.54
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • INST_DECODED.DEC0: 0.0

With JO (Rel32)

• Code:

     0:	04 02                	add    al,0x2
     2:	0f 80 00 00 00 00    	jo     0x8
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.0
  • Reference cycles: 0.8
  • UOPS_RETIRED.ANY: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.46
  • UOPS_PORT_1: 0.48
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • INST_DECODED.DEC0: 0.0

With JO (Rel8)

• Code:

     0:	04 02                	add    al,0x2
     2:	70 00                	jo     0x4
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.0
  • Reference cycles: 0.8
  • UOPS_RETIRED.ANY: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.46
  • UOPS_PORT_1: 0.48
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • INST_DECODED.DEC0: 0.0

With JP (Rel32)

• Code:

     0:	04 02                	add    al,0x2
     2:	0f 8a 00 00 00 00    	jp     0x8
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.0
  • Reference cycles: 0.8
  • UOPS_RETIRED.ANY: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.46
  • UOPS_PORT_1: 0.48
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • INST_DECODED.DEC0: 0.0

With JP (Rel8)

• Code:

     0:	04 02                	add    al,0x2
     2:	7a 00                	jp     0x4
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.0
  • Reference cycles: 0.8
  • UOPS_RETIRED.ANY: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.46
  • UOPS_PORT_1: 0.48
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.99
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • INST_DECODED.DEC0: 0.0

With JS (Rel32)

• Code:

     0:	04 02                	add    al,0x2
     2:	0f 88 00 00 00 00    	js     0x8
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.14
  • Reference cycles: 1.0
  • UOPS_RETIRED.ANY: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.45
  • UOPS_PORT_1: 0.49
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 1.13
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • INST_DECODED.DEC0: 0.0

With JS (Rel8)

• Code:

     0:	04 02                	add    al,0x2
     2:	78 00                	js     0x4
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.19
  • Reference cycles: 1.0
  • UOPS_RETIRED.ANY: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.45
  • UOPS_PORT_1: 0.49
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 1.18
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • INST_DECODED.DEC0: 0.0

With JZ (Rel32)

• Code:

     0:	04 02                	add    al,0x2
     2:	0f 84 00 00 00 00    	je     0x8
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.0
  • Reference cycles: 0.8
  • UOPS_RETIRED.ANY: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.46
  • UOPS_PORT_1: 0.48
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.99
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • INST_DECODED.DEC0: 0.0

With JZ (Rel8)

• Code:

     0:	04 02                	add    al,0x2
     2:	74 00                	je     0x4
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.0
  • Reference cycles: 0.8
  • UOPS_RETIRED.ANY: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.46
  • UOPS_PORT_1: 0.48
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • INST_DECODED.DEC0: 0.0