VPHADDD (YMM, YMM, YMM)

With unroll_count=500 and no inner loop

Code:

   0:	c4 e2 75 02 c2       	vphaddd ymm0,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 3.55
- Reference cycles: 2.83
- UOPS_RETIRED.ALL: 6.0
- UOPS_MS: 6.0

With loop_count=1000 and unroll_count=10

Code:

   0:	c4 e2 75 02 c2       	vphaddd ymm0,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 3.1
- Reference cycles: 2.45
- UOPS_RETIRED.ALL: 6.2
- UOPS_MS: 6.0

With loop_count=100 and unroll_count=100

Code:

   0:	c4 e2 75 02 c2       	vphaddd ymm0,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 3.54
- Reference cycles: 2.8
- UOPS_RETIRED.ALL: 6.02
- UOPS_MS: 6.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	c4 e2 75 02 c2       	vphaddd ymm0,ymm1,ymm2
   5:	c4 e2 75 02 da       	vphaddd ymm3,ymm1,ymm2
   a:	c4 e2 75 02 e2       	vphaddd ymm4,ymm1,ymm2
   f:	c4 e2 75 02 ea       	vphaddd ymm5,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 14.16
- Reference cycles: 11.18
- UOPS_RETIRED.ALL: 24.0
- UOPS_MS: 24.0

With loop_count=1000 and unroll_count=2

Code:

   0:	c4 e2 75 02 c2       	vphaddd ymm0,ymm1,ymm2
   5:	c4 e2 75 02 da       	vphaddd ymm3,ymm1,ymm2
   a:	c4 e2 75 02 e2       	vphaddd ymm4,ymm1,ymm2
   f:	c4 e2 75 02 ea       	vphaddd ymm5,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 14.01
- Reference cycles: 11.08
- UOPS_RETIRED.ALL: 25.0
- UOPS_MS: 24.0

With loop_count=100 and unroll_count=20

Code:

   0:	c4 e2 75 02 c2       	vphaddd ymm0,ymm1,ymm2
   5:	c4 e2 75 02 da       	vphaddd ymm3,ymm1,ymm2
   a:	c4 e2 75 02 e2       	vphaddd ymm4,ymm1,ymm2
   f:	c4 e2 75 02 ea       	vphaddd ymm5,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 14.04
- Reference cycles: 11.08
- UOPS_RETIRED.ALL: 24.1
- UOPS_MS: 24.0

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 e2 75 02 c2       	vphaddd ymm0,ymm1,ymm2
   5:	c4 e2 75 02 da       	vphaddd ymm3,ymm1,ymm2
   a:	c4 e2 75 02 e2       	vphaddd ymm4,ymm1,ymm2
   f:	c4 e2 75 02 ea       	vphaddd ymm5,ymm1,ymm2
  14:	c4 e2 75 02 f2       	vphaddd ymm6,ymm1,ymm2
  19:	c4 e2 75 02 fa       	vphaddd ymm7,ymm1,ymm2
  1e:	c4 62 75 02 c2       	vphaddd ymm8,ymm1,ymm2
  23:	c4 62 75 02 ca       	vphaddd ymm9,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 28.24
- Reference cycles: 21.97
- UOPS_RETIRED.ALL: 48.0
- UOPS_MS: 48.0

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 e2 75 02 c2       	vphaddd ymm0,ymm1,ymm2
   5:	c4 e2 75 02 da       	vphaddd ymm3,ymm1,ymm2
   a:	c4 e2 75 02 e2       	vphaddd ymm4,ymm1,ymm2
   f:	c4 e2 75 02 ea       	vphaddd ymm5,ymm1,ymm2
  14:	c4 e2 75 02 f2       	vphaddd ymm6,ymm1,ymm2
  19:	c4 e2 75 02 fa       	vphaddd ymm7,ymm1,ymm2
  1e:	c4 62 75 02 c2       	vphaddd ymm8,ymm1,ymm2
  23:	c4 62 75 02 ca       	vphaddd ymm9,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 28.02
- Reference cycles: 22.11
- UOPS_RETIRED.ALL: 50.0
- UOPS_MS: 48.0

With loop_count=100 and unroll_count=10

Code:

   0:	c4 e2 75 02 c2       	vphaddd ymm0,ymm1,ymm2
   5:	c4 e2 75 02 da       	vphaddd ymm3,ymm1,ymm2
   a:	c4 e2 75 02 e2       	vphaddd ymm4,ymm1,ymm2
   f:	c4 e2 75 02 ea       	vphaddd ymm5,ymm1,ymm2
  14:	c4 e2 75 02 f2       	vphaddd ymm6,ymm1,ymm2
  19:	c4 e2 75 02 fa       	vphaddd ymm7,ymm1,ymm2
  1e:	c4 62 75 02 c2       	vphaddd ymm8,ymm1,ymm2
  23:	c4 62 75 02 ca       	vphaddd ymm9,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 27.94
- Reference cycles: 22.07
- UOPS_RETIRED.ALL: 48.2
- UOPS_MS: 48.0

With 11 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 e2 75 02 c2       	vphaddd ymm0,ymm1,ymm2
   5:	c4 e2 75 02 da       	vphaddd ymm3,ymm1,ymm2
   a:	c4 e2 75 02 e2       	vphaddd ymm4,ymm1,ymm2
   f:	c4 e2 75 02 ea       	vphaddd ymm5,ymm1,ymm2
  14:	c4 e2 75 02 f2       	vphaddd ymm6,ymm1,ymm2
  19:	c4 e2 75 02 fa       	vphaddd ymm7,ymm1,ymm2
  1e:	c4 62 75 02 c2       	vphaddd ymm8,ymm1,ymm2
  23:	c4 62 75 02 ca       	vphaddd ymm9,ymm1,ymm2
  28:	c4 62 75 02 d2       	vphaddd ymm10,ymm1,ymm2
  2d:	c4 62 75 02 da       	vphaddd ymm11,ymm1,ymm2
  32:	c4 62 75 02 e2       	vphaddd ymm12,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 38.51
- Reference cycles: 30.68
- UOPS_RETIRED.ALL: 66.0
- UOPS_MS: 66.0

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 e2 75 02 c2       	vphaddd ymm0,ymm1,ymm2
   5:	c4 e2 75 02 da       	vphaddd ymm3,ymm1,ymm2
   a:	c4 e2 75 02 e2       	vphaddd ymm4,ymm1,ymm2
   f:	c4 e2 75 02 ea       	vphaddd ymm5,ymm1,ymm2
  14:	c4 e2 75 02 f2       	vphaddd ymm6,ymm1,ymm2
  19:	c4 e2 75 02 fa       	vphaddd ymm7,ymm1,ymm2
  1e:	c4 62 75 02 c2       	vphaddd ymm8,ymm1,ymm2
  23:	c4 62 75 02 ca       	vphaddd ymm9,ymm1,ymm2
  28:	c4 62 75 02 d2       	vphaddd ymm10,ymm1,ymm2
  2d:	c4 62 75 02 da       	vphaddd ymm11,ymm1,ymm2
  32:	c4 62 75 02 e2       	vphaddd ymm12,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 34.65
- Reference cycles: 27.35
- UOPS_RETIRED.ALL: 68.0
- UOPS_MS: 66.0

With loop_count=100 and unroll_count=10

Code:

   0:	c4 e2 75 02 c2       	vphaddd ymm0,ymm1,ymm2
   5:	c4 e2 75 02 da       	vphaddd ymm3,ymm1,ymm2
   a:	c4 e2 75 02 e2       	vphaddd ymm4,ymm1,ymm2
   f:	c4 e2 75 02 ea       	vphaddd ymm5,ymm1,ymm2
  14:	c4 e2 75 02 f2       	vphaddd ymm6,ymm1,ymm2
  19:	c4 e2 75 02 fa       	vphaddd ymm7,ymm1,ymm2
  1e:	c4 62 75 02 c2       	vphaddd ymm8,ymm1,ymm2
  23:	c4 62 75 02 ca       	vphaddd ymm9,ymm1,ymm2
  28:	c4 62 75 02 d2       	vphaddd ymm10,ymm1,ymm2
  2d:	c4 62 75 02 da       	vphaddd ymm11,ymm1,ymm2
  32:	c4 62 75 02 e2       	vphaddd ymm12,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 11.2
- Core cycles: 39.18
- Reference cycles: 30.99
- UOPS_RETIRED.ALL: 66.2
- UOPS_MS: 66.0

With the same register for for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	c4 e2 7d 02 c0       	vphaddd ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 3.81
- Reference cycles: 2.94
- UOPS_RETIRED.ALL: 6.0
- UOPS_MS: 6.0

With loop_count=1000 and unroll_count=10

Code:

   0:	c4 e2 7d 02 c0       	vphaddd ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 3.1
- Reference cycles: 2.45
- UOPS_RETIRED.ALL: 6.2
- UOPS_MS: 6.0

With loop_count=100 and unroll_count=100

Code:

   0:	c4 e2 7d 02 c0       	vphaddd ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 3.65
- Reference cycles: 2.88
- UOPS_RETIRED.ALL: 6.02
- UOPS_MS: 6.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	c4 e2 7d 02 c0       	vphaddd ymm0,ymm0,ymm0
   5:	c4 e2 75 02 c9       	vphaddd ymm1,ymm1,ymm1
   a:	c4 e2 6d 02 d2       	vphaddd ymm2,ymm2,ymm2
   f:	c4 e2 65 02 db       	vphaddd ymm3,ymm3,ymm3

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM3, YMM3, YMM3

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 14.16
- Reference cycles: 11.12
- UOPS_RETIRED.ALL: 24.0
- UOPS_MS: 24.0

With loop_count=1000 and unroll_count=2

Code:

   0:	c4 e2 7d 02 c0       	vphaddd ymm0,ymm0,ymm0
   5:	c4 e2 75 02 c9       	vphaddd ymm1,ymm1,ymm1
   a:	c4 e2 6d 02 d2       	vphaddd ymm2,ymm2,ymm2
   f:	c4 e2 65 02 db       	vphaddd ymm3,ymm3,ymm3

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM3, YMM3, YMM3

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 14.01
- Reference cycles: 11.08
- UOPS_RETIRED.ALL: 25.0
- UOPS_MS: 24.0

With loop_count=100 and unroll_count=20

Code:

   0:	c4 e2 7d 02 c0       	vphaddd ymm0,ymm0,ymm0
   5:	c4 e2 75 02 c9       	vphaddd ymm1,ymm1,ymm1
   a:	c4 e2 6d 02 d2       	vphaddd ymm2,ymm2,ymm2
   f:	c4 e2 65 02 db       	vphaddd ymm3,ymm3,ymm3

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM3, YMM3, YMM3

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 14.02
- Reference cycles: 11.06
- UOPS_RETIRED.ALL: 24.1
- UOPS_MS: 24.0

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 e2 7d 02 c0       	vphaddd ymm0,ymm0,ymm0
   5:	c4 e2 75 02 c9       	vphaddd ymm1,ymm1,ymm1
   a:	c4 e2 6d 02 d2       	vphaddd ymm2,ymm2,ymm2
   f:	c4 e2 65 02 db       	vphaddd ymm3,ymm3,ymm3
  14:	c4 e2 5d 02 e4       	vphaddd ymm4,ymm4,ymm4
  19:	c4 e2 55 02 ed       	vphaddd ymm5,ymm5,ymm5
  1e:	c4 e2 4d 02 f6       	vphaddd ymm6,ymm6,ymm6
  23:	c4 e2 45 02 ff       	vphaddd ymm7,ymm7,ymm7

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM3, YMM3, YMM3;
VXORPS YMM4, YMM4, YMM4;
VXORPS YMM5, YMM5, YMM5;
VXORPS YMM6, YMM6, YMM6;
VXORPS YMM7, YMM7, YMM7

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 28.25
- Reference cycles: 22.36
- UOPS_RETIRED.ALL: 48.0
- UOPS_MS: 48.0

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 e2 7d 02 c0       	vphaddd ymm0,ymm0,ymm0
   5:	c4 e2 75 02 c9       	vphaddd ymm1,ymm1,ymm1
   a:	c4 e2 6d 02 d2       	vphaddd ymm2,ymm2,ymm2
   f:	c4 e2 65 02 db       	vphaddd ymm3,ymm3,ymm3
  14:	c4 e2 5d 02 e4       	vphaddd ymm4,ymm4,ymm4
  19:	c4 e2 55 02 ed       	vphaddd ymm5,ymm5,ymm5
  1e:	c4 e2 4d 02 f6       	vphaddd ymm6,ymm6,ymm6
  23:	c4 e2 45 02 ff       	vphaddd ymm7,ymm7,ymm7

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM3, YMM3, YMM3;
VXORPS YMM4, YMM4, YMM4;
VXORPS YMM5, YMM5, YMM5;
VXORPS YMM6, YMM6, YMM6;
VXORPS YMM7, YMM7, YMM7

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 28.02
- Reference cycles: 22.1
- UOPS_RETIRED.ALL: 50.0
- UOPS_MS: 48.0

With loop_count=100 and unroll_count=10

Code:

   0:	c4 e2 7d 02 c0       	vphaddd ymm0,ymm0,ymm0
   5:	c4 e2 75 02 c9       	vphaddd ymm1,ymm1,ymm1
   a:	c4 e2 6d 02 d2       	vphaddd ymm2,ymm2,ymm2
   f:	c4 e2 65 02 db       	vphaddd ymm3,ymm3,ymm3
  14:	c4 e2 5d 02 e4       	vphaddd ymm4,ymm4,ymm4
  19:	c4 e2 55 02 ed       	vphaddd ymm5,ymm5,ymm5
  1e:	c4 e2 4d 02 f6       	vphaddd ymm6,ymm6,ymm6
  23:	c4 e2 45 02 ff       	vphaddd ymm7,ymm7,ymm7

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM3, YMM3, YMM3;
VXORPS YMM4, YMM4, YMM4;
VXORPS YMM5, YMM5, YMM5;
VXORPS YMM6, YMM6, YMM6;
VXORPS YMM7, YMM7, YMM7

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 28.01
- Reference cycles: 22.17
- UOPS_RETIRED.ALL: 48.2
- UOPS_MS: 48.0

With 13 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 e2 7d 02 c0       	vphaddd ymm0,ymm0,ymm0
   5:	c4 e2 75 02 c9       	vphaddd ymm1,ymm1,ymm1
   a:	c4 e2 6d 02 d2       	vphaddd ymm2,ymm2,ymm2
   f:	c4 e2 65 02 db       	vphaddd ymm3,ymm3,ymm3
  14:	c4 e2 5d 02 e4       	vphaddd ymm4,ymm4,ymm4
  19:	c4 e2 55 02 ed       	vphaddd ymm5,ymm5,ymm5
  1e:	c4 e2 4d 02 f6       	vphaddd ymm6,ymm6,ymm6
  23:	c4 e2 45 02 ff       	vphaddd ymm7,ymm7,ymm7
  28:	c4 42 3d 02 c0       	vphaddd ymm8,ymm8,ymm8
  2d:	c4 42 35 02 c9       	vphaddd ymm9,ymm9,ymm9
  32:	c4 42 2d 02 d2       	vphaddd ymm10,ymm10,ymm10
  37:	c4 42 25 02 db       	vphaddd ymm11,ymm11,ymm11
  3c:	c4 42 1d 02 e4       	vphaddd ymm12,ymm12,ymm12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM3, YMM3, YMM3;
VXORPS YMM4, YMM4, YMM4;
VXORPS YMM5, YMM5, YMM5;
VXORPS YMM6, YMM6, YMM6;
VXORPS YMM7, YMM7, YMM7;
VXORPS YMM8, YMM8, YMM8;
VXORPS YMM9, YMM9, YMM9;
VXORPS YMM10, YMM10, YMM10;
VXORPS YMM11, YMM11, YMM11;
VXORPS YMM12, YMM12, YMM12

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 45.9
- Reference cycles: 36.53
- UOPS_RETIRED.ALL: 78.0
- UOPS_MS: 78.0

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 e2 7d 02 c0       	vphaddd ymm0,ymm0,ymm0
   5:	c4 e2 75 02 c9       	vphaddd ymm1,ymm1,ymm1
   a:	c4 e2 6d 02 d2       	vphaddd ymm2,ymm2,ymm2
   f:	c4 e2 65 02 db       	vphaddd ymm3,ymm3,ymm3
  14:	c4 e2 5d 02 e4       	vphaddd ymm4,ymm4,ymm4
  19:	c4 e2 55 02 ed       	vphaddd ymm5,ymm5,ymm5
  1e:	c4 e2 4d 02 f6       	vphaddd ymm6,ymm6,ymm6
  23:	c4 e2 45 02 ff       	vphaddd ymm7,ymm7,ymm7
  28:	c4 42 3d 02 c0       	vphaddd ymm8,ymm8,ymm8
  2d:	c4 42 35 02 c9       	vphaddd ymm9,ymm9,ymm9
  32:	c4 42 2d 02 d2       	vphaddd ymm10,ymm10,ymm10
  37:	c4 42 25 02 db       	vphaddd ymm11,ymm11,ymm11
  3c:	c4 42 1d 02 e4       	vphaddd ymm12,ymm12,ymm12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM3, YMM3, YMM3;
VXORPS YMM4, YMM4, YMM4;
VXORPS YMM5, YMM5, YMM5;
VXORPS YMM6, YMM6, YMM6;
VXORPS YMM7, YMM7, YMM7;
VXORPS YMM8, YMM8, YMM8;
VXORPS YMM9, YMM9, YMM9;
VXORPS YMM10, YMM10, YMM10;
VXORPS YMM11, YMM11, YMM11;
VXORPS YMM12, YMM12, YMM12

Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 40.72
- Reference cycles: 32.12
- UOPS_RETIRED.ALL: 80.0
- UOPS_MS: 78.0

With loop_count=100 and unroll_count=10

Code:

   0:	c4 e2 7d 02 c0       	vphaddd ymm0,ymm0,ymm0
   5:	c4 e2 75 02 c9       	vphaddd ymm1,ymm1,ymm1
   a:	c4 e2 6d 02 d2       	vphaddd ymm2,ymm2,ymm2
   f:	c4 e2 65 02 db       	vphaddd ymm3,ymm3,ymm3
  14:	c4 e2 5d 02 e4       	vphaddd ymm4,ymm4,ymm4
  19:	c4 e2 55 02 ed       	vphaddd ymm5,ymm5,ymm5
  1e:	c4 e2 4d 02 f6       	vphaddd ymm6,ymm6,ymm6
  23:	c4 e2 45 02 ff       	vphaddd ymm7,ymm7,ymm7
  28:	c4 42 3d 02 c0       	vphaddd ymm8,ymm8,ymm8
  2d:	c4 42 35 02 c9       	vphaddd ymm9,ymm9,ymm9
  32:	c4 42 2d 02 d2       	vphaddd ymm10,ymm10,ymm10
  37:	c4 42 25 02 db       	vphaddd ymm11,ymm11,ymm11
  3c:	c4 42 1d 02 e4       	vphaddd ymm12,ymm12,ymm12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM3, YMM3, YMM3;
VXORPS YMM4, YMM4, YMM4;
VXORPS YMM5, YMM5, YMM5;
VXORPS YMM6, YMM6, YMM6;
VXORPS YMM7, YMM7, YMM7;
VXORPS YMM8, YMM8, YMM8;
VXORPS YMM9, YMM9, YMM9;
VXORPS YMM10, YMM10, YMM10;
VXORPS YMM11, YMM11, YMM11;
VXORPS YMM12, YMM12, YMM12

Show nanoBench command
Results:
- Instructions retired: 13.2
- Core cycles: 46.48
- Reference cycles: 36.71
- UOPS_RETIRED.ALL: 78.2
- UOPS_MS: 78.0

VPHADDD (YMM, YMM, YMM) - Throughput and Uops

With different registers for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 11 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With the same register for for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 13 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10