RDMSR - Throughput and Uops
With unroll_count=500 and no inner loop
- Code:
0: 0f 32 rdmsr
- Init:
MOV RCX, 0xE7
- Show nanoBench command
- Results:
- Instructions retired: 1.0
- Core cycles: 91.05
- Reference cycles: 78.15
- UOPS_EXECUTED.THREAD: 80.0
- RETIRE_SLOTS: 83.0
- UOPS_MITE: 0.0
- UOPS_MS: 83.0
- UOPS_PORT_0: 17.0
- UOPS_PORT_1: 17.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 30.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0
With unroll_count=500, no inner loop, and 1 NOP
- Code:
0: 0f 32 rdmsr
2: 90 nop
- Init:
MOV RCX, 0xE7
- Show nanoBench command
- Results:
- Instructions retired: 2.0
- Core cycles: 92.14
- Reference cycles: 79.05
- UOPS_EXECUTED.THREAD: 80.0
- RETIRE_SLOTS: 84.0
- UOPS_MITE: 1.0
- UOPS_MS: 83.0
- UOPS_PORT_0: 17.0
- UOPS_PORT_1: 17.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 30.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0
With loop_count=1000 and unroll_count=10
- Code:
0: 0f 32 rdmsr
- Init:
MOV RCX, 0xE7
- Show nanoBench command
- Results:
- Instructions retired: 1.2
- Core cycles: 92.2
- Reference cycles: 79.21
- UOPS_EXECUTED.THREAD: 80.1
- RETIRE_SLOTS: 83.1
- UOPS_MITE: 0.1
- UOPS_MS: 83.0
- UOPS_PORT_0: 17.0
- UOPS_PORT_1: 16.9
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 16.1
- UOPS_PORT_6: 30.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.1
With loop_count=100 and unroll_count=100
- Code:
0: 0f 32 rdmsr
- Init:
MOV RCX, 0xE7
- Show nanoBench command
- Results:
- Instructions retired: 1.02
- Core cycles: 91.08
- Reference cycles: 78.26
- UOPS_EXECUTED.THREAD: 80.01
- RETIRE_SLOTS: 83.01
- UOPS_MITE: 0.01
- UOPS_MS: 83.0
- UOPS_PORT_0: 16.98
- UOPS_PORT_1: 17.01
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 30.02
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01