BZHI (R32, R32, R32) - Throughput and Uops

With different registers for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 0.5
- Reference cycles: 0.3
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 0.5
- Reference cycles: 0.43
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 0.5
- Reference cycles: 0.43
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d
   5:	c4 42 28 f5 d9       	bzhi   r11d,r9d,r10d
   a:	c4 42 28 f5 e1       	bzhi   r12d,r9d,r10d
   f:	c4 42 28 f5 e9       	bzhi   r13d,r9d,r10d

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 2.0
- Reference cycles: 1.5
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 2.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d
   5:	c4 42 28 f5 d9       	bzhi   r11d,r9d,r10d
   a:	c4 42 28 f5 e1       	bzhi   r12d,r9d,r10d
   f:	c4 42 28 f5 e9       	bzhi   r13d,r9d,r10d

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 2.0
- Reference cycles: 1.73
- UOPS_EXECUTED.THREAD: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 2.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d
   5:	c4 42 28 f5 d9       	bzhi   r11d,r9d,r10d
   a:	c4 42 28 f5 e1       	bzhi   r12d,r9d,r10d
   f:	c4 42 28 f5 e9       	bzhi   r13d,r9d,r10d

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 2.0
- Reference cycles: 1.7
- UOPS_EXECUTED.THREAD: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 2.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d
   5:	c4 42 28 f5 d9       	bzhi   r11d,r9d,r10d
   a:	c4 42 28 f5 e1       	bzhi   r12d,r9d,r10d
   f:	c4 42 28 f5 e9       	bzhi   r13d,r9d,r10d
  14:	c4 42 28 f5 f1       	bzhi   r14d,r9d,r10d
  19:	c4 c2 28 f5 d9       	bzhi   ebx,r9d,r10d
  1e:	c4 c2 28 f5 c9       	bzhi   ecx,r9d,r10d
  23:	c4 c2 28 f5 d1       	bzhi   edx,r9d,r10d

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 4.0
- Reference cycles: 3.5
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d
   5:	c4 42 28 f5 d9       	bzhi   r11d,r9d,r10d
   a:	c4 42 28 f5 e1       	bzhi   r12d,r9d,r10d
   f:	c4 42 28 f5 e9       	bzhi   r13d,r9d,r10d
  14:	c4 42 28 f5 f1       	bzhi   r14d,r9d,r10d
  19:	c4 c2 28 f5 d9       	bzhi   ebx,r9d,r10d
  1e:	c4 c2 28 f5 c9       	bzhi   ecx,r9d,r10d
  23:	c4 c2 28 f5 d1       	bzhi   edx,r9d,r10d

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 4.01
- Reference cycles: 3.33
- UOPS_EXECUTED.THREAD: 9.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d
   5:	c4 42 28 f5 d9       	bzhi   r11d,r9d,r10d
   a:	c4 42 28 f5 e1       	bzhi   r12d,r9d,r10d
   f:	c4 42 28 f5 e9       	bzhi   r13d,r9d,r10d
  14:	c4 42 28 f5 f1       	bzhi   r14d,r9d,r10d
  19:	c4 c2 28 f5 d9       	bzhi   ebx,r9d,r10d
  1e:	c4 c2 28 f5 c9       	bzhi   ecx,r9d,r10d
  23:	c4 c2 28 f5 d1       	bzhi   edx,r9d,r10d

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 4.01
- Reference cycles: 3.43
- UOPS_EXECUTED.THREAD: 8.1
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 11 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d
   5:	c4 42 28 f5 d9       	bzhi   r11d,r9d,r10d
   a:	c4 42 28 f5 e1       	bzhi   r12d,r9d,r10d
   f:	c4 42 28 f5 e9       	bzhi   r13d,r9d,r10d
  14:	c4 42 28 f5 f1       	bzhi   r14d,r9d,r10d
  19:	c4 c2 28 f5 d9       	bzhi   ebx,r9d,r10d
  1e:	c4 c2 28 f5 c9       	bzhi   ecx,r9d,r10d
  23:	c4 c2 28 f5 d1       	bzhi   edx,r9d,r10d
  28:	c4 c2 28 f5 f9       	bzhi   edi,r9d,r10d
  2d:	c4 c2 28 f5 f1       	bzhi   esi,r9d,r10d
  32:	c4 c2 28 f5 e9       	bzhi   ebp,r9d,r10d

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 5.5
- Reference cycles: 4.75
- UOPS_EXECUTED.THREAD: 11.0
- RETIRE_SLOTS: 11.0
- UOPS_MITE: 11.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 5.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 5.5
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.75

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d
   5:	c4 42 28 f5 d9       	bzhi   r11d,r9d,r10d
   a:	c4 42 28 f5 e1       	bzhi   r12d,r9d,r10d
   f:	c4 42 28 f5 e9       	bzhi   r13d,r9d,r10d
  14:	c4 42 28 f5 f1       	bzhi   r14d,r9d,r10d
  19:	c4 c2 28 f5 d9       	bzhi   ebx,r9d,r10d
  1e:	c4 c2 28 f5 c9       	bzhi   ecx,r9d,r10d
  23:	c4 c2 28 f5 d1       	bzhi   edx,r9d,r10d
  28:	c4 c2 28 f5 f9       	bzhi   edi,r9d,r10d
  2d:	c4 c2 28 f5 f1       	bzhi   esi,r9d,r10d
  32:	c4 c2 28 f5 e9       	bzhi   ebp,r9d,r10d

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 5.51
- Reference cycles: 4.8
- UOPS_EXECUTED.THREAD: 12.0
- RETIRE_SLOTS: 12.0
- UOPS_MITE: 12.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 5.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 5.5
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 3.03

With loop_count=100 and unroll_count=10

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d
   5:	c4 42 28 f5 d9       	bzhi   r11d,r9d,r10d
   a:	c4 42 28 f5 e1       	bzhi   r12d,r9d,r10d
   f:	c4 42 28 f5 e9       	bzhi   r13d,r9d,r10d
  14:	c4 42 28 f5 f1       	bzhi   r14d,r9d,r10d
  19:	c4 c2 28 f5 d9       	bzhi   ebx,r9d,r10d
  1e:	c4 c2 28 f5 c9       	bzhi   ecx,r9d,r10d
  23:	c4 c2 28 f5 d1       	bzhi   edx,r9d,r10d
  28:	c4 c2 28 f5 f9       	bzhi   edi,r9d,r10d
  2d:	c4 c2 28 f5 f1       	bzhi   esi,r9d,r10d
  32:	c4 c2 28 f5 e9       	bzhi   ebp,r9d,r10d

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 11.2
- Core cycles: 5.51
- Reference cycles: 4.78
- UOPS_EXECUTED.THREAD: 11.1
- RETIRE_SLOTS: 11.1
- UOPS_MITE: 0.11
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 5.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 5.5
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.03

With the same register for for different operands

With unroll_count=500 and no inner loop

Code:

   0:	c4 42 38 f5 c0       	bzhi   r8d,r8d,r8d

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.75
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	c4 42 38 f5 c0       	bzhi   r8d,r8d,r8d

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 0.86
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	c4 42 38 f5 c0       	bzhi   r8d,r8d,r8d

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 0.87
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

Tests for macro-fusion

With JB (Rel32)

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d
   5:	0f 82 00 00 00 00    	jb     0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 0.74
- Reference cycles: 1.0
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.43
- UOPS_PORT_1: 0.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.57
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.61

With JB (Rel8)

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d
   5:	72 00                	jb     0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 0.75
- Reference cycles: 1.0
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.44
- UOPS_PORT_1: 0.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.56
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.54

With JBE (Rel32)

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d
   5:	0f 86 00 00 00 00    	jbe    0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.19
- Reference cycles: 1.0
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.71
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 0.47
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.52
- UOPS_PORT_6: 0.99
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.93

With JBE (Rel8)

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d
   5:	76 00                	jbe    0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.32
- Reference cycles: 1.0
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.75
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.48
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.53
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.9

With JL (Rel32)

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d
   5:	0f 8c 00 00 00 00    	jl     0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 0.75
- Reference cycles: 1.0
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.43
- UOPS_PORT_1: 0.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.57
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.61

With JL (Rel8)

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d
   5:	7c 00                	jl     0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 0.75
- Reference cycles: 1.0
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.44
- UOPS_PORT_1: 0.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.56
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.54

With JLE (Rel32)

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d
   5:	0f 8e 00 00 00 00    	jle    0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.16
- Reference cycles: 0.75
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.62
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 0.48
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.51
- UOPS_PORT_6: 0.99
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.03

With JLE (Rel8)

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d
   5:	7e 00                	jle    0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.25
- Reference cycles: 1.0
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 1.7
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.48
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.52
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.89

With JNB (Rel32)

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d
   5:	0f 83 00 00 00 00    	jae    0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.2
- Reference cycles: 1.5
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.75
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 0.47
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.52
- UOPS_PORT_6: 0.99
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.91

With JNB (Rel8)

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d
   5:	73 00                	jae    0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.31
- Reference cycles: 1.0
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.63
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.48
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.52
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.83

With JNBE (Rel32)

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d
   5:	0f 87 00 00 00 00    	ja     0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 0.76
- Reference cycles: 0.75
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.43
- UOPS_PORT_1: 0.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.57
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.61

With JNBE (Rel8)

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d
   5:	77 00                	ja     0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 0.76
- Reference cycles: 1.0
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.44
- UOPS_PORT_1: 0.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.56
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.54

With JNL (Rel32)

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d
   5:	0f 8d 00 00 00 00    	jge    0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.21
- Reference cycles: 1.0
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.68
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 0.48
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.51
- UOPS_PORT_6: 0.99
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.92

With JNL (Rel8)

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d
   5:	7d 00                	jge    0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.21
- Reference cycles: 0.75
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.77
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.47
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.52
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.92

With JNLE (Rel32)

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d
   5:	0f 8f 00 00 00 00    	jg     0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 0.76
- Reference cycles: 1.25
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.43
- UOPS_PORT_1: 0.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.57
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.61

With JNLE (Rel8)

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d
   5:	7f 00                	jg     0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 0.75
- Reference cycles: 1.0
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.44
- UOPS_PORT_1: 0.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.56
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.54

With JNO (Rel32)

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d
   5:	0f 81 00 00 00 00    	jno    0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.43
- Reference cycles: 1.0
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.7
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 0.47
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.53
- UOPS_PORT_6: 0.99
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.95

With JNO (Rel8)

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d
   5:	71 00                	jno    0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.33
- Reference cycles: 1.0
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.74
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.47
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.52
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.9

With JNP (Rel32)

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d
   5:	0f 8b 00 00 00 00    	jnp    0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.15
- Reference cycles: 1.0
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.56
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 0.48
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.53
- UOPS_PORT_6: 0.99
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.93

With JNP (Rel8)

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d
   5:	7b 00                	jnp    0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.23
- Reference cycles: 1.0
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.68
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.47
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.53
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.9

With JNS (Rel32)

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d
   5:	0f 89 00 00 00 00    	jns    0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.17
- Reference cycles: 1.0
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.68
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 0.48
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.52
- UOPS_PORT_6: 0.99
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.98

With JNS (Rel8)

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d
   5:	79 00                	jns    0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.24
- Reference cycles: 1.0
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.74
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.48
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.52
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.84

With JNZ (Rel32)

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d
   5:	0f 85 00 00 00 00    	jne    0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 0.75
- Reference cycles: 1.0
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.43
- UOPS_PORT_1: 0.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.57
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.61

With JNZ (Rel8)

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d
   5:	75 00                	jne    0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 0.75
- Reference cycles: 1.0
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.44
- UOPS_PORT_1: 0.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.56
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.54

With JO (Rel32)

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d
   5:	0f 80 00 00 00 00    	jo     0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 0.75
- Reference cycles: 1.0
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.43
- UOPS_PORT_1: 0.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.57
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.61

With JO (Rel8)

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d
   5:	70 00                	jo     0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 0.75
- Reference cycles: 1.0
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.44
- UOPS_PORT_1: 0.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.56
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.54

With JP (Rel32)

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d
   5:	0f 8a 00 00 00 00    	jp     0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 0.76
- Reference cycles: 1.0
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.43
- UOPS_PORT_1: 0.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.57
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.61

With JP (Rel8)

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d
   5:	7a 00                	jp     0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 0.76
- Reference cycles: 0.75
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.44
- UOPS_PORT_1: 0.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.56
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.54

With JS (Rel32)

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d
   5:	0f 88 00 00 00 00    	js     0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 0.75
- Reference cycles: 1.0
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.43
- UOPS_PORT_1: 0.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.57
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.61

With JS (Rel8)

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d
   5:	78 00                	js     0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 0.75
- Reference cycles: 1.0
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.44
- UOPS_PORT_1: 0.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.56
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.54

With JZ (Rel32)

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d
   5:	0f 84 00 00 00 00    	je     0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.38
- Reference cycles: 0.75
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.8
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 0.47
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.52
- UOPS_PORT_6: 0.99
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.88

With JZ (Rel8)

Code:

   0:	c4 42 28 f5 c1       	bzhi   r8d,r9d,r10d
   5:	74 00                	je     0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.16
- Reference cycles: 0.75
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.78
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.52
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.83