ADD (R64, I8) - Throughput and Uops

With unroll_count=500 and no inner loop

• Code:

     0:	49 83 c0 02          	add    r8,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.0
  • Core cycles: 1.0
  • Reference cycles: 0.9
  • UOPS_EXECUTED.THREAD: 1.0
  • RETIRE_SLOTS: 1.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.24
  • UOPS_PORT_1: 0.25
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.25
  • UOPS_PORT_6: 0.26
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

• Code:

     0:	49 83 c0 02          	add    r8,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.2
  • Core cycles: 1.0
  • Reference cycles: 0.86
  • UOPS_EXECUTED.THREAD: 1.1
  • RETIRE_SLOTS: 1.1
  • UOPS_MITE: 0.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.25
  • UOPS_PORT_1: 0.25
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.25
  • UOPS_PORT_6: 0.35
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

• Code:

     0:	49 83 c0 02          	add    r8,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.02
  • Core cycles: 1.0
  • Reference cycles: 0.87
  • UOPS_EXECUTED.THREAD: 1.01
  • RETIRE_SLOTS: 1.01
  • UOPS_MITE: 0.01
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.25
  • UOPS_PORT_1: 0.25
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.25
  • UOPS_PORT_6: 0.27
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With unroll_count=200 and no inner loop

• Code:

     0:	49 83 c0 02          	add    r8,0x2
     4:	49 83 c1 02          	add    r9,0x2
     8:	49 83 c2 02          	add    r10,0x2
     c:	49 83 c3 02          	add    r11,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 1.0
  • Reference cycles: 0.88
  • UOPS_EXECUTED.THREAD: 4.0
  • RETIRE_SLOTS: 4.0
  • UOPS_MITE: 4.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.0
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 1.0
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

• Code:

     0:	49 83 c0 02          	add    r8,0x2
     4:	49 83 c1 02          	add    r9,0x2
     8:	49 83 c2 02          	add    r10,0x2
     c:	49 83 c3 02          	add    r11,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 1.37
  • Reference cycles: 1.16
  • UOPS_EXECUTED.THREAD: 4.5
  • RETIRE_SLOTS: 4.5
  • UOPS_MITE: 0.04
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.04
  • UOPS_PORT_1: 1.05
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 1.07
  • UOPS_PORT_6: 1.34
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=20

• Code:

     0:	49 83 c0 02          	add    r8,0x2
     4:	49 83 c1 02          	add    r9,0x2
     8:	49 83 c2 02          	add    r10,0x2
     c:	49 83 c3 02          	add    r11,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 4.1
  • Core cycles: 1.16
  • Reference cycles: 1.01
  • UOPS_EXECUTED.THREAD: 4.05
  • RETIRE_SLOTS: 4.05
  • UOPS_MITE: 0.04
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.99
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 1.02
  • UOPS_PORT_6: 1.04
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With unroll_count=100 and no inner loop

• Code:

     0:	49 83 c0 02          	add    r8,0x2
     4:	49 83 c1 02          	add    r9,0x2
     8:	49 83 c2 02          	add    r10,0x2
     c:	49 83 c3 02          	add    r11,0x2
    10:	49 83 c4 02          	add    r12,0x2
    14:	49 83 c5 02          	add    r13,0x2
    18:	49 83 c6 02          	add    r14,0x2
    1c:	48 83 c3 02          	add    rbx,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 8.0
  • Core cycles: 2.0
  • Reference cycles: 1.5
  • UOPS_EXECUTED.THREAD: 8.0
  • RETIRE_SLOTS: 8.0
  • UOPS_MITE: 8.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.0
  • UOPS_PORT_1: 2.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 2.0
  • UOPS_PORT_6: 2.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	49 83 c0 02          	add    r8,0x2
     4:	49 83 c1 02          	add    r9,0x2
     8:	49 83 c2 02          	add    r10,0x2
     c:	49 83 c3 02          	add    r11,0x2
    10:	49 83 c4 02          	add    r12,0x2
    14:	49 83 c5 02          	add    r13,0x2
    18:	49 83 c6 02          	add    r14,0x2
    1c:	48 83 c3 02          	add    rbx,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 10.0
  • Core cycles: 2.28
  • Reference cycles: 1.98
  • UOPS_EXECUTED.THREAD: 9.02
  • RETIRE_SLOTS: 9.0
  • UOPS_MITE: 0.09
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.25
  • UOPS_PORT_1: 2.26
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 2.26
  • UOPS_PORT_6: 2.26
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.03

With loop_count=100 and unroll_count=10

• Code:

     0:	49 83 c0 02          	add    r8,0x2
     4:	49 83 c1 02          	add    r9,0x2
     8:	49 83 c2 02          	add    r10,0x2
     c:	49 83 c3 02          	add    r11,0x2
    10:	49 83 c4 02          	add    r12,0x2
    14:	49 83 c5 02          	add    r13,0x2
    18:	49 83 c6 02          	add    r14,0x2
    1c:	48 83 c3 02          	add    rbx,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 8.2
  • Core cycles: 2.05
  • Reference cycles: 1.75
  • UOPS_EXECUTED.THREAD: 8.12
  • RETIRE_SLOTS: 8.1
  • UOPS_MITE: 0.08
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.03
  • UOPS_PORT_1: 2.03
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 2.03
  • UOPS_PORT_6: 2.03
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.02

With unroll_count=100 and no inner loop

• Code:

     0:	49 83 c0 02          	add    r8,0x2
     4:	49 83 c1 02          	add    r9,0x2
     8:	49 83 c2 02          	add    r10,0x2
     c:	49 83 c3 02          	add    r11,0x2
    10:	49 83 c4 02          	add    r12,0x2
    14:	49 83 c5 02          	add    r13,0x2
    18:	49 83 c6 02          	add    r14,0x2
    1c:	48 83 c3 02          	add    rbx,0x2
    20:	48 83 c1 02          	add    rcx,0x2
    24:	48 83 c2 02          	add    rdx,0x2
    28:	48 83 c7 02          	add    rdi,0x2
    2c:	48 83 c6 02          	add    rsi,0x2
    30:	48 83 c5 02          	add    rbp,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 13.0
  • Core cycles: 3.25
  • Reference cycles: 2.5
  • UOPS_EXECUTED.THREAD: 13.0
  • RETIRE_SLOTS: 13.0
  • UOPS_MITE: 13.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 3.24
  • UOPS_PORT_1: 3.25
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 3.25
  • UOPS_PORT_6: 3.26
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 3.25

With loop_count=1000 and unroll_count=1

• Code:

     0:	49 83 c0 02          	add    r8,0x2
     4:	49 83 c1 02          	add    r9,0x2
     8:	49 83 c2 02          	add    r10,0x2
     c:	49 83 c3 02          	add    r11,0x2
    10:	49 83 c4 02          	add    r12,0x2
    14:	49 83 c5 02          	add    r13,0x2
    18:	49 83 c6 02          	add    r14,0x2
    1c:	48 83 c3 02          	add    rbx,0x2
    20:	48 83 c1 02          	add    rcx,0x2
    24:	48 83 c2 02          	add    rdx,0x2
    28:	48 83 c7 02          	add    rdi,0x2
    2c:	48 83 c6 02          	add    rsi,0x2
    30:	48 83 c5 02          	add    rbp,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 15.0
  • Core cycles: 3.52
  • Reference cycles: 3.08
  • UOPS_EXECUTED.THREAD: 14.03
  • RETIRE_SLOTS: 14.0
  • UOPS_MITE: 0.01
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 3.51
  • UOPS_PORT_1: 3.51
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 3.51
  • UOPS_PORT_6: 3.51
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

• Code:

     0:	49 83 c0 02          	add    r8,0x2
     4:	49 83 c1 02          	add    r9,0x2
     8:	49 83 c2 02          	add    r10,0x2
     c:	49 83 c3 02          	add    r11,0x2
    10:	49 83 c4 02          	add    r12,0x2
    14:	49 83 c5 02          	add    r13,0x2
    18:	49 83 c6 02          	add    r14,0x2
    1c:	48 83 c3 02          	add    rbx,0x2
    20:	48 83 c1 02          	add    rcx,0x2
    24:	48 83 c2 02          	add    rdx,0x2
    28:	48 83 c7 02          	add    rdi,0x2
    2c:	48 83 c6 02          	add    rsi,0x2
    30:	48 83 c5 02          	add    rbp,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 13.2
  • Core cycles: 3.3
  • Reference cycles: 2.83
  • UOPS_EXECUTED.THREAD: 13.13
  • RETIRE_SLOTS: 13.1
  • UOPS_MITE: 0.13
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 3.28
  • UOPS_PORT_1: 3.28
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 3.28
  • UOPS_PORT_6: 3.28
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.03

With JB (Rel32)

• Code:

     0:	49 83 c0 02          	add    r8,0x2
     4:	0f 82 00 00 00 00    	jb     0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.07
  • Reference cycles: 1.25
  • UOPS_EXECUTED.THREAD: 1.0
  • RETIRE_SLOTS: 1.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.37
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.63
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.54

With JB (Rel8)

• Code:

     0:	49 83 c0 02          	add    r8,0x2
     4:	72 00                	jb     0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.07
  • Reference cycles: 1.0
  • UOPS_EXECUTED.THREAD: 1.0
  • RETIRE_SLOTS: 1.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.37
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.63
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.54

With JBE (Rel32)

• Code:

     0:	49 83 c0 02          	add    r8,0x2
     4:	0f 86 00 00 00 00    	jbe    0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.07
  • Reference cycles: 0.5
  • UOPS_EXECUTED.THREAD: 1.0
  • RETIRE_SLOTS: 1.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.37
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.63
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.54

With JBE (Rel8)

• Code:

     0:	49 83 c0 02          	add    r8,0x2
     4:	76 00                	jbe    0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.07
  • Reference cycles: 1.0
  • UOPS_EXECUTED.THREAD: 1.0
  • RETIRE_SLOTS: 1.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.37
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.63
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.54

With JL (Rel32)

• Code:

     0:	49 83 c0 02          	add    r8,0x2
     4:	0f 8c 00 00 00 00    	jl     0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.07
  • Reference cycles: 0.75
  • UOPS_EXECUTED.THREAD: 1.0
  • RETIRE_SLOTS: 1.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.37
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.63
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.54

With JL (Rel8)

• Code:

     0:	49 83 c0 02          	add    r8,0x2
     4:	7c 00                	jl     0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.07
  • Reference cycles: 1.0
  • UOPS_EXECUTED.THREAD: 1.0
  • RETIRE_SLOTS: 1.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.37
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.63
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.54

With JLE (Rel32)

• Code:

     0:	49 83 c0 02          	add    r8,0x2
     4:	0f 8e 00 00 00 00    	jle    0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.07
  • Reference cycles: 1.25
  • UOPS_EXECUTED.THREAD: 1.0
  • RETIRE_SLOTS: 1.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.37
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.63
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.54

With JLE (Rel8)

• Code:

     0:	49 83 c0 02          	add    r8,0x2
     4:	7e 00                	jle    0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.07
  • Reference cycles: 1.25
  • UOPS_EXECUTED.THREAD: 1.0
  • RETIRE_SLOTS: 1.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.37
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.63
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.54

With JNB (Rel32)

• Code:

     0:	49 83 c0 02          	add    r8,0x2
     4:	0f 83 00 00 00 00    	jae    0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.13
  • Reference cycles: 1.0
  • UOPS_EXECUTED.THREAD: 1.02
  • RETIRE_SLOTS: 1.02
  • UOPS_MITE: 0.72
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.01
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.02
  • UOPS_PORT_6: 0.99
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.64

With JNB (Rel8)

• Code:

     0:	49 83 c0 02          	add    r8,0x2
     4:	73 00                	jae    0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.12
  • Reference cycles: 1.0
  • UOPS_EXECUTED.THREAD: 1.0
  • RETIRE_SLOTS: 1.0
  • UOPS_MITE: 0.84
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.01
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.99
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.83

With JNBE (Rel32)

• Code:

     0:	49 83 c0 02          	add    r8,0x2
     4:	0f 87 00 00 00 00    	ja     0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.12
  • Reference cycles: 1.25
  • UOPS_EXECUTED.THREAD: 1.02
  • RETIRE_SLOTS: 1.02
  • UOPS_MITE: 0.68
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.01
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.02
  • UOPS_PORT_6: 0.99
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.64

With JNBE (Rel8)

• Code:

     0:	49 83 c0 02          	add    r8,0x2
     4:	77 00                	ja     0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.12
  • Reference cycles: 1.0
  • UOPS_EXECUTED.THREAD: 1.01
  • RETIRE_SLOTS: 1.01
  • UOPS_MITE: 0.82
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.01
  • UOPS_PORT_1: 0.01
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.01
  • UOPS_PORT_6: 0.99
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.83

With JNL (Rel32)

• Code:

     0:	49 83 c0 02          	add    r8,0x2
     4:	0f 8d 00 00 00 00    	jge    0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.12
  • Reference cycles: 1.25
  • UOPS_EXECUTED.THREAD: 1.02
  • RETIRE_SLOTS: 1.02
  • UOPS_MITE: 0.65
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.01
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.02
  • UOPS_PORT_6: 0.99
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.66

With JNL (Rel8)

• Code:

     0:	49 83 c0 02          	add    r8,0x2
     4:	7d 00                	jge    0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.1
  • Reference cycles: 1.25
  • UOPS_EXECUTED.THREAD: 1.02
  • RETIRE_SLOTS: 1.02
  • UOPS_MITE: 0.78
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.01
  • UOPS_PORT_1: 0.01
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.01
  • UOPS_PORT_6: 0.99
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.79

With JNLE (Rel32)

• Code:

     0:	49 83 c0 02          	add    r8,0x2
     4:	0f 8f 00 00 00 00    	jg     0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.12
  • Reference cycles: 1.25
  • UOPS_EXECUTED.THREAD: 1.01
  • RETIRE_SLOTS: 1.01
  • UOPS_MITE: 0.77
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.01
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.02
  • UOPS_PORT_6: 0.99
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.68

With JNLE (Rel8)

• Code:

     0:	49 83 c0 02          	add    r8,0x2
     4:	7f 00                	jg     0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.11
  • Reference cycles: 1.0
  • UOPS_EXECUTED.THREAD: 1.01
  • RETIRE_SLOTS: 1.01
  • UOPS_MITE: 0.8
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.01
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.01
  • UOPS_PORT_6: 0.99
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.81

With JNO (Rel32)

• Code:

     0:	49 83 c0 02          	add    r8,0x2
     4:	0f 81 00 00 00 00    	jno    0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.34
  • Reference cycles: 1.0
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.45
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.31
  • UOPS_PORT_1: 0.31
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.37
  • UOPS_PORT_6: 0.99
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.64

With JNO (Rel8)

• Code:

     0:	49 83 c0 02          	add    r8,0x2
     4:	71 00                	jno    0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.16
  • Reference cycles: 0.75
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.62
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.32
  • UOPS_PORT_1: 0.31
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.37
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.86

With JNP (Rel32)

• Code:

     0:	49 83 c0 02          	add    r8,0x2
     4:	0f 8b 00 00 00 00    	jnp    0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.1
  • Reference cycles: 0.75
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.29
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.49
  • UOPS_PORT_1: 0.4
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.43
  • UOPS_PORT_6: 0.68
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.44

With JNP (Rel8)

• Code:

     0:	49 83 c0 02          	add    r8,0x2
     4:	7b 00                	jnp    0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.09
  • Reference cycles: 1.0
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.12
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.46
  • UOPS_PORT_1: 0.39
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.46
  • UOPS_PORT_6: 0.71
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.4

With JNS (Rel32)

• Code:

     0:	49 83 c0 02          	add    r8,0x2
     4:	0f 89 00 00 00 00    	jns    0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.41
  • Reference cycles: 1.0
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.33
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.32
  • UOPS_PORT_1: 0.3
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.38
  • UOPS_PORT_6: 0.99
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.71

With JNS (Rel8)

• Code:

     0:	49 83 c0 02          	add    r8,0x2
     4:	79 00                	jns    0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.28
  • Reference cycles: 1.0
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.72
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.32
  • UOPS_PORT_1: 0.31
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.37
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.87

With JNZ (Rel32)

• Code:

     0:	49 83 c0 02          	add    r8,0x2
     4:	0f 85 00 00 00 00    	jne    0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.12
  • Reference cycles: 1.0
  • UOPS_EXECUTED.THREAD: 1.02
  • RETIRE_SLOTS: 1.02
  • UOPS_MITE: 0.66
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.01
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.02
  • UOPS_PORT_6: 0.99
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.65

With JNZ (Rel8)

• Code:

     0:	49 83 c0 02          	add    r8,0x2
     4:	75 00                	jne    0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.12
  • Reference cycles: 1.0
  • UOPS_EXECUTED.THREAD: 1.02
  • RETIRE_SLOTS: 1.02
  • UOPS_MITE: 0.81
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.01
  • UOPS_PORT_1: 0.01
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.01
  • UOPS_PORT_6: 0.99
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.83

With JO (Rel32)

• Code:

     0:	49 83 c0 02          	add    r8,0x2
     4:	0f 80 00 00 00 00    	jo     0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.09
  • Reference cycles: 1.0
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.52
  • UOPS_PORT_1: 0.41
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.42
  • UOPS_PORT_6: 0.65
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.57

With JO (Rel8)

• Code:

     0:	49 83 c0 02          	add    r8,0x2
     4:	70 00                	jo     0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.1
  • Reference cycles: 0.75
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.53
  • UOPS_PORT_1: 0.42
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.42
  • UOPS_PORT_6: 0.63
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.57

With JP (Rel32)

• Code:

     0:	49 83 c0 02          	add    r8,0x2
     4:	0f 8a 00 00 00 00    	jp     0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.1
  • Reference cycles: 0.75
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.24
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.44
  • UOPS_PORT_1: 0.43
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.45
  • UOPS_PORT_6: 0.69
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.42

With JP (Rel8)

• Code:

     0:	49 83 c0 02          	add    r8,0x2
     4:	7a 00                	jp     0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.09
  • Reference cycles: 0.75
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.43
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.48
  • UOPS_PORT_1: 0.4
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.45
  • UOPS_PORT_6: 0.67
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.53

With JS (Rel32)

• Code:

     0:	49 83 c0 02          	add    r8,0x2
     4:	0f 88 00 00 00 00    	js     0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.08
  • Reference cycles: 0.75
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.53
  • UOPS_PORT_1: 0.41
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.41
  • UOPS_PORT_6: 0.65
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.56

With JS (Rel8)

• Code:

     0:	49 83 c0 02          	add    r8,0x2
     4:	78 00                	js     0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.09
  • Reference cycles: 1.0
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.52
  • UOPS_PORT_1: 0.41
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.43
  • UOPS_PORT_6: 0.65
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.57

With JZ (Rel32)

• Code:

     0:	49 83 c0 02          	add    r8,0x2
     4:	0f 84 00 00 00 00    	je     0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.07
  • Reference cycles: 1.25
  • UOPS_EXECUTED.THREAD: 1.0
  • RETIRE_SLOTS: 1.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.37
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.63
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.54

With JZ (Rel8)

• Code:

     0:	49 83 c0 02          	add    r8,0x2
     4:	74 00                	je     0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.07
  • Reference cycles: 1.25
  • UOPS_EXECUTED.THREAD: 1.0
  • RETIRE_SLOTS: 1.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.37
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.63
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.54