VAESENC (XMM, XMM, XMM) - Throughput and Uops

With unroll_count=500 and no inner loop

• Code:

     0:	c4 e2 71 dc c2       	vaesenc xmm0,xmm1,xmm2
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1;
  VXORPS XMM2, XMM2, XMM2

• Show nanoBench command
• Results:
  • Instructions retired: 1.0
  • Core cycles: 1.28
  • Reference cycles: 1.41
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.5
  • UOPS_PORT_1: 0.48
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 1.02
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

• Code:

     0:	c4 e2 71 dc c2       	vaesenc xmm0,xmm1,xmm2
     5:	90                   	nop
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1;
  VXORPS XMM2, XMM2, XMM2

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 2.0
  • Reference cycles: 2.21
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 3.0
  • UOPS_MITE: 3.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.57
  • UOPS_PORT_1: 0.43
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 1.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

• Code:

     0:	c4 e2 71 dc c2       	vaesenc xmm0,xmm1,xmm2
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1;
  VXORPS XMM2, XMM2, XMM2

• Show nanoBench command
• Results:
  • Instructions retired: 1.2
  • Core cycles: 1.29
  • Reference cycles: 1.43
  • UOPS_EXECUTED.THREAD: 2.1
  • RETIRE_SLOTS: 2.1
  • UOPS_MITE: 0.01
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.49
  • UOPS_PORT_1: 0.49
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 1.12
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

• Code:

     0:	c4 e2 71 dc c2       	vaesenc xmm0,xmm1,xmm2
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1;
  VXORPS XMM2, XMM2, XMM2

• Show nanoBench command
• Results:
  • Instructions retired: 1.02
  • Core cycles: 1.3
  • Reference cycles: 1.43
  • UOPS_EXECUTED.THREAD: 2.02
  • RETIRE_SLOTS: 2.01
  • UOPS_MITE: 0.02
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.5
  • UOPS_PORT_1: 0.48
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 1.03
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With unroll_count=200 and no inner loop

• Code:

     0:	c4 e2 71 dc c2       	vaesenc xmm0,xmm1,xmm2
     5:	c4 e2 71 dc da       	vaesenc xmm3,xmm1,xmm2
     a:	c4 e2 71 dc e2       	vaesenc xmm4,xmm1,xmm2
     f:	c4 e2 71 dc ea       	vaesenc xmm5,xmm1,xmm2
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1;
  VXORPS XMM2, XMM2, XMM2

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 5.28
  • Reference cycles: 5.81
  • UOPS_EXECUTED.THREAD: 8.0
  • RETIRE_SLOTS: 8.0
  • UOPS_MITE: 8.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.01
  • UOPS_PORT_1: 1.93
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 4.07
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

• Code:

     0:	c4 e2 71 dc c2       	vaesenc xmm0,xmm1,xmm2
     5:	c4 e2 71 dc da       	vaesenc xmm3,xmm1,xmm2
     a:	c4 e2 71 dc e2       	vaesenc xmm4,xmm1,xmm2
     f:	c4 e2 71 dc ea       	vaesenc xmm5,xmm1,xmm2
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1;
  VXORPS XMM2, XMM2, XMM2

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 5.16
  • Reference cycles: 5.69
  • UOPS_EXECUTED.THREAD: 8.51
  • RETIRE_SLOTS: 8.5
  • UOPS_MITE: 0.01
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.97
  • UOPS_PORT_1: 1.97
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 4.57
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

• Code:

     0:	c4 e2 71 dc c2       	vaesenc xmm0,xmm1,xmm2
     5:	c4 e2 71 dc da       	vaesenc xmm3,xmm1,xmm2
     a:	c4 e2 71 dc e2       	vaesenc xmm4,xmm1,xmm2
     f:	c4 e2 71 dc ea       	vaesenc xmm5,xmm1,xmm2
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1;
  VXORPS XMM2, XMM2, XMM2

• Show nanoBench command
• Results:
  • Instructions retired: 4.1
  • Core cycles: 5.16
  • Reference cycles: 5.69
  • UOPS_EXECUTED.THREAD: 8.09
  • RETIRE_SLOTS: 8.05
  • UOPS_MITE: 0.08
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.0
  • UOPS_PORT_1: 1.95
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 4.13
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.04

With unroll_count=100 and no inner loop

• Code:

     0:	c4 e2 71 dc c2       	vaesenc xmm0,xmm1,xmm2
     5:	c4 e2 71 dc da       	vaesenc xmm3,xmm1,xmm2
     a:	c4 e2 71 dc e2       	vaesenc xmm4,xmm1,xmm2
     f:	c4 e2 71 dc ea       	vaesenc xmm5,xmm1,xmm2
    14:	c4 e2 71 dc f2       	vaesenc xmm6,xmm1,xmm2
    19:	c4 e2 71 dc fa       	vaesenc xmm7,xmm1,xmm2
    1e:	c4 62 71 dc c2       	vaesenc xmm8,xmm1,xmm2
    23:	c4 62 71 dc ca       	vaesenc xmm9,xmm1,xmm2
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1;
  VXORPS XMM2, XMM2, XMM2

• Show nanoBench command
• Results:
  • Instructions retired: 8.0
  • Core cycles: 10.54
  • Reference cycles: 10.29
  • UOPS_EXECUTED.THREAD: 16.0
  • RETIRE_SLOTS: 16.0
  • UOPS_MITE: 16.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 4.0
  • UOPS_PORT_1: 3.85
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 8.15
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	c4 e2 71 dc c2       	vaesenc xmm0,xmm1,xmm2
     5:	c4 e2 71 dc da       	vaesenc xmm3,xmm1,xmm2
     a:	c4 e2 71 dc e2       	vaesenc xmm4,xmm1,xmm2
     f:	c4 e2 71 dc ea       	vaesenc xmm5,xmm1,xmm2
    14:	c4 e2 71 dc f2       	vaesenc xmm6,xmm1,xmm2
    19:	c4 e2 71 dc fa       	vaesenc xmm7,xmm1,xmm2
    1e:	c4 62 71 dc c2       	vaesenc xmm8,xmm1,xmm2
    23:	c4 62 71 dc ca       	vaesenc xmm9,xmm1,xmm2
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1;
  VXORPS XMM2, XMM2, XMM2

• Show nanoBench command
• Results:
  • Instructions retired: 10.0
  • Core cycles: 10.48
  • Reference cycles: 10.18
  • UOPS_EXECUTED.THREAD: 17.07
  • RETIRE_SLOTS: 17.0
  • UOPS_MITE: 0.02
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 3.96
  • UOPS_PORT_1: 3.96
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 9.14
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

• Code:

     0:	c4 e2 71 dc c2       	vaesenc xmm0,xmm1,xmm2
     5:	c4 e2 71 dc da       	vaesenc xmm3,xmm1,xmm2
     a:	c4 e2 71 dc e2       	vaesenc xmm4,xmm1,xmm2
     f:	c4 e2 71 dc ea       	vaesenc xmm5,xmm1,xmm2
    14:	c4 e2 71 dc f2       	vaesenc xmm6,xmm1,xmm2
    19:	c4 e2 71 dc fa       	vaesenc xmm7,xmm1,xmm2
    1e:	c4 62 71 dc c2       	vaesenc xmm8,xmm1,xmm2
    23:	c4 62 71 dc ca       	vaesenc xmm9,xmm1,xmm2
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1;
  VXORPS XMM2, XMM2, XMM2

• Show nanoBench command
• Results:
  • Instructions retired: 8.2
  • Core cycles: 10.49
  • Reference cycles: 10.17
  • UOPS_EXECUTED.THREAD: 16.18
  • RETIRE_SLOTS: 16.1
  • UOPS_MITE: 0.17
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 4.0
  • UOPS_PORT_1: 3.91
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 8.27
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.08

With unroll_count=100 and no inner loop

• Code:

     0:	c4 e2 71 dc c2       	vaesenc xmm0,xmm1,xmm2
     5:	c4 e2 71 dc da       	vaesenc xmm3,xmm1,xmm2
     a:	c4 e2 71 dc e2       	vaesenc xmm4,xmm1,xmm2
     f:	c4 e2 71 dc ea       	vaesenc xmm5,xmm1,xmm2
    14:	c4 e2 71 dc f2       	vaesenc xmm6,xmm1,xmm2
    19:	c4 e2 71 dc fa       	vaesenc xmm7,xmm1,xmm2
    1e:	c4 62 71 dc c2       	vaesenc xmm8,xmm1,xmm2
    23:	c4 62 71 dc ca       	vaesenc xmm9,xmm1,xmm2
    28:	c4 62 71 dc d2       	vaesenc xmm10,xmm1,xmm2
    2d:	c4 62 71 dc da       	vaesenc xmm11,xmm1,xmm2
    32:	c4 62 71 dc e2       	vaesenc xmm12,xmm1,xmm2
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1;
  VXORPS XMM2, XMM2, XMM2

• Show nanoBench command
• Results:
  • Instructions retired: 11.0
  • Core cycles: 14.71
  • Reference cycles: 14.24
  • UOPS_EXECUTED.THREAD: 22.0
  • RETIRE_SLOTS: 22.0
  • UOPS_MITE: 22.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 5.42
  • UOPS_PORT_1: 5.39
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 11.2
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 11.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	c4 e2 71 dc c2       	vaesenc xmm0,xmm1,xmm2
     5:	c4 e2 71 dc da       	vaesenc xmm3,xmm1,xmm2
     a:	c4 e2 71 dc e2       	vaesenc xmm4,xmm1,xmm2
     f:	c4 e2 71 dc ea       	vaesenc xmm5,xmm1,xmm2
    14:	c4 e2 71 dc f2       	vaesenc xmm6,xmm1,xmm2
    19:	c4 e2 71 dc fa       	vaesenc xmm7,xmm1,xmm2
    1e:	c4 62 71 dc c2       	vaesenc xmm8,xmm1,xmm2
    23:	c4 62 71 dc ca       	vaesenc xmm9,xmm1,xmm2
    28:	c4 62 71 dc d2       	vaesenc xmm10,xmm1,xmm2
    2d:	c4 62 71 dc da       	vaesenc xmm11,xmm1,xmm2
    32:	c4 62 71 dc e2       	vaesenc xmm12,xmm1,xmm2
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1;
  VXORPS XMM2, XMM2, XMM2

• Show nanoBench command
• Results:
  • Instructions retired: 13.0
  • Core cycles: 14.47
  • Reference cycles: 14.03
  • UOPS_EXECUTED.THREAD: 23.08
  • RETIRE_SLOTS: 23.0
  • UOPS_MITE: 0.02
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 5.5
  • UOPS_PORT_1: 5.33
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 12.22
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

• Code:

     0:	c4 e2 71 dc c2       	vaesenc xmm0,xmm1,xmm2
     5:	c4 e2 71 dc da       	vaesenc xmm3,xmm1,xmm2
     a:	c4 e2 71 dc e2       	vaesenc xmm4,xmm1,xmm2
     f:	c4 e2 71 dc ea       	vaesenc xmm5,xmm1,xmm2
    14:	c4 e2 71 dc f2       	vaesenc xmm6,xmm1,xmm2
    19:	c4 e2 71 dc fa       	vaesenc xmm7,xmm1,xmm2
    1e:	c4 62 71 dc c2       	vaesenc xmm8,xmm1,xmm2
    23:	c4 62 71 dc ca       	vaesenc xmm9,xmm1,xmm2
    28:	c4 62 71 dc d2       	vaesenc xmm10,xmm1,xmm2
    2d:	c4 62 71 dc da       	vaesenc xmm11,xmm1,xmm2
    32:	c4 62 71 dc e2       	vaesenc xmm12,xmm1,xmm2
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1;
  VXORPS XMM2, XMM2, XMM2

• Show nanoBench command
• Results:
  • Instructions retired: 11.2
  • Core cycles: 14.44
  • Reference cycles: 14.01
  • UOPS_EXECUTED.THREAD: 22.16
  • RETIRE_SLOTS: 22.1
  • UOPS_MITE: 0.22
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 5.51
  • UOPS_PORT_1: 5.35
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 11.32
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.11

With unroll_count=500 and no inner loop

• Code:

     0:	c4 e2 79 dc c0       	vaesenc xmm0,xmm0,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM0, XMM0, XMM0

• Show nanoBench command
• Results:
  • Instructions retired: 1.0
  • Core cycles: 8.0
  • Reference cycles: 7.77
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.5
  • UOPS_PORT_1: 0.5
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 1.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

• Code:

     0:	c4 e2 79 dc c0       	vaesenc xmm0,xmm0,xmm0
     5:	90                   	nop
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM0, XMM0, XMM0

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 8.0
  • Reference cycles: 7.77
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 3.0
  • UOPS_MITE: 3.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.51
  • UOPS_PORT_1: 0.49
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 1.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

• Code:

     0:	c4 e2 79 dc c0       	vaesenc xmm0,xmm0,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM0, XMM0, XMM0

• Show nanoBench command
• Results:
  • Instructions retired: 1.2
  • Core cycles: 8.0
  • Reference cycles: 7.76
  • UOPS_EXECUTED.THREAD: 2.1
  • RETIRE_SLOTS: 2.1
  • UOPS_MITE: 0.01
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.52
  • UOPS_PORT_1: 0.48
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 1.1
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

• Code:

     0:	c4 e2 79 dc c0       	vaesenc xmm0,xmm0,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM0, XMM0, XMM0

• Show nanoBench command
• Results:
  • Instructions retired: 1.02
  • Core cycles: 8.0
  • Reference cycles: 7.76
  • UOPS_EXECUTED.THREAD: 2.01
  • RETIRE_SLOTS: 2.01
  • UOPS_MITE: 0.02
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.51
  • UOPS_PORT_1: 0.49
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 1.01
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With unroll_count=200 and no inner loop

• Code:

     0:	c4 e2 79 dc c0       	vaesenc xmm0,xmm0,xmm0
     5:	c4 e2 71 dc c9       	vaesenc xmm1,xmm1,xmm1
     a:	c4 e2 69 dc d2       	vaesenc xmm2,xmm2,xmm2
     f:	c4 e2 61 dc db       	vaesenc xmm3,xmm3,xmm3
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM0, XMM0, XMM0;
  VXORPS XMM1, XMM1, XMM1;
  VXORPS XMM2, XMM2, XMM2;
  VXORPS XMM3, XMM3, XMM3

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 8.0
  • Reference cycles: 7.84
  • UOPS_EXECUTED.THREAD: 8.0
  • RETIRE_SLOTS: 8.0
  • UOPS_MITE: 8.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.01
  • UOPS_PORT_1: 1.99
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 4.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

• Code:

     0:	c4 e2 79 dc c0       	vaesenc xmm0,xmm0,xmm0
     5:	c4 e2 71 dc c9       	vaesenc xmm1,xmm1,xmm1
     a:	c4 e2 69 dc d2       	vaesenc xmm2,xmm2,xmm2
     f:	c4 e2 61 dc db       	vaesenc xmm3,xmm3,xmm3
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM0, XMM0, XMM0;
  VXORPS XMM1, XMM1, XMM1;
  VXORPS XMM2, XMM2, XMM2;
  VXORPS XMM3, XMM3, XMM3

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 8.01
  • Reference cycles: 7.76
  • UOPS_EXECUTED.THREAD: 8.5
  • RETIRE_SLOTS: 8.5
  • UOPS_MITE: 0.01
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.07
  • UOPS_PORT_1: 1.93
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 4.5
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

• Code:

     0:	c4 e2 79 dc c0       	vaesenc xmm0,xmm0,xmm0
     5:	c4 e2 71 dc c9       	vaesenc xmm1,xmm1,xmm1
     a:	c4 e2 69 dc d2       	vaesenc xmm2,xmm2,xmm2
     f:	c4 e2 61 dc db       	vaesenc xmm3,xmm3,xmm3
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM0, XMM0, XMM0;
  VXORPS XMM1, XMM1, XMM1;
  VXORPS XMM2, XMM2, XMM2;
  VXORPS XMM3, XMM3, XMM3

• Show nanoBench command
• Results:
  • Instructions retired: 4.1
  • Core cycles: 8.01
  • Reference cycles: 7.77
  • UOPS_EXECUTED.THREAD: 8.05
  • RETIRE_SLOTS: 8.05
  • UOPS_MITE: 0.08
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.05
  • UOPS_PORT_1: 1.95
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 4.05
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.04

With unroll_count=100 and no inner loop

• Code:

     0:	c4 e2 79 dc c0       	vaesenc xmm0,xmm0,xmm0
     5:	c4 e2 71 dc c9       	vaesenc xmm1,xmm1,xmm1
     a:	c4 e2 69 dc d2       	vaesenc xmm2,xmm2,xmm2
     f:	c4 e2 61 dc db       	vaesenc xmm3,xmm3,xmm3
    14:	c4 e2 59 dc e4       	vaesenc xmm4,xmm4,xmm4
    19:	c4 e2 51 dc ed       	vaesenc xmm5,xmm5,xmm5
    1e:	c4 e2 49 dc f6       	vaesenc xmm6,xmm6,xmm6
    23:	c4 e2 41 dc ff       	vaesenc xmm7,xmm7,xmm7
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM0, XMM0, XMM0;
  VXORPS XMM1, XMM1, XMM1;
  VXORPS XMM2, XMM2, XMM2;
  VXORPS XMM3, XMM3, XMM3;
  VXORPS XMM4, XMM4, XMM4;
  VXORPS XMM5, XMM5, XMM5;
  VXORPS XMM6, XMM6, XMM6;
  VXORPS XMM7, XMM7, XMM7

• Show nanoBench command
• Results:
  • Instructions retired: 8.0
  • Core cycles: 8.07
  • Reference cycles: 7.89
  • UOPS_EXECUTED.THREAD: 16.0
  • RETIRE_SLOTS: 16.0
  • UOPS_MITE: 16.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 4.0
  • UOPS_PORT_1: 4.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 8.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	c4 e2 79 dc c0       	vaesenc xmm0,xmm0,xmm0
     5:	c4 e2 71 dc c9       	vaesenc xmm1,xmm1,xmm1
     a:	c4 e2 69 dc d2       	vaesenc xmm2,xmm2,xmm2
     f:	c4 e2 61 dc db       	vaesenc xmm3,xmm3,xmm3
    14:	c4 e2 59 dc e4       	vaesenc xmm4,xmm4,xmm4
    19:	c4 e2 51 dc ed       	vaesenc xmm5,xmm5,xmm5
    1e:	c4 e2 49 dc f6       	vaesenc xmm6,xmm6,xmm6
    23:	c4 e2 41 dc ff       	vaesenc xmm7,xmm7,xmm7
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM0, XMM0, XMM0;
  VXORPS XMM1, XMM1, XMM1;
  VXORPS XMM2, XMM2, XMM2;
  VXORPS XMM3, XMM3, XMM3;
  VXORPS XMM4, XMM4, XMM4;
  VXORPS XMM5, XMM5, XMM5;
  VXORPS XMM6, XMM6, XMM6;
  VXORPS XMM7, XMM7, XMM7

• Show nanoBench command
• Results:
  • Instructions retired: 10.0
  • Core cycles: 10.12
  • Reference cycles: 9.82
  • UOPS_EXECUTED.THREAD: 17.08
  • RETIRE_SLOTS: 17.0
  • UOPS_MITE: 0.02
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 4.0
  • UOPS_PORT_1: 3.94
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 9.12
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

• Code:

     0:	c4 e2 79 dc c0       	vaesenc xmm0,xmm0,xmm0
     5:	c4 e2 71 dc c9       	vaesenc xmm1,xmm1,xmm1
     a:	c4 e2 69 dc d2       	vaesenc xmm2,xmm2,xmm2
     f:	c4 e2 61 dc db       	vaesenc xmm3,xmm3,xmm3
    14:	c4 e2 59 dc e4       	vaesenc xmm4,xmm4,xmm4
    19:	c4 e2 51 dc ed       	vaesenc xmm5,xmm5,xmm5
    1e:	c4 e2 49 dc f6       	vaesenc xmm6,xmm6,xmm6
    23:	c4 e2 41 dc ff       	vaesenc xmm7,xmm7,xmm7
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM0, XMM0, XMM0;
  VXORPS XMM1, XMM1, XMM1;
  VXORPS XMM2, XMM2, XMM2;
  VXORPS XMM3, XMM3, XMM3;
  VXORPS XMM4, XMM4, XMM4;
  VXORPS XMM5, XMM5, XMM5;
  VXORPS XMM6, XMM6, XMM6;
  VXORPS XMM7, XMM7, XMM7

• Show nanoBench command
• Results:
  • Instructions retired: 8.2
  • Core cycles: 9.12
  • Reference cycles: 8.84
  • UOPS_EXECUTED.THREAD: 16.21
  • RETIRE_SLOTS: 16.1
  • UOPS_MITE: 0.17
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 4.08
  • UOPS_PORT_1: 3.92
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 8.2
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.08

With unroll_count=100 and no inner loop

• Code:

     0:	c4 e2 79 dc c0       	vaesenc xmm0,xmm0,xmm0
     5:	c4 e2 71 dc c9       	vaesenc xmm1,xmm1,xmm1
     a:	c4 e2 69 dc d2       	vaesenc xmm2,xmm2,xmm2
     f:	c4 e2 61 dc db       	vaesenc xmm3,xmm3,xmm3
    14:	c4 e2 59 dc e4       	vaesenc xmm4,xmm4,xmm4
    19:	c4 e2 51 dc ed       	vaesenc xmm5,xmm5,xmm5
    1e:	c4 e2 49 dc f6       	vaesenc xmm6,xmm6,xmm6
    23:	c4 e2 41 dc ff       	vaesenc xmm7,xmm7,xmm7
    28:	c4 42 39 dc c0       	vaesenc xmm8,xmm8,xmm8
    2d:	c4 42 31 dc c9       	vaesenc xmm9,xmm9,xmm9
    32:	c4 42 29 dc d2       	vaesenc xmm10,xmm10,xmm10
    37:	c4 42 21 dc db       	vaesenc xmm11,xmm11,xmm11
    3c:	c4 42 19 dc e4       	vaesenc xmm12,xmm12,xmm12
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM0, XMM0, XMM0;
  VXORPS XMM1, XMM1, XMM1;
  VXORPS XMM2, XMM2, XMM2;
  VXORPS XMM3, XMM3, XMM3;
  VXORPS XMM4, XMM4, XMM4;
  VXORPS XMM5, XMM5, XMM5;
  VXORPS XMM6, XMM6, XMM6;
  VXORPS XMM7, XMM7, XMM7;
  VXORPS XMM8, XMM8, XMM8;
  VXORPS XMM9, XMM9, XMM9;
  VXORPS XMM10, XMM10, XMM10;
  VXORPS XMM11, XMM11, XMM11;
  VXORPS XMM12, XMM12, XMM12

• Show nanoBench command
• Results:
  • Instructions retired: 13.0
  • Core cycles: 15.17
  • Reference cycles: 14.72
  • UOPS_EXECUTED.THREAD: 26.0
  • RETIRE_SLOTS: 26.0
  • UOPS_MITE: 26.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 6.55
  • UOPS_PORT_1: 6.37
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 13.08
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 13.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	c4 e2 79 dc c0       	vaesenc xmm0,xmm0,xmm0
     5:	c4 e2 71 dc c9       	vaesenc xmm1,xmm1,xmm1
     a:	c4 e2 69 dc d2       	vaesenc xmm2,xmm2,xmm2
     f:	c4 e2 61 dc db       	vaesenc xmm3,xmm3,xmm3
    14:	c4 e2 59 dc e4       	vaesenc xmm4,xmm4,xmm4
    19:	c4 e2 51 dc ed       	vaesenc xmm5,xmm5,xmm5
    1e:	c4 e2 49 dc f6       	vaesenc xmm6,xmm6,xmm6
    23:	c4 e2 41 dc ff       	vaesenc xmm7,xmm7,xmm7
    28:	c4 42 39 dc c0       	vaesenc xmm8,xmm8,xmm8
    2d:	c4 42 31 dc c9       	vaesenc xmm9,xmm9,xmm9
    32:	c4 42 29 dc d2       	vaesenc xmm10,xmm10,xmm10
    37:	c4 42 21 dc db       	vaesenc xmm11,xmm11,xmm11
    3c:	c4 42 19 dc e4       	vaesenc xmm12,xmm12,xmm12
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM0, XMM0, XMM0;
  VXORPS XMM1, XMM1, XMM1;
  VXORPS XMM2, XMM2, XMM2;
  VXORPS XMM3, XMM3, XMM3;
  VXORPS XMM4, XMM4, XMM4;
  VXORPS XMM5, XMM5, XMM5;
  VXORPS XMM6, XMM6, XMM6;
  VXORPS XMM7, XMM7, XMM7;
  VXORPS XMM8, XMM8, XMM8;
  VXORPS XMM9, XMM9, XMM9;
  VXORPS XMM10, XMM10, XMM10;
  VXORPS XMM11, XMM11, XMM11;
  VXORPS XMM12, XMM12, XMM12

• Show nanoBench command
• Results:
  • Instructions retired: 15.0
  • Core cycles: 16.71
  • Reference cycles: 16.21
  • UOPS_EXECUTED.THREAD: 27.02
  • RETIRE_SLOTS: 27.0
  • UOPS_MITE: 0.03
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 6.58
  • UOPS_PORT_1: 6.25
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 14.19
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

• Code:

     0:	c4 e2 79 dc c0       	vaesenc xmm0,xmm0,xmm0
     5:	c4 e2 71 dc c9       	vaesenc xmm1,xmm1,xmm1
     a:	c4 e2 69 dc d2       	vaesenc xmm2,xmm2,xmm2
     f:	c4 e2 61 dc db       	vaesenc xmm3,xmm3,xmm3
    14:	c4 e2 59 dc e4       	vaesenc xmm4,xmm4,xmm4
    19:	c4 e2 51 dc ed       	vaesenc xmm5,xmm5,xmm5
    1e:	c4 e2 49 dc f6       	vaesenc xmm6,xmm6,xmm6
    23:	c4 e2 41 dc ff       	vaesenc xmm7,xmm7,xmm7
    28:	c4 42 39 dc c0       	vaesenc xmm8,xmm8,xmm8
    2d:	c4 42 31 dc c9       	vaesenc xmm9,xmm9,xmm9
    32:	c4 42 29 dc d2       	vaesenc xmm10,xmm10,xmm10
    37:	c4 42 21 dc db       	vaesenc xmm11,xmm11,xmm11
    3c:	c4 42 19 dc e4       	vaesenc xmm12,xmm12,xmm12
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM0, XMM0, XMM0;
  VXORPS XMM1, XMM1, XMM1;
  VXORPS XMM2, XMM2, XMM2;
  VXORPS XMM3, XMM3, XMM3;
  VXORPS XMM4, XMM4, XMM4;
  VXORPS XMM5, XMM5, XMM5;
  VXORPS XMM6, XMM6, XMM6;
  VXORPS XMM7, XMM7, XMM7;
  VXORPS XMM8, XMM8, XMM8;
  VXORPS XMM9, XMM9, XMM9;
  VXORPS XMM10, XMM10, XMM10;
  VXORPS XMM11, XMM11, XMM11;
  VXORPS XMM12, XMM12, XMM12

• Show nanoBench command
• Results:
  • Instructions retired: 13.2
  • Core cycles: 15.89
  • Reference cycles: 15.41
  • UOPS_EXECUTED.THREAD: 26.2
  • RETIRE_SLOTS: 26.1
  • UOPS_MITE: 0.26
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 6.54
  • UOPS_PORT_1: 6.34
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 13.32
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.13