VADDPD (XMM, XMM, M128)

With unroll_count=500 and no inner loop

Code:

   0:	c4 c1 71 58 06       	vaddpd xmm0,xmm1,XMMWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.01
- Reference cycles: 0.98
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	c4 c1 71 58 06       	vaddpd xmm0,xmm1,XMMWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.02
- Reference cycles: 0.99
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.1
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	c4 c1 71 58 06       	vaddpd xmm0,xmm1,XMMWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.02
- Reference cycles: 0.98
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.01
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	c4 c1 71 58 06       	vaddpd xmm0,xmm1,XMMWORD PTR [r14]
   5:	c4 c1 71 58 56 10    	vaddpd xmm2,xmm1,XMMWORD PTR [r14+0x10]
   b:	c4 c1 71 58 5e 20    	vaddpd xmm3,xmm1,XMMWORD PTR [r14+0x20]
  11:	c4 c1 71 58 66 30    	vaddpd xmm4,xmm1,XMMWORD PTR [r14+0x30]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.06
- Reference cycles: 4.0
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	c4 c1 71 58 06       	vaddpd xmm0,xmm1,XMMWORD PTR [r14]
   5:	c4 c1 71 58 56 10    	vaddpd xmm2,xmm1,XMMWORD PTR [r14+0x10]
   b:	c4 c1 71 58 5e 20    	vaddpd xmm3,xmm1,XMMWORD PTR [r14+0x20]
  11:	c4 c1 71 58 66 30    	vaddpd xmm4,xmm1,XMMWORD PTR [r14+0x30]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.07
- Reference cycles: 3.95
- UOPS_EXECUTED.THREAD: 8.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	c4 c1 71 58 06       	vaddpd xmm0,xmm1,XMMWORD PTR [r14]
   5:	c4 c1 71 58 56 10    	vaddpd xmm2,xmm1,XMMWORD PTR [r14+0x10]
   b:	c4 c1 71 58 5e 20    	vaddpd xmm3,xmm1,XMMWORD PTR [r14+0x20]
  11:	c4 c1 71 58 66 30    	vaddpd xmm4,xmm1,XMMWORD PTR [r14+0x30]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.06
- Reference cycles: 3.94
- UOPS_EXECUTED.THREAD: 8.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.05
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 c1 71 58 06       	vaddpd xmm0,xmm1,XMMWORD PTR [r14]
   5:	c4 c1 71 58 56 10    	vaddpd xmm2,xmm1,XMMWORD PTR [r14+0x10]
   b:	c4 c1 71 58 5e 20    	vaddpd xmm3,xmm1,XMMWORD PTR [r14+0x20]
  11:	c4 c1 71 58 66 30    	vaddpd xmm4,xmm1,XMMWORD PTR [r14+0x30]
  17:	c4 c1 71 58 6e 40    	vaddpd xmm5,xmm1,XMMWORD PTR [r14+0x40]
  1d:	c4 c1 71 58 76 50    	vaddpd xmm6,xmm1,XMMWORD PTR [r14+0x50]
  23:	c4 c1 71 58 7e 60    	vaddpd xmm7,xmm1,XMMWORD PTR [r14+0x60]
  29:	c4 41 71 58 46 70    	vaddpd xmm8,xmm1,XMMWORD PTR [r14+0x70]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX;
MOV [R14+104], RAX;
MOV [R14+112], RAX;
MOV [R14+120], RAX

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.12
- Reference cycles: 7.95
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 c1 71 58 06       	vaddpd xmm0,xmm1,XMMWORD PTR [r14]
   5:	c4 c1 71 58 56 10    	vaddpd xmm2,xmm1,XMMWORD PTR [r14+0x10]
   b:	c4 c1 71 58 5e 20    	vaddpd xmm3,xmm1,XMMWORD PTR [r14+0x20]
  11:	c4 c1 71 58 66 30    	vaddpd xmm4,xmm1,XMMWORD PTR [r14+0x30]
  17:	c4 c1 71 58 6e 40    	vaddpd xmm5,xmm1,XMMWORD PTR [r14+0x40]
  1d:	c4 c1 71 58 76 50    	vaddpd xmm6,xmm1,XMMWORD PTR [r14+0x50]
  23:	c4 c1 71 58 7e 60    	vaddpd xmm7,xmm1,XMMWORD PTR [r14+0x60]
  29:	c4 41 71 58 46 70    	vaddpd xmm8,xmm1,XMMWORD PTR [r14+0x70]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX;
MOV [R14+104], RAX;
MOV [R14+112], RAX;
MOV [R14+120], RAX

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.13
- Reference cycles: 7.89
- UOPS_EXECUTED.THREAD: 17.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	c4 c1 71 58 06       	vaddpd xmm0,xmm1,XMMWORD PTR [r14]
   5:	c4 c1 71 58 56 10    	vaddpd xmm2,xmm1,XMMWORD PTR [r14+0x10]
   b:	c4 c1 71 58 5e 20    	vaddpd xmm3,xmm1,XMMWORD PTR [r14+0x20]
  11:	c4 c1 71 58 66 30    	vaddpd xmm4,xmm1,XMMWORD PTR [r14+0x30]
  17:	c4 c1 71 58 6e 40    	vaddpd xmm5,xmm1,XMMWORD PTR [r14+0x40]
  1d:	c4 c1 71 58 76 50    	vaddpd xmm6,xmm1,XMMWORD PTR [r14+0x50]
  23:	c4 c1 71 58 7e 60    	vaddpd xmm7,xmm1,XMMWORD PTR [r14+0x60]
  29:	c4 41 71 58 46 70    	vaddpd xmm8,xmm1,XMMWORD PTR [r14+0x70]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX;
MOV [R14+104], RAX;
MOV [R14+112], RAX;
MOV [R14+120], RAX

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.13
- Reference cycles: 7.89
- UOPS_EXECUTED.THREAD: 16.11
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.1
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 12 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 c1 71 58 06       	vaddpd xmm0,xmm1,XMMWORD PTR [r14]
   5:	c4 c1 71 58 56 10    	vaddpd xmm2,xmm1,XMMWORD PTR [r14+0x10]
   b:	c4 c1 71 58 5e 20    	vaddpd xmm3,xmm1,XMMWORD PTR [r14+0x20]
  11:	c4 c1 71 58 66 30    	vaddpd xmm4,xmm1,XMMWORD PTR [r14+0x30]
  17:	c4 c1 71 58 6e 40    	vaddpd xmm5,xmm1,XMMWORD PTR [r14+0x40]
  1d:	c4 c1 71 58 76 50    	vaddpd xmm6,xmm1,XMMWORD PTR [r14+0x50]
  23:	c4 c1 71 58 7e 60    	vaddpd xmm7,xmm1,XMMWORD PTR [r14+0x60]
  29:	c4 41 71 58 46 70    	vaddpd xmm8,xmm1,XMMWORD PTR [r14+0x70]
  2f:	c4 41 71 58 8e 80 00 	vaddpd xmm9,xmm1,XMMWORD PTR [r14+0x80]
  36:	00 00 
  38:	c4 41 71 58 96 90 00 	vaddpd xmm10,xmm1,XMMWORD PTR [r14+0x90]
  3f:	00 00 
  41:	c4 41 71 58 9e a0 00 	vaddpd xmm11,xmm1,XMMWORD PTR [r14+0xa0]
  48:	00 00 
  4a:	c4 41 71 58 a6 b0 00 	vaddpd xmm12,xmm1,XMMWORD PTR [r14+0xb0]
  51:	00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX;
MOV [R14+104], RAX;
MOV [R14+112], RAX;
MOV [R14+120], RAX;
MOV [R14+128], RAX;
MOV [R14+136], RAX;
MOV [R14+144], RAX;
MOV [R14+152], RAX;
MOV [R14+160], RAX;
MOV [R14+168], RAX;
MOV [R14+176], RAX;
MOV [R14+184], RAX

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 12.17
- Reference cycles: 11.89
- UOPS_EXECUTED.THREAD: 24.0
- RETIRE_SLOTS: 12.0
- UOPS_MITE: 12.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 12.0
- UOPS_PORT_2: 6.0
- UOPS_PORT_3: 6.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 3.02

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 c1 71 58 06       	vaddpd xmm0,xmm1,XMMWORD PTR [r14]
   5:	c4 c1 71 58 56 10    	vaddpd xmm2,xmm1,XMMWORD PTR [r14+0x10]
   b:	c4 c1 71 58 5e 20    	vaddpd xmm3,xmm1,XMMWORD PTR [r14+0x20]
  11:	c4 c1 71 58 66 30    	vaddpd xmm4,xmm1,XMMWORD PTR [r14+0x30]
  17:	c4 c1 71 58 6e 40    	vaddpd xmm5,xmm1,XMMWORD PTR [r14+0x40]
  1d:	c4 c1 71 58 76 50    	vaddpd xmm6,xmm1,XMMWORD PTR [r14+0x50]
  23:	c4 c1 71 58 7e 60    	vaddpd xmm7,xmm1,XMMWORD PTR [r14+0x60]
  29:	c4 41 71 58 46 70    	vaddpd xmm8,xmm1,XMMWORD PTR [r14+0x70]
  2f:	c4 41 71 58 8e 80 00 	vaddpd xmm9,xmm1,XMMWORD PTR [r14+0x80]
  36:	00 00 
  38:	c4 41 71 58 96 90 00 	vaddpd xmm10,xmm1,XMMWORD PTR [r14+0x90]
  3f:	00 00 
  41:	c4 41 71 58 9e a0 00 	vaddpd xmm11,xmm1,XMMWORD PTR [r14+0xa0]
  48:	00 00 
  4a:	c4 41 71 58 a6 b0 00 	vaddpd xmm12,xmm1,XMMWORD PTR [r14+0xb0]
  51:	00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX;
MOV [R14+104], RAX;
MOV [R14+112], RAX;
MOV [R14+120], RAX;
MOV [R14+128], RAX;
MOV [R14+136], RAX;
MOV [R14+144], RAX;
MOV [R14+152], RAX;
MOV [R14+160], RAX;
MOV [R14+168], RAX;
MOV [R14+176], RAX;
MOV [R14+184], RAX

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 12.19
- Reference cycles: 11.82
- UOPS_EXECUTED.THREAD: 25.01
- RETIRE_SLOTS: 13.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 12.0
- UOPS_PORT_2: 6.0
- UOPS_PORT_3: 6.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	c4 c1 71 58 06       	vaddpd xmm0,xmm1,XMMWORD PTR [r14]
   5:	c4 c1 71 58 56 10    	vaddpd xmm2,xmm1,XMMWORD PTR [r14+0x10]
   b:	c4 c1 71 58 5e 20    	vaddpd xmm3,xmm1,XMMWORD PTR [r14+0x20]
  11:	c4 c1 71 58 66 30    	vaddpd xmm4,xmm1,XMMWORD PTR [r14+0x30]
  17:	c4 c1 71 58 6e 40    	vaddpd xmm5,xmm1,XMMWORD PTR [r14+0x40]
  1d:	c4 c1 71 58 76 50    	vaddpd xmm6,xmm1,XMMWORD PTR [r14+0x50]
  23:	c4 c1 71 58 7e 60    	vaddpd xmm7,xmm1,XMMWORD PTR [r14+0x60]
  29:	c4 41 71 58 46 70    	vaddpd xmm8,xmm1,XMMWORD PTR [r14+0x70]
  2f:	c4 41 71 58 8e 80 00 	vaddpd xmm9,xmm1,XMMWORD PTR [r14+0x80]
  36:	00 00 
  38:	c4 41 71 58 96 90 00 	vaddpd xmm10,xmm1,XMMWORD PTR [r14+0x90]
  3f:	00 00 
  41:	c4 41 71 58 9e a0 00 	vaddpd xmm11,xmm1,XMMWORD PTR [r14+0xa0]
  48:	00 00 
  4a:	c4 41 71 58 a6 b0 00 	vaddpd xmm12,xmm1,XMMWORD PTR [r14+0xb0]
  51:	00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX;
MOV [R14+104], RAX;
MOV [R14+112], RAX;
MOV [R14+120], RAX;
MOV [R14+128], RAX;
MOV [R14+136], RAX;
MOV [R14+144], RAX;
MOV [R14+152], RAX;
MOV [R14+160], RAX;
MOV [R14+168], RAX;
MOV [R14+176], RAX;
MOV [R14+184], RAX

Show nanoBench command
Results:
- Instructions retired: 12.2
- Core cycles: 12.19
- Reference cycles: 11.82
- UOPS_EXECUTED.THREAD: 24.11
- RETIRE_SLOTS: 12.1
- UOPS_MITE: 0.12
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 12.0
- UOPS_PORT_2: 6.0
- UOPS_PORT_3: 6.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.1
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	c4 81 71 58 04 2e    	vaddpd xmm0,xmm1,XMMWORD PTR [r14+r13*1]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.01
- Reference cycles: 1.15
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	c4 81 71 58 04 2e    	vaddpd xmm0,xmm1,XMMWORD PTR [r14+r13*1]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.02
- Reference cycles: 1.12
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.1
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	c4 81 71 58 04 2e    	vaddpd xmm0,xmm1,XMMWORD PTR [r14+r13*1]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.02
- Reference cycles: 1.12
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.01
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	c4 81 71 58 04 2e    	vaddpd xmm0,xmm1,XMMWORD PTR [r14+r13*1]
   6:	c4 81 71 58 54 2e 10 	vaddpd xmm2,xmm1,XMMWORD PTR [r14+r13*1+0x10]
   d:	c4 81 71 58 5c 2e 20 	vaddpd xmm3,xmm1,XMMWORD PTR [r14+r13*1+0x20]
  14:	c4 81 71 58 64 2e 30 	vaddpd xmm4,xmm1,XMMWORD PTR [r14+r13*1+0x30]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
XOR R13, R13;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.06
- Reference cycles: 4.45
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	c4 81 71 58 04 2e    	vaddpd xmm0,xmm1,XMMWORD PTR [r14+r13*1]
   6:	c4 81 71 58 54 2e 10 	vaddpd xmm2,xmm1,XMMWORD PTR [r14+r13*1+0x10]
   d:	c4 81 71 58 5c 2e 20 	vaddpd xmm3,xmm1,XMMWORD PTR [r14+r13*1+0x20]
  14:	c4 81 71 58 64 2e 30 	vaddpd xmm4,xmm1,XMMWORD PTR [r14+r13*1+0x30]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
XOR R13, R13;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.07
- Reference cycles: 4.49
- UOPS_EXECUTED.THREAD: 8.5
- RETIRE_SLOTS: 8.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	c4 81 71 58 04 2e    	vaddpd xmm0,xmm1,XMMWORD PTR [r14+r13*1]
   6:	c4 81 71 58 54 2e 10 	vaddpd xmm2,xmm1,XMMWORD PTR [r14+r13*1+0x10]
   d:	c4 81 71 58 5c 2e 20 	vaddpd xmm3,xmm1,XMMWORD PTR [r14+r13*1+0x20]
  14:	c4 81 71 58 64 2e 30 	vaddpd xmm4,xmm1,XMMWORD PTR [r14+r13*1+0x30]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
XOR R13, R13;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.06
- Reference cycles: 4.48
- UOPS_EXECUTED.THREAD: 8.05
- RETIRE_SLOTS: 8.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.05
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 81 71 58 04 2e    	vaddpd xmm0,xmm1,XMMWORD PTR [r14+r13*1]
   6:	c4 81 71 58 54 2e 10 	vaddpd xmm2,xmm1,XMMWORD PTR [r14+r13*1+0x10]
   d:	c4 81 71 58 5c 2e 20 	vaddpd xmm3,xmm1,XMMWORD PTR [r14+r13*1+0x20]
  14:	c4 81 71 58 64 2e 30 	vaddpd xmm4,xmm1,XMMWORD PTR [r14+r13*1+0x30]
  1b:	c4 81 71 58 6c 2e 40 	vaddpd xmm5,xmm1,XMMWORD PTR [r14+r13*1+0x40]
  22:	c4 81 71 58 74 2e 50 	vaddpd xmm6,xmm1,XMMWORD PTR [r14+r13*1+0x50]
  29:	c4 81 71 58 7c 2e 60 	vaddpd xmm7,xmm1,XMMWORD PTR [r14+r13*1+0x60]
  30:	c4 01 71 58 44 2e 70 	vaddpd xmm8,xmm1,XMMWORD PTR [r14+r13*1+0x70]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
XOR R13, R13;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX;
MOV [R14+104], RAX;
MOV [R14+112], RAX;
MOV [R14+120], RAX

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.12
- Reference cycles: 8.96
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 81 71 58 04 2e    	vaddpd xmm0,xmm1,XMMWORD PTR [r14+r13*1]
   6:	c4 81 71 58 54 2e 10 	vaddpd xmm2,xmm1,XMMWORD PTR [r14+r13*1+0x10]
   d:	c4 81 71 58 5c 2e 20 	vaddpd xmm3,xmm1,XMMWORD PTR [r14+r13*1+0x20]
  14:	c4 81 71 58 64 2e 30 	vaddpd xmm4,xmm1,XMMWORD PTR [r14+r13*1+0x30]
  1b:	c4 81 71 58 6c 2e 40 	vaddpd xmm5,xmm1,XMMWORD PTR [r14+r13*1+0x40]
  22:	c4 81 71 58 74 2e 50 	vaddpd xmm6,xmm1,XMMWORD PTR [r14+r13*1+0x50]
  29:	c4 81 71 58 7c 2e 60 	vaddpd xmm7,xmm1,XMMWORD PTR [r14+r13*1+0x60]
  30:	c4 01 71 58 44 2e 70 	vaddpd xmm8,xmm1,XMMWORD PTR [r14+r13*1+0x70]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
XOR R13, R13;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX;
MOV [R14+104], RAX;
MOV [R14+112], RAX;
MOV [R14+120], RAX

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.13
- Reference cycles: 8.96
- UOPS_EXECUTED.THREAD: 17.01
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	c4 81 71 58 04 2e    	vaddpd xmm0,xmm1,XMMWORD PTR [r14+r13*1]
   6:	c4 81 71 58 54 2e 10 	vaddpd xmm2,xmm1,XMMWORD PTR [r14+r13*1+0x10]
   d:	c4 81 71 58 5c 2e 20 	vaddpd xmm3,xmm1,XMMWORD PTR [r14+r13*1+0x20]
  14:	c4 81 71 58 64 2e 30 	vaddpd xmm4,xmm1,XMMWORD PTR [r14+r13*1+0x30]
  1b:	c4 81 71 58 6c 2e 40 	vaddpd xmm5,xmm1,XMMWORD PTR [r14+r13*1+0x40]
  22:	c4 81 71 58 74 2e 50 	vaddpd xmm6,xmm1,XMMWORD PTR [r14+r13*1+0x50]
  29:	c4 81 71 58 7c 2e 60 	vaddpd xmm7,xmm1,XMMWORD PTR [r14+r13*1+0x60]
  30:	c4 01 71 58 44 2e 70 	vaddpd xmm8,xmm1,XMMWORD PTR [r14+r13*1+0x70]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
XOR R13, R13;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX;
MOV [R14+104], RAX;
MOV [R14+112], RAX;
MOV [R14+120], RAX

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.13
- Reference cycles: 8.97
- UOPS_EXECUTED.THREAD: 16.11
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.1
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 12 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 81 71 58 04 2e    	vaddpd xmm0,xmm1,XMMWORD PTR [r14+r13*1]
   6:	c4 81 71 58 54 2e 10 	vaddpd xmm2,xmm1,XMMWORD PTR [r14+r13*1+0x10]
   d:	c4 81 71 58 5c 2e 20 	vaddpd xmm3,xmm1,XMMWORD PTR [r14+r13*1+0x20]
  14:	c4 81 71 58 64 2e 30 	vaddpd xmm4,xmm1,XMMWORD PTR [r14+r13*1+0x30]
  1b:	c4 81 71 58 6c 2e 40 	vaddpd xmm5,xmm1,XMMWORD PTR [r14+r13*1+0x40]
  22:	c4 81 71 58 74 2e 50 	vaddpd xmm6,xmm1,XMMWORD PTR [r14+r13*1+0x50]
  29:	c4 81 71 58 7c 2e 60 	vaddpd xmm7,xmm1,XMMWORD PTR [r14+r13*1+0x60]
  30:	c4 01 71 58 44 2e 70 	vaddpd xmm8,xmm1,XMMWORD PTR [r14+r13*1+0x70]
  37:	c4 01 71 58 8c 2e 80 	vaddpd xmm9,xmm1,XMMWORD PTR [r14+r13*1+0x80]
  3e:	00 00 00 
  41:	c4 01 71 58 94 2e 90 	vaddpd xmm10,xmm1,XMMWORD PTR [r14+r13*1+0x90]
  48:	00 00 00 
  4b:	c4 01 71 58 9c 2e a0 	vaddpd xmm11,xmm1,XMMWORD PTR [r14+r13*1+0xa0]
  52:	00 00 00 
  55:	c4 01 71 58 a4 2e b0 	vaddpd xmm12,xmm1,XMMWORD PTR [r14+r13*1+0xb0]
  5c:	00 00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
XOR R13, R13;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX;
MOV [R14+104], RAX;
MOV [R14+112], RAX;
MOV [R14+120], RAX;
MOV [R14+128], RAX;
MOV [R14+136], RAX;
MOV [R14+144], RAX;
MOV [R14+152], RAX;
MOV [R14+160], RAX;
MOV [R14+168], RAX;
MOV [R14+176], RAX;
MOV [R14+184], RAX

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 12.17
- Reference cycles: 13.39
- UOPS_EXECUTED.THREAD: 24.0
- RETIRE_SLOTS: 24.0
- UOPS_MITE: 12.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 12.0
- UOPS_PORT_2: 6.0
- UOPS_PORT_3: 6.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 3.05

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 81 71 58 04 2e    	vaddpd xmm0,xmm1,XMMWORD PTR [r14+r13*1]
   6:	c4 81 71 58 54 2e 10 	vaddpd xmm2,xmm1,XMMWORD PTR [r14+r13*1+0x10]
   d:	c4 81 71 58 5c 2e 20 	vaddpd xmm3,xmm1,XMMWORD PTR [r14+r13*1+0x20]
  14:	c4 81 71 58 64 2e 30 	vaddpd xmm4,xmm1,XMMWORD PTR [r14+r13*1+0x30]
  1b:	c4 81 71 58 6c 2e 40 	vaddpd xmm5,xmm1,XMMWORD PTR [r14+r13*1+0x40]
  22:	c4 81 71 58 74 2e 50 	vaddpd xmm6,xmm1,XMMWORD PTR [r14+r13*1+0x50]
  29:	c4 81 71 58 7c 2e 60 	vaddpd xmm7,xmm1,XMMWORD PTR [r14+r13*1+0x60]
  30:	c4 01 71 58 44 2e 70 	vaddpd xmm8,xmm1,XMMWORD PTR [r14+r13*1+0x70]
  37:	c4 01 71 58 8c 2e 80 	vaddpd xmm9,xmm1,XMMWORD PTR [r14+r13*1+0x80]
  3e:	00 00 00 
  41:	c4 01 71 58 94 2e 90 	vaddpd xmm10,xmm1,XMMWORD PTR [r14+r13*1+0x90]
  48:	00 00 00 
  4b:	c4 01 71 58 9c 2e a0 	vaddpd xmm11,xmm1,XMMWORD PTR [r14+r13*1+0xa0]
  52:	00 00 00 
  55:	c4 01 71 58 a4 2e b0 	vaddpd xmm12,xmm1,XMMWORD PTR [r14+r13*1+0xb0]
  5c:	00 00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
XOR R13, R13;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX;
MOV [R14+104], RAX;
MOV [R14+112], RAX;
MOV [R14+120], RAX;
MOV [R14+128], RAX;
MOV [R14+136], RAX;
MOV [R14+144], RAX;
MOV [R14+152], RAX;
MOV [R14+160], RAX;
MOV [R14+168], RAX;
MOV [R14+176], RAX;
MOV [R14+184], RAX

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 12.19
- Reference cycles: 13.45
- UOPS_EXECUTED.THREAD: 25.01
- RETIRE_SLOTS: 25.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 12.0
- UOPS_PORT_2: 6.0
- UOPS_PORT_3: 6.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	c4 81 71 58 04 2e    	vaddpd xmm0,xmm1,XMMWORD PTR [r14+r13*1]
   6:	c4 81 71 58 54 2e 10 	vaddpd xmm2,xmm1,XMMWORD PTR [r14+r13*1+0x10]
   d:	c4 81 71 58 5c 2e 20 	vaddpd xmm3,xmm1,XMMWORD PTR [r14+r13*1+0x20]
  14:	c4 81 71 58 64 2e 30 	vaddpd xmm4,xmm1,XMMWORD PTR [r14+r13*1+0x30]
  1b:	c4 81 71 58 6c 2e 40 	vaddpd xmm5,xmm1,XMMWORD PTR [r14+r13*1+0x40]
  22:	c4 81 71 58 74 2e 50 	vaddpd xmm6,xmm1,XMMWORD PTR [r14+r13*1+0x50]
  29:	c4 81 71 58 7c 2e 60 	vaddpd xmm7,xmm1,XMMWORD PTR [r14+r13*1+0x60]
  30:	c4 01 71 58 44 2e 70 	vaddpd xmm8,xmm1,XMMWORD PTR [r14+r13*1+0x70]
  37:	c4 01 71 58 8c 2e 80 	vaddpd xmm9,xmm1,XMMWORD PTR [r14+r13*1+0x80]
  3e:	00 00 00 
  41:	c4 01 71 58 94 2e 90 	vaddpd xmm10,xmm1,XMMWORD PTR [r14+r13*1+0x90]
  48:	00 00 00 
  4b:	c4 01 71 58 9c 2e a0 	vaddpd xmm11,xmm1,XMMWORD PTR [r14+r13*1+0xa0]
  52:	00 00 00 
  55:	c4 01 71 58 a4 2e b0 	vaddpd xmm12,xmm1,XMMWORD PTR [r14+r13*1+0xb0]
  5c:	00 00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
XOR R13, R13;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX;
MOV [R14+104], RAX;
MOV [R14+112], RAX;
MOV [R14+120], RAX;
MOV [R14+128], RAX;
MOV [R14+136], RAX;
MOV [R14+144], RAX;
MOV [R14+152], RAX;
MOV [R14+160], RAX;
MOV [R14+168], RAX;
MOV [R14+176], RAX;
MOV [R14+184], RAX

Show nanoBench command
Results:
- Instructions retired: 12.2
- Core cycles: 12.19
- Reference cycles: 13.44
- UOPS_EXECUTED.THREAD: 24.11
- RETIRE_SLOTS: 24.1
- UOPS_MITE: 0.12
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 12.0
- UOPS_PORT_2: 6.0
- UOPS_PORT_3: 6.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.1
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

VADDPD (XMM, XMM, M128) - Throughput and Uops

With a non-indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 12 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 12 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10