RDMSR - Throughput and Uops
With unroll_count=500 and no inner loop
- Code:
0: 0f 32 rdmsr
- Init:
MOV RCX, 0xE7
- Show nanoBench command
- Results:
- Instructions retired: 1.0
- Core cycles: 107.5
- Reference cycles: 118.61
- UOPS_EXECUTED.THREAD: 81.0
- RETIRE_SLOTS: 76.0
- UOPS_MITE: 0.0
- UOPS_MS: 82.0
- UOPS_PORT_0: 20.0
- UOPS_PORT_1: 16.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 45.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0
With unroll_count=500, no inner loop, and 1 NOP
- Code:
0: 0f 32 rdmsr
2: 90 nop
- Init:
MOV RCX, 0xE7
- Show nanoBench command
- Results:
- Instructions retired: 2.0
- Core cycles: 108.62
- Reference cycles: 119.85
- UOPS_EXECUTED.THREAD: 81.0
- RETIRE_SLOTS: 77.0
- UOPS_MITE: 1.0
- UOPS_MS: 82.0
- UOPS_PORT_0: 20.0
- UOPS_PORT_1: 16.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 45.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0
With loop_count=10 and unroll_count=1
- Code:
0: 0f 32 rdmsr
- Init:
MOV RCX, 0xE7
- Show nanoBench command
- Results:
- Instructions retired: 3.0
- Core cycles: 108.63
- Reference cycles: 120.53
- UOPS_EXECUTED.THREAD: 81.9
- RETIRE_SLOTS: 77.0
- UOPS_MITE: 1.0
- UOPS_MS: 82.0
- UOPS_PORT_0: 19.9
- UOPS_PORT_1: 16.0
- UOPS_PORT_2: 0.1
- UOPS_PORT_3: 0.1
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 46.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.8
With loop_count=10 and unroll_count=1
- Code:
0: 0f 32 rdmsr
- Init:
MOV RCX, 0xE7
- Show nanoBench command
- Results:
- Instructions retired: 3.0
- Core cycles: 108.63
- Reference cycles: 120.0
- UOPS_EXECUTED.THREAD: 81.9
- RETIRE_SLOTS: 77.0
- UOPS_MITE: 1.0
- UOPS_MS: 82.0
- UOPS_PORT_0: 19.9
- UOPS_PORT_1: 16.0
- UOPS_PORT_2: 0.1
- UOPS_PORT_3: 0.1
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 46.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.8