ADD (M32, I32)

With unroll_count=500 and no inner loop

Code:

   0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 6.02
- Reference cycles: 5.37
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.32
- UOPS_PORT_1: 2.21
- UOPS_PORT_2: 1.0
- UOPS_PORT_3: 1.0
- UOPS_PORT_4: 5.94
- UOPS_PORT_5: 2.91
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
   7:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 6.5
- Reference cycles: 5.79
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 3.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.19
- UOPS_PORT_1: 1.99
- UOPS_PORT_2: 1.0
- UOPS_PORT_3: 1.0
- UOPS_PORT_4: 5.32
- UOPS_PORT_5: 2.63
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
   7:	90                   	nop
   8:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 6.24
- Reference cycles: 5.58
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.15
- UOPS_PORT_1: 1.93
- UOPS_PORT_2: 0.95
- UOPS_PORT_3: 1.05
- UOPS_PORT_4: 1.72
- UOPS_PORT_5: 3.39
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 7.41
- Reference cycles: 6.59
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.69
- UOPS_PORT_1: 2.57
- UOPS_PORT_2: 0.93
- UOPS_PORT_3: 1.07
- UOPS_PORT_4: 1.7
- UOPS_PORT_5: 2.48
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 6.0
- Reference cycles: 5.33
- UOPS_EXECUTED.THREAD: 4.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.91
- UOPS_PORT_1: 1.81
- UOPS_PORT_2: 1.0
- UOPS_PORT_3: 1.0
- UOPS_PORT_4: 5.22
- UOPS_PORT_5: 2.78
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 6.0
- Reference cycles: 5.33
- UOPS_EXECUTED.THREAD: 4.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.97
- UOPS_PORT_1: 1.86
- UOPS_PORT_2: 1.0
- UOPS_PORT_3: 1.0
- UOPS_PORT_4: 4.86
- UOPS_PORT_5: 2.7
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 6.03
- Reference cycles: 5.36
- UOPS_EXECUTED.THREAD: 4.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.2
- UOPS_PORT_1: 2.09
- UOPS_PORT_2: 1.0
- UOPS_PORT_3: 1.0
- UOPS_PORT_4: 5.72
- UOPS_PORT_5: 2.82
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 6.0
- Reference cycles: 5.33
- UOPS_EXECUTED.THREAD: 4.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.14
- UOPS_PORT_1: 2.04
- UOPS_PORT_2: 1.0
- UOPS_PORT_3: 1.0
- UOPS_PORT_4: 5.73
- UOPS_PORT_5: 2.82
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
   7:	41 81 46 04 00 00 00 	add    DWORD PTR [r14+0x4],0x1000000
   e:	01 
   f:	41 81 46 08 00 00 00 	add    DWORD PTR [r14+0x8],0x1000000
  16:	01 
  17:	41 81 46 0c 00 00 00 	add    DWORD PTR [r14+0xc],0x1000000
  1e:	01

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 6.15
- Reference cycles: 5.52
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.84
- UOPS_PORT_1: 2.68
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 5.38
- UOPS_PORT_5: 3.91
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
   7:	41 81 46 04 00 00 00 	add    DWORD PTR [r14+0x4],0x1000000
   e:	01 
   f:	41 81 46 08 00 00 00 	add    DWORD PTR [r14+0x8],0x1000000
  16:	01 
  17:	41 81 46 0c 00 00 00 	add    DWORD PTR [r14+0xc],0x1000000
  1e:	01

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 7.46
- Reference cycles: 6.63
- UOPS_EXECUTED.THREAD: 16.5
- RETIRE_SLOTS: 8.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.36
- UOPS_PORT_1: 3.11
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 4.33
- UOPS_PORT_5: 5.03
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=1000, unroll_count=2, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
   8:	40                   	rex
   9:	41 81 46 04 00 00 00 	add    DWORD PTR [r14+0x4],0x1000000
  10:	01 
  11:	40                   	rex
  12:	41 81 46 08 00 00 00 	add    DWORD PTR [r14+0x8],0x1000000
  19:	01 
  1a:	40                   	rex
  1b:	41 81 46 0c 00 00 00 	add    DWORD PTR [r14+0xc],0x1000000
  22:	01

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 6.1
- Reference cycles: 5.42
- UOPS_EXECUTED.THREAD: 16.51
- RETIRE_SLOTS: 8.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.9
- UOPS_PORT_1: 2.68
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.01
- UOPS_PORT_4: 5.25
- UOPS_PORT_5: 4.26
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
   7:	41 81 46 04 00 00 00 	add    DWORD PTR [r14+0x4],0x1000000
   e:	01 
   f:	41 81 46 08 00 00 00 	add    DWORD PTR [r14+0x8],0x1000000
  16:	01 
  17:	41 81 46 0c 00 00 00 	add    DWORD PTR [r14+0xc],0x1000000
  1e:	01

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 6.46
- Reference cycles: 5.74
- UOPS_EXECUTED.THREAD: 16.06
- RETIRE_SLOTS: 8.05
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.11
- UOPS_PORT_1: 2.9
- UOPS_PORT_2: 3.99
- UOPS_PORT_3: 4.01
- UOPS_PORT_4: 5.16
- UOPS_PORT_5: 3.99
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With loop_count=100, unroll_count=20, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
   8:	40                   	rex
   9:	41 81 46 04 00 00 00 	add    DWORD PTR [r14+0x4],0x1000000
  10:	01 
  11:	40                   	rex
  12:	41 81 46 08 00 00 00 	add    DWORD PTR [r14+0x8],0x1000000
  19:	01 
  1a:	40                   	rex
  1b:	41 81 46 0c 00 00 00 	add    DWORD PTR [r14+0xc],0x1000000
  22:	01

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 6.55
- Reference cycles: 5.82
- UOPS_EXECUTED.THREAD: 16.06
- RETIRE_SLOTS: 8.05
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.11
- UOPS_PORT_1: 2.9
- UOPS_PORT_2: 3.99
- UOPS_PORT_3: 4.01
- UOPS_PORT_4: 5.16
- UOPS_PORT_5: 3.99
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
   7:	41 81 46 04 00 00 00 	add    DWORD PTR [r14+0x4],0x1000000
   e:	01 
   f:	41 81 46 08 00 00 00 	add    DWORD PTR [r14+0x8],0x1000000
  16:	01 
  17:	41 81 46 0c 00 00 00 	add    DWORD PTR [r14+0xc],0x1000000
  1e:	01 
  1f:	41 81 46 10 00 00 00 	add    DWORD PTR [r14+0x10],0x1000000
  26:	01 
  27:	41 81 46 14 00 00 00 	add    DWORD PTR [r14+0x14],0x1000000
  2e:	01 
  2f:	41 81 46 18 00 00 00 	add    DWORD PTR [r14+0x18],0x1000000
  36:	01 
  37:	41 81 46 1c 00 00 00 	add    DWORD PTR [r14+0x1c],0x1000000
  3e:	01

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.14
- Reference cycles: 7.31
- UOPS_EXECUTED.THREAD: 32.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.24
- UOPS_PORT_1: 2.78
- UOPS_PORT_2: 7.99
- UOPS_PORT_3: 7.99
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 5.82
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
   7:	41 81 46 04 00 00 00 	add    DWORD PTR [r14+0x4],0x1000000
   e:	01 
   f:	41 81 46 08 00 00 00 	add    DWORD PTR [r14+0x8],0x1000000
  16:	01 
  17:	41 81 46 0c 00 00 00 	add    DWORD PTR [r14+0xc],0x1000000
  1e:	01 
  1f:	41 81 46 10 00 00 00 	add    DWORD PTR [r14+0x10],0x1000000
  26:	01 
  27:	41 81 46 14 00 00 00 	add    DWORD PTR [r14+0x14],0x1000000
  2e:	01 
  2f:	41 81 46 18 00 00 00 	add    DWORD PTR [r14+0x18],0x1000000
  36:	01 
  37:	41 81 46 1c 00 00 00 	add    DWORD PTR [r14+0x1c],0x1000000
  3e:	01

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.04
- Reference cycles: 7.15
- UOPS_EXECUTED.THREAD: 33.01
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.17
- UOPS_PORT_1: 2.9
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.0
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 4.89
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
   8:	40                   	rex
   9:	41 81 46 04 00 00 00 	add    DWORD PTR [r14+0x4],0x1000000
  10:	01 
  11:	40                   	rex
  12:	41 81 46 08 00 00 00 	add    DWORD PTR [r14+0x8],0x1000000
  19:	01 
  1a:	40                   	rex
  1b:	41 81 46 0c 00 00 00 	add    DWORD PTR [r14+0xc],0x1000000
  22:	01 
  23:	40                   	rex
  24:	41 81 46 10 00 00 00 	add    DWORD PTR [r14+0x10],0x1000000
  2b:	01 
  2c:	40                   	rex
  2d:	41 81 46 14 00 00 00 	add    DWORD PTR [r14+0x14],0x1000000
  34:	01 
  35:	40                   	rex
  36:	41 81 46 18 00 00 00 	add    DWORD PTR [r14+0x18],0x1000000
  3d:	01 
  3e:	40                   	rex
  3f:	41 81 46 1c 00 00 00 	add    DWORD PTR [r14+0x1c],0x1000000
  46:	01

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.05
- Reference cycles: 7.17
- UOPS_EXECUTED.THREAD: 33.01
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.2
- UOPS_PORT_1: 2.89
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.01
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 5.2
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
   7:	41 81 46 04 00 00 00 	add    DWORD PTR [r14+0x4],0x1000000
   e:	01 
   f:	41 81 46 08 00 00 00 	add    DWORD PTR [r14+0x8],0x1000000
  16:	01 
  17:	41 81 46 0c 00 00 00 	add    DWORD PTR [r14+0xc],0x1000000
  1e:	01 
  1f:	41 81 46 10 00 00 00 	add    DWORD PTR [r14+0x10],0x1000000
  26:	01 
  27:	41 81 46 14 00 00 00 	add    DWORD PTR [r14+0x14],0x1000000
  2e:	01 
  2f:	41 81 46 18 00 00 00 	add    DWORD PTR [r14+0x18],0x1000000
  36:	01 
  37:	41 81 46 1c 00 00 00 	add    DWORD PTR [r14+0x1c],0x1000000
  3e:	01

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.11
- Reference cycles: 7.23
- UOPS_EXECUTED.THREAD: 32.11
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.58
- UOPS_PORT_1: 3.35
- UOPS_PORT_2: 7.97
- UOPS_PORT_3: 8.04
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 3.66
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
   8:	40                   	rex
   9:	41 81 46 04 00 00 00 	add    DWORD PTR [r14+0x4],0x1000000
  10:	01 
  11:	40                   	rex
  12:	41 81 46 08 00 00 00 	add    DWORD PTR [r14+0x8],0x1000000
  19:	01 
  1a:	40                   	rex
  1b:	41 81 46 0c 00 00 00 	add    DWORD PTR [r14+0xc],0x1000000
  22:	01 
  23:	40                   	rex
  24:	41 81 46 10 00 00 00 	add    DWORD PTR [r14+0x10],0x1000000
  2b:	01 
  2c:	40                   	rex
  2d:	41 81 46 14 00 00 00 	add    DWORD PTR [r14+0x14],0x1000000
  34:	01 
  35:	40                   	rex
  36:	41 81 46 18 00 00 00 	add    DWORD PTR [r14+0x18],0x1000000
  3d:	01 
  3e:	40                   	rex
  3f:	41 81 46 1c 00 00 00 	add    DWORD PTR [r14+0x1c],0x1000000
  46:	01

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.11
- Reference cycles: 7.22
- UOPS_EXECUTED.THREAD: 32.11
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.58
- UOPS_PORT_1: 3.35
- UOPS_PORT_2: 7.97
- UOPS_PORT_3: 8.04
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 3.66
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
   7:	41 81 46 04 00 00 00 	add    DWORD PTR [r14+0x4],0x1000000
   e:	01 
   f:	41 81 46 08 00 00 00 	add    DWORD PTR [r14+0x8],0x1000000
  16:	01 
  17:	41 81 46 0c 00 00 00 	add    DWORD PTR [r14+0xc],0x1000000
  1e:	01 
  1f:	41 81 46 10 00 00 00 	add    DWORD PTR [r14+0x10],0x1000000
  26:	01 
  27:	41 81 46 14 00 00 00 	add    DWORD PTR [r14+0x14],0x1000000
  2e:	01 
  2f:	41 81 46 18 00 00 00 	add    DWORD PTR [r14+0x18],0x1000000
  36:	01 
  37:	41 81 46 1c 00 00 00 	add    DWORD PTR [r14+0x1c],0x1000000
  3e:	01 
  3f:	41 81 46 20 00 00 00 	add    DWORD PTR [r14+0x20],0x1000000
  46:	01 
  47:	41 81 46 24 00 00 00 	add    DWORD PTR [r14+0x24],0x1000000
  4e:	01 
  4f:	41 81 46 28 00 00 00 	add    DWORD PTR [r14+0x28],0x1000000
  56:	01 
  57:	41 81 46 2c 00 00 00 	add    DWORD PTR [r14+0x2c],0x1000000
  5e:	01 
  5f:	41 81 46 30 00 00 00 	add    DWORD PTR [r14+0x30],0x1000000
  66:	01 
  67:	41 81 46 34 00 00 00 	add    DWORD PTR [r14+0x34],0x1000000
  6e:	01 
  6f:	41 81 46 38 00 00 00 	add    DWORD PTR [r14+0x38],0x1000000
  76:	01 
  77:	41 81 46 3c 00 00 00 	add    DWORD PTR [r14+0x3c],0x1000000
  7e:	01

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 16.18
- Reference cycles: 14.4
- UOPS_EXECUTED.THREAD: 64.0
- RETIRE_SLOTS: 32.0
- UOPS_MITE: 32.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 5.4
- UOPS_PORT_1: 4.88
- UOPS_PORT_2: 15.99
- UOPS_PORT_3: 16.01
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 9.34
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.01

With loop_count=1000 and unroll_count=1

Code:

   0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
   7:	41 81 46 04 00 00 00 	add    DWORD PTR [r14+0x4],0x1000000
   e:	01 
   f:	41 81 46 08 00 00 00 	add    DWORD PTR [r14+0x8],0x1000000
  16:	01 
  17:	41 81 46 0c 00 00 00 	add    DWORD PTR [r14+0xc],0x1000000
  1e:	01 
  1f:	41 81 46 10 00 00 00 	add    DWORD PTR [r14+0x10],0x1000000
  26:	01 
  27:	41 81 46 14 00 00 00 	add    DWORD PTR [r14+0x14],0x1000000
  2e:	01 
  2f:	41 81 46 18 00 00 00 	add    DWORD PTR [r14+0x18],0x1000000
  36:	01 
  37:	41 81 46 1c 00 00 00 	add    DWORD PTR [r14+0x1c],0x1000000
  3e:	01 
  3f:	41 81 46 20 00 00 00 	add    DWORD PTR [r14+0x20],0x1000000
  46:	01 
  47:	41 81 46 24 00 00 00 	add    DWORD PTR [r14+0x24],0x1000000
  4e:	01 
  4f:	41 81 46 28 00 00 00 	add    DWORD PTR [r14+0x28],0x1000000
  56:	01 
  57:	41 81 46 2c 00 00 00 	add    DWORD PTR [r14+0x2c],0x1000000
  5e:	01 
  5f:	41 81 46 30 00 00 00 	add    DWORD PTR [r14+0x30],0x1000000
  66:	01 
  67:	41 81 46 34 00 00 00 	add    DWORD PTR [r14+0x34],0x1000000
  6e:	01 
  6f:	41 81 46 38 00 00 00 	add    DWORD PTR [r14+0x38],0x1000000
  76:	01 
  77:	41 81 46 3c 00 00 00 	add    DWORD PTR [r14+0x3c],0x1000000
  7e:	01

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 16.03
- Reference cycles: 14.26
- UOPS_EXECUTED.THREAD: 65.01
- RETIRE_SLOTS: 33.0
- UOPS_MITE: 0.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 5.41
- UOPS_PORT_1: 4.89
- UOPS_PORT_2: 16.0
- UOPS_PORT_3: 16.01
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 7.99
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
   8:	40                   	rex
   9:	41 81 46 04 00 00 00 	add    DWORD PTR [r14+0x4],0x1000000
  10:	01 
  11:	40                   	rex
  12:	41 81 46 08 00 00 00 	add    DWORD PTR [r14+0x8],0x1000000
  19:	01 
  1a:	40                   	rex
  1b:	41 81 46 0c 00 00 00 	add    DWORD PTR [r14+0xc],0x1000000
  22:	01 
  23:	40                   	rex
  24:	41 81 46 10 00 00 00 	add    DWORD PTR [r14+0x10],0x1000000
  2b:	01 
  2c:	40                   	rex
  2d:	41 81 46 14 00 00 00 	add    DWORD PTR [r14+0x14],0x1000000
  34:	01 
  35:	40                   	rex
  36:	41 81 46 18 00 00 00 	add    DWORD PTR [r14+0x18],0x1000000
  3d:	01 
  3e:	40                   	rex
  3f:	41 81 46 1c 00 00 00 	add    DWORD PTR [r14+0x1c],0x1000000
  46:	01 
  47:	40                   	rex
  48:	41 81 46 20 00 00 00 	add    DWORD PTR [r14+0x20],0x1000000
  4f:	01 
  50:	40                   	rex
  51:	41 81 46 24 00 00 00 	add    DWORD PTR [r14+0x24],0x1000000
  58:	01 
  59:	40                   	rex
  5a:	41 81 46 28 00 00 00 	add    DWORD PTR [r14+0x28],0x1000000
  61:	01 
  62:	40                   	rex
  63:	41 81 46 2c 00 00 00 	add    DWORD PTR [r14+0x2c],0x1000000
  6a:	01 
  6b:	40                   	rex
  6c:	41 81 46 30 00 00 00 	add    DWORD PTR [r14+0x30],0x1000000
  73:	01 
  74:	40                   	rex
  75:	41 81 46 34 00 00 00 	add    DWORD PTR [r14+0x34],0x1000000
  7c:	01 
  7d:	40                   	rex
  7e:	41 81 46 38 00 00 00 	add    DWORD PTR [r14+0x38],0x1000000
  85:	01 
  86:	40                   	rex
  87:	41 81 46 3c 00 00 00 	add    DWORD PTR [r14+0x3c],0x1000000
  8e:	01

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 16.02
- Reference cycles: 14.25
- UOPS_EXECUTED.THREAD: 65.01
- RETIRE_SLOTS: 33.0
- UOPS_MITE: 0.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 5.41
- UOPS_PORT_1: 4.89
- UOPS_PORT_2: 16.0
- UOPS_PORT_3: 16.01
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 8.14
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
   7:	41 81 46 04 00 00 00 	add    DWORD PTR [r14+0x4],0x1000000
   e:	01 
   f:	41 81 46 08 00 00 00 	add    DWORD PTR [r14+0x8],0x1000000
  16:	01 
  17:	41 81 46 0c 00 00 00 	add    DWORD PTR [r14+0xc],0x1000000
  1e:	01 
  1f:	41 81 46 10 00 00 00 	add    DWORD PTR [r14+0x10],0x1000000
  26:	01 
  27:	41 81 46 14 00 00 00 	add    DWORD PTR [r14+0x14],0x1000000
  2e:	01 
  2f:	41 81 46 18 00 00 00 	add    DWORD PTR [r14+0x18],0x1000000
  36:	01 
  37:	41 81 46 1c 00 00 00 	add    DWORD PTR [r14+0x1c],0x1000000
  3e:	01 
  3f:	41 81 46 20 00 00 00 	add    DWORD PTR [r14+0x20],0x1000000
  46:	01 
  47:	41 81 46 24 00 00 00 	add    DWORD PTR [r14+0x24],0x1000000
  4e:	01 
  4f:	41 81 46 28 00 00 00 	add    DWORD PTR [r14+0x28],0x1000000
  56:	01 
  57:	41 81 46 2c 00 00 00 	add    DWORD PTR [r14+0x2c],0x1000000
  5e:	01 
  5f:	41 81 46 30 00 00 00 	add    DWORD PTR [r14+0x30],0x1000000
  66:	01 
  67:	41 81 46 34 00 00 00 	add    DWORD PTR [r14+0x34],0x1000000
  6e:	01 
  6f:	41 81 46 38 00 00 00 	add    DWORD PTR [r14+0x38],0x1000000
  76:	01 
  77:	41 81 46 3c 00 00 00 	add    DWORD PTR [r14+0x3c],0x1000000
  7e:	01

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 16.11
- Reference cycles: 14.32
- UOPS_EXECUTED.THREAD: 64.1
- RETIRE_SLOTS: 32.1
- UOPS_MITE: 0.32
- UOPS_MS: 0.0
- UOPS_PORT_0: 6.72
- UOPS_PORT_1: 6.25
- UOPS_PORT_2: 15.96
- UOPS_PORT_3: 16.04
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 6.91
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.16

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
   8:	40                   	rex
   9:	41 81 46 04 00 00 00 	add    DWORD PTR [r14+0x4],0x1000000
  10:	01 
  11:	40                   	rex
  12:	41 81 46 08 00 00 00 	add    DWORD PTR [r14+0x8],0x1000000
  19:	01 
  1a:	40                   	rex
  1b:	41 81 46 0c 00 00 00 	add    DWORD PTR [r14+0xc],0x1000000
  22:	01 
  23:	40                   	rex
  24:	41 81 46 10 00 00 00 	add    DWORD PTR [r14+0x10],0x1000000
  2b:	01 
  2c:	40                   	rex
  2d:	41 81 46 14 00 00 00 	add    DWORD PTR [r14+0x14],0x1000000
  34:	01 
  35:	40                   	rex
  36:	41 81 46 18 00 00 00 	add    DWORD PTR [r14+0x18],0x1000000
  3d:	01 
  3e:	40                   	rex
  3f:	41 81 46 1c 00 00 00 	add    DWORD PTR [r14+0x1c],0x1000000
  46:	01 
  47:	40                   	rex
  48:	41 81 46 20 00 00 00 	add    DWORD PTR [r14+0x20],0x1000000
  4f:	01 
  50:	40                   	rex
  51:	41 81 46 24 00 00 00 	add    DWORD PTR [r14+0x24],0x1000000
  58:	01 
  59:	40                   	rex
  5a:	41 81 46 28 00 00 00 	add    DWORD PTR [r14+0x28],0x1000000
  61:	01 
  62:	40                   	rex
  63:	41 81 46 2c 00 00 00 	add    DWORD PTR [r14+0x2c],0x1000000
  6a:	01 
  6b:	40                   	rex
  6c:	41 81 46 30 00 00 00 	add    DWORD PTR [r14+0x30],0x1000000
  73:	01 
  74:	40                   	rex
  75:	41 81 46 34 00 00 00 	add    DWORD PTR [r14+0x34],0x1000000
  7c:	01 
  7d:	40                   	rex
  7e:	41 81 46 38 00 00 00 	add    DWORD PTR [r14+0x38],0x1000000
  85:	01 
  86:	40                   	rex
  87:	41 81 46 3c 00 00 00 	add    DWORD PTR [r14+0x3c],0x1000000
  8e:	01

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 16.11
- Reference cycles: 14.34
- UOPS_EXECUTED.THREAD: 64.1
- RETIRE_SLOTS: 32.1
- UOPS_MITE: 0.32
- UOPS_MS: 0.0
- UOPS_PORT_0: 6.73
- UOPS_PORT_1: 6.26
- UOPS_PORT_2: 15.96
- UOPS_PORT_3: 16.04
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 6.91
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.16

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
   7:	01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 7.36
- Reference cycles: 6.55
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.91
- UOPS_PORT_1: 2.92
- UOPS_PORT_2: 0.92
- UOPS_PORT_3: 1.08
- UOPS_PORT_4: 1.63
- UOPS_PORT_5: 2.78
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
   7:	01 
   8:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 6.02
- Reference cycles: 5.37
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 3.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.88
- UOPS_PORT_1: 1.67
- UOPS_PORT_2: 0.59
- UOPS_PORT_3: 1.41
- UOPS_PORT_4: 5.58
- UOPS_PORT_5: 2.38
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
   7:	01 
   8:	90                   	nop
   9:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 6.0
- Reference cycles: 5.31
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.99
- UOPS_PORT_1: 2.15
- UOPS_PORT_2: 0.81
- UOPS_PORT_3: 1.19
- UOPS_PORT_4: 6.01
- UOPS_PORT_5: 1.97
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
   7:	01 
   8:	90                   	nop
   9:	90                   	nop
   a:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 7.0
- Reference cycles: 6.23
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 7.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.27
- UOPS_PORT_1: 1.07
- UOPS_PORT_2: 0.99
- UOPS_PORT_3: 1.01
- UOPS_PORT_4: 1.83
- UOPS_PORT_5: 2.67
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
   7:	01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 7.49
- Reference cycles: 6.66
- UOPS_EXECUTED.THREAD: 4.1
- RETIRE_SLOTS: 4.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.1
- UOPS_PORT_1: 2.09
- UOPS_PORT_2: 1.0
- UOPS_PORT_3: 1.0
- UOPS_PORT_4: 2.34
- UOPS_PORT_5: 1.94
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
   8:	01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 7.49
- Reference cycles: 6.66
- UOPS_EXECUTED.THREAD: 4.1
- RETIRE_SLOTS: 4.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.1
- UOPS_PORT_1: 2.09
- UOPS_PORT_2: 1.0
- UOPS_PORT_3: 1.0
- UOPS_PORT_4: 2.31
- UOPS_PORT_5: 1.94
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
   7:	01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 7.49
- Reference cycles: 6.66
- UOPS_EXECUTED.THREAD: 4.01
- RETIRE_SLOTS: 4.01
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.89
- UOPS_PORT_1: 2.86
- UOPS_PORT_2: 0.96
- UOPS_PORT_3: 1.04
- UOPS_PORT_4: 1.65
- UOPS_PORT_5: 2.68
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
   8:	01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 7.49
- Reference cycles: 6.66
- UOPS_EXECUTED.THREAD: 4.01
- RETIRE_SLOTS: 4.01
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.89
- UOPS_PORT_1: 2.86
- UOPS_PORT_2: 0.96
- UOPS_PORT_3: 1.04
- UOPS_PORT_4: 1.65
- UOPS_PORT_5: 2.68
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
   7:	01 
   8:	43 81 44 2e 04 00 00 	add    DWORD PTR [r14+r13*1+0x4],0x1000000
   f:	00 01 
  11:	43 81 44 2e 08 00 00 	add    DWORD PTR [r14+r13*1+0x8],0x1000000
  18:	00 01 
  1a:	43 81 44 2e 0c 00 00 	add    DWORD PTR [r14+r13*1+0xc],0x1000000
  21:	00 01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.01
- Reference cycles: 3.52
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 8.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.54
- UOPS_PORT_1: 1.23
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 4.0
- UOPS_PORT_5: 1.24
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.01

With loop_count=1000 and unroll_count=2

Code:

   0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
   7:	01 
   8:	43 81 44 2e 04 00 00 	add    DWORD PTR [r14+r13*1+0x4],0x1000000
   f:	00 01 
  11:	43 81 44 2e 08 00 00 	add    DWORD PTR [r14+r13*1+0x8],0x1000000
  18:	00 01 
  1a:	43 81 44 2e 0c 00 00 	add    DWORD PTR [r14+r13*1+0xc],0x1000000
  21:	00 01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 8.0
- Reference cycles: 7.12
- UOPS_EXECUTED.THREAD: 16.5
- RETIRE_SLOTS: 16.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.17
- UOPS_PORT_1: 4.01
- UOPS_PORT_2: 3.82
- UOPS_PORT_3: 4.18
- UOPS_PORT_4: 4.0
- UOPS_PORT_5: 4.07
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=1000, unroll_count=2, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
   8:	01 
   9:	40                   	rex
   a:	43 81 44 2e 04 00 00 	add    DWORD PTR [r14+r13*1+0x4],0x1000000
  11:	00 01 
  13:	40                   	rex
  14:	43 81 44 2e 08 00 00 	add    DWORD PTR [r14+r13*1+0x8],0x1000000
  1b:	00 01 
  1d:	40                   	rex
  1e:	43 81 44 2e 0c 00 00 	add    DWORD PTR [r14+r13*1+0xc],0x1000000
  25:	00 01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 8.0
- Reference cycles: 7.12
- UOPS_EXECUTED.THREAD: 16.5
- RETIRE_SLOTS: 16.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.17
- UOPS_PORT_1: 4.03
- UOPS_PORT_2: 3.83
- UOPS_PORT_3: 4.18
- UOPS_PORT_4: 4.0
- UOPS_PORT_5: 4.07
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
   7:	01 
   8:	43 81 44 2e 04 00 00 	add    DWORD PTR [r14+r13*1+0x4],0x1000000
   f:	00 01 
  11:	43 81 44 2e 08 00 00 	add    DWORD PTR [r14+r13*1+0x8],0x1000000
  18:	00 01 
  1a:	43 81 44 2e 0c 00 00 	add    DWORD PTR [r14+r13*1+0xc],0x1000000
  21:	00 01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 6.96
- Reference cycles: 6.18
- UOPS_EXECUTED.THREAD: 16.05
- RETIRE_SLOTS: 16.05
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.32
- UOPS_PORT_1: 3.16
- UOPS_PORT_2: 3.91
- UOPS_PORT_3: 4.09
- UOPS_PORT_4: 5.65
- UOPS_PORT_5: 3.07
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With loop_count=100, unroll_count=20, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
   8:	01 
   9:	40                   	rex
   a:	43 81 44 2e 04 00 00 	add    DWORD PTR [r14+r13*1+0x4],0x1000000
  11:	00 01 
  13:	40                   	rex
  14:	43 81 44 2e 08 00 00 	add    DWORD PTR [r14+r13*1+0x8],0x1000000
  1b:	00 01 
  1d:	40                   	rex
  1e:	43 81 44 2e 0c 00 00 	add    DWORD PTR [r14+r13*1+0xc],0x1000000
  25:	00 01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 6.17
- Reference cycles: 5.49
- UOPS_EXECUTED.THREAD: 16.05
- RETIRE_SLOTS: 16.05
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.31
- UOPS_PORT_1: 3.14
- UOPS_PORT_2: 3.92
- UOPS_PORT_3: 4.09
- UOPS_PORT_4: 5.65
- UOPS_PORT_5: 3.07
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
   7:	01 
   8:	43 81 44 2e 04 00 00 	add    DWORD PTR [r14+r13*1+0x4],0x1000000
   f:	00 01 
  11:	43 81 44 2e 08 00 00 	add    DWORD PTR [r14+r13*1+0x8],0x1000000
  18:	00 01 
  1a:	43 81 44 2e 0c 00 00 	add    DWORD PTR [r14+r13*1+0xc],0x1000000
  21:	00 01 
  23:	43 81 44 2e 10 00 00 	add    DWORD PTR [r14+r13*1+0x10],0x1000000
  2a:	00 01 
  2c:	43 81 44 2e 14 00 00 	add    DWORD PTR [r14+r13*1+0x14],0x1000000
  33:	00 01 
  35:	43 81 44 2e 18 00 00 	add    DWORD PTR [r14+r13*1+0x18],0x1000000
  3c:	00 01 
  3e:	43 81 44 2e 1c 00 00 	add    DWORD PTR [r14+r13*1+0x1c],0x1000000
  45:	00 01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.13
- Reference cycles: 7.04
- UOPS_EXECUTED.THREAD: 32.0
- RETIRE_SLOTS: 32.0
- UOPS_MITE: 16.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.95
- UOPS_PORT_1: 2.53
- UOPS_PORT_2: 7.99
- UOPS_PORT_3: 8.01
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 2.52
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.01

With loop_count=1000 and unroll_count=1

Code:

   0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
   7:	01 
   8:	43 81 44 2e 04 00 00 	add    DWORD PTR [r14+r13*1+0x4],0x1000000
   f:	00 01 
  11:	43 81 44 2e 08 00 00 	add    DWORD PTR [r14+r13*1+0x8],0x1000000
  18:	00 01 
  1a:	43 81 44 2e 0c 00 00 	add    DWORD PTR [r14+r13*1+0xc],0x1000000
  21:	00 01 
  23:	43 81 44 2e 10 00 00 	add    DWORD PTR [r14+r13*1+0x10],0x1000000
  2a:	00 01 
  2c:	43 81 44 2e 14 00 00 	add    DWORD PTR [r14+r13*1+0x14],0x1000000
  33:	00 01 
  35:	43 81 44 2e 18 00 00 	add    DWORD PTR [r14+r13*1+0x18],0x1000000
  3c:	00 01 
  3e:	43 81 44 2e 1c 00 00 	add    DWORD PTR [r14+r13*1+0x1c],0x1000000
  45:	00 01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 9.01
- Reference cycles: 8.02
- UOPS_EXECUTED.THREAD: 33.01
- RETIRE_SLOTS: 33.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.03
- UOPS_PORT_1: 3.03
- UOPS_PORT_2: 7.99
- UOPS_PORT_3: 8.02
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 3.02
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
   8:	01 
   9:	40                   	rex
   a:	43 81 44 2e 04 00 00 	add    DWORD PTR [r14+r13*1+0x4],0x1000000
  11:	00 01 
  13:	40                   	rex
  14:	43 81 44 2e 08 00 00 	add    DWORD PTR [r14+r13*1+0x8],0x1000000
  1b:	00 01 
  1d:	40                   	rex
  1e:	43 81 44 2e 0c 00 00 	add    DWORD PTR [r14+r13*1+0xc],0x1000000
  25:	00 01 
  27:	40                   	rex
  28:	43 81 44 2e 10 00 00 	add    DWORD PTR [r14+r13*1+0x10],0x1000000
  2f:	00 01 
  31:	40                   	rex
  32:	43 81 44 2e 14 00 00 	add    DWORD PTR [r14+r13*1+0x14],0x1000000
  39:	00 01 
  3b:	40                   	rex
  3c:	43 81 44 2e 18 00 00 	add    DWORD PTR [r14+r13*1+0x18],0x1000000
  43:	00 01 
  45:	40                   	rex
  46:	43 81 44 2e 1c 00 00 	add    DWORD PTR [r14+r13*1+0x1c],0x1000000
  4d:	00 01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 9.01
- Reference cycles: 8.02
- UOPS_EXECUTED.THREAD: 33.01
- RETIRE_SLOTS: 33.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.03
- UOPS_PORT_1: 3.03
- UOPS_PORT_2: 7.99
- UOPS_PORT_3: 8.02
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 3.02
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
   7:	01 
   8:	43 81 44 2e 04 00 00 	add    DWORD PTR [r14+r13*1+0x4],0x1000000
   f:	00 01 
  11:	43 81 44 2e 08 00 00 	add    DWORD PTR [r14+r13*1+0x8],0x1000000
  18:	00 01 
  1a:	43 81 44 2e 0c 00 00 	add    DWORD PTR [r14+r13*1+0xc],0x1000000
  21:	00 01 
  23:	43 81 44 2e 10 00 00 	add    DWORD PTR [r14+r13*1+0x10],0x1000000
  2a:	00 01 
  2c:	43 81 44 2e 14 00 00 	add    DWORD PTR [r14+r13*1+0x14],0x1000000
  33:	00 01 
  35:	43 81 44 2e 18 00 00 	add    DWORD PTR [r14+r13*1+0x18],0x1000000
  3c:	00 01 
  3e:	43 81 44 2e 1c 00 00 	add    DWORD PTR [r14+r13*1+0x1c],0x1000000
  45:	00 01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.11
- Reference cycles: 7.22
- UOPS_EXECUTED.THREAD: 32.11
- RETIRE_SLOTS: 32.1
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.03
- UOPS_PORT_1: 2.53
- UOPS_PORT_2: 7.99
- UOPS_PORT_3: 8.02
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 2.57
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
   8:	01 
   9:	40                   	rex
   a:	43 81 44 2e 04 00 00 	add    DWORD PTR [r14+r13*1+0x4],0x1000000
  11:	00 01 
  13:	40                   	rex
  14:	43 81 44 2e 08 00 00 	add    DWORD PTR [r14+r13*1+0x8],0x1000000
  1b:	00 01 
  1d:	40                   	rex
  1e:	43 81 44 2e 0c 00 00 	add    DWORD PTR [r14+r13*1+0xc],0x1000000
  25:	00 01 
  27:	40                   	rex
  28:	43 81 44 2e 10 00 00 	add    DWORD PTR [r14+r13*1+0x10],0x1000000
  2f:	00 01 
  31:	40                   	rex
  32:	43 81 44 2e 14 00 00 	add    DWORD PTR [r14+r13*1+0x14],0x1000000
  39:	00 01 
  3b:	40                   	rex
  3c:	43 81 44 2e 18 00 00 	add    DWORD PTR [r14+r13*1+0x18],0x1000000
  43:	00 01 
  45:	40                   	rex
  46:	43 81 44 2e 1c 00 00 	add    DWORD PTR [r14+r13*1+0x1c],0x1000000
  4d:	00 01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.11
- Reference cycles: 7.2
- UOPS_EXECUTED.THREAD: 32.11
- RETIRE_SLOTS: 32.1
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.03
- UOPS_PORT_1: 2.53
- UOPS_PORT_2: 7.99
- UOPS_PORT_3: 8.02
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 2.57
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
   7:	01 
   8:	43 81 44 2e 04 00 00 	add    DWORD PTR [r14+r13*1+0x4],0x1000000
   f:	00 01 
  11:	43 81 44 2e 08 00 00 	add    DWORD PTR [r14+r13*1+0x8],0x1000000
  18:	00 01 
  1a:	43 81 44 2e 0c 00 00 	add    DWORD PTR [r14+r13*1+0xc],0x1000000
  21:	00 01 
  23:	43 81 44 2e 10 00 00 	add    DWORD PTR [r14+r13*1+0x10],0x1000000
  2a:	00 01 
  2c:	43 81 44 2e 14 00 00 	add    DWORD PTR [r14+r13*1+0x14],0x1000000
  33:	00 01 
  35:	43 81 44 2e 18 00 00 	add    DWORD PTR [r14+r13*1+0x18],0x1000000
  3c:	00 01 
  3e:	43 81 44 2e 1c 00 00 	add    DWORD PTR [r14+r13*1+0x1c],0x1000000
  45:	00 01 
  47:	43 81 44 2e 20 00 00 	add    DWORD PTR [r14+r13*1+0x20],0x1000000
  4e:	00 01 
  50:	43 81 44 2e 24 00 00 	add    DWORD PTR [r14+r13*1+0x24],0x1000000
  57:	00 01 
  59:	43 81 44 2e 28 00 00 	add    DWORD PTR [r14+r13*1+0x28],0x1000000
  60:	00 01 
  62:	43 81 44 2e 2c 00 00 	add    DWORD PTR [r14+r13*1+0x2c],0x1000000
  69:	00 01 
  6b:	43 81 44 2e 30 00 00 	add    DWORD PTR [r14+r13*1+0x30],0x1000000
  72:	00 01 
  74:	43 81 44 2e 34 00 00 	add    DWORD PTR [r14+r13*1+0x34],0x1000000
  7b:	00 01 
  7d:	43 81 44 2e 38 00 00 	add    DWORD PTR [r14+r13*1+0x38],0x1000000
  84:	00 01 
  86:	43 81 44 2e 3c 00 00 	add    DWORD PTR [r14+r13*1+0x3c],0x1000000
  8d:	00 01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 16.09
- Reference cycles: 14.29
- UOPS_EXECUTED.THREAD: 64.06
- RETIRE_SLOTS: 64.06
- UOPS_MITE: 32.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 6.18
- UOPS_PORT_1: 4.96
- UOPS_PORT_2: 15.99
- UOPS_PORT_3: 16.01
- UOPS_PORT_4: 16.03
- UOPS_PORT_5: 4.95
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.04

With loop_count=1000 and unroll_count=1

Code:

   0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
   7:	01 
   8:	43 81 44 2e 04 00 00 	add    DWORD PTR [r14+r13*1+0x4],0x1000000
   f:	00 01 
  11:	43 81 44 2e 08 00 00 	add    DWORD PTR [r14+r13*1+0x8],0x1000000
  18:	00 01 
  1a:	43 81 44 2e 0c 00 00 	add    DWORD PTR [r14+r13*1+0xc],0x1000000
  21:	00 01 
  23:	43 81 44 2e 10 00 00 	add    DWORD PTR [r14+r13*1+0x10],0x1000000
  2a:	00 01 
  2c:	43 81 44 2e 14 00 00 	add    DWORD PTR [r14+r13*1+0x14],0x1000000
  33:	00 01 
  35:	43 81 44 2e 18 00 00 	add    DWORD PTR [r14+r13*1+0x18],0x1000000
  3c:	00 01 
  3e:	43 81 44 2e 1c 00 00 	add    DWORD PTR [r14+r13*1+0x1c],0x1000000
  45:	00 01 
  47:	43 81 44 2e 20 00 00 	add    DWORD PTR [r14+r13*1+0x20],0x1000000
  4e:	00 01 
  50:	43 81 44 2e 24 00 00 	add    DWORD PTR [r14+r13*1+0x24],0x1000000
  57:	00 01 
  59:	43 81 44 2e 28 00 00 	add    DWORD PTR [r14+r13*1+0x28],0x1000000
  60:	00 01 
  62:	43 81 44 2e 2c 00 00 	add    DWORD PTR [r14+r13*1+0x2c],0x1000000
  69:	00 01 
  6b:	43 81 44 2e 30 00 00 	add    DWORD PTR [r14+r13*1+0x30],0x1000000
  72:	00 01 
  74:	43 81 44 2e 34 00 00 	add    DWORD PTR [r14+r13*1+0x34],0x1000000
  7b:	00 01 
  7d:	43 81 44 2e 38 00 00 	add    DWORD PTR [r14+r13*1+0x38],0x1000000
  84:	00 01 
  86:	43 81 44 2e 3c 00 00 	add    DWORD PTR [r14+r13*1+0x3c],0x1000000
  8d:	00 01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 17.01
- Reference cycles: 15.13
- UOPS_EXECUTED.THREAD: 65.01
- RETIRE_SLOTS: 65.0
- UOPS_MITE: 0.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 9.95
- UOPS_PORT_1: 8.49
- UOPS_PORT_2: 15.99
- UOPS_PORT_3: 16.02
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 8.97
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
   8:	01 
   9:	40                   	rex
   a:	43 81 44 2e 04 00 00 	add    DWORD PTR [r14+r13*1+0x4],0x1000000
  11:	00 01 
  13:	40                   	rex
  14:	43 81 44 2e 08 00 00 	add    DWORD PTR [r14+r13*1+0x8],0x1000000
  1b:	00 01 
  1d:	40                   	rex
  1e:	43 81 44 2e 0c 00 00 	add    DWORD PTR [r14+r13*1+0xc],0x1000000
  25:	00 01 
  27:	40                   	rex
  28:	43 81 44 2e 10 00 00 	add    DWORD PTR [r14+r13*1+0x10],0x1000000
  2f:	00 01 
  31:	40                   	rex
  32:	43 81 44 2e 14 00 00 	add    DWORD PTR [r14+r13*1+0x14],0x1000000
  39:	00 01 
  3b:	40                   	rex
  3c:	43 81 44 2e 18 00 00 	add    DWORD PTR [r14+r13*1+0x18],0x1000000
  43:	00 01 
  45:	40                   	rex
  46:	43 81 44 2e 1c 00 00 	add    DWORD PTR [r14+r13*1+0x1c],0x1000000
  4d:	00 01 
  4f:	40                   	rex
  50:	43 81 44 2e 20 00 00 	add    DWORD PTR [r14+r13*1+0x20],0x1000000
  57:	00 01 
  59:	40                   	rex
  5a:	43 81 44 2e 24 00 00 	add    DWORD PTR [r14+r13*1+0x24],0x1000000
  61:	00 01 
  63:	40                   	rex
  64:	43 81 44 2e 28 00 00 	add    DWORD PTR [r14+r13*1+0x28],0x1000000
  6b:	00 01 
  6d:	40                   	rex
  6e:	43 81 44 2e 2c 00 00 	add    DWORD PTR [r14+r13*1+0x2c],0x1000000
  75:	00 01 
  77:	40                   	rex
  78:	43 81 44 2e 30 00 00 	add    DWORD PTR [r14+r13*1+0x30],0x1000000
  7f:	00 01 
  81:	40                   	rex
  82:	43 81 44 2e 34 00 00 	add    DWORD PTR [r14+r13*1+0x34],0x1000000
  89:	00 01 
  8b:	40                   	rex
  8c:	43 81 44 2e 38 00 00 	add    DWORD PTR [r14+r13*1+0x38],0x1000000
  93:	00 01 
  95:	40                   	rex
  96:	43 81 44 2e 3c 00 00 	add    DWORD PTR [r14+r13*1+0x3c],0x1000000
  9d:	00 01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 17.01
- Reference cycles: 15.13
- UOPS_EXECUTED.THREAD: 65.01
- RETIRE_SLOTS: 65.0
- UOPS_MITE: 0.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 9.95
- UOPS_PORT_1: 8.65
- UOPS_PORT_2: 15.99
- UOPS_PORT_3: 16.02
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 8.97
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
   7:	01 
   8:	43 81 44 2e 04 00 00 	add    DWORD PTR [r14+r13*1+0x4],0x1000000
   f:	00 01 
  11:	43 81 44 2e 08 00 00 	add    DWORD PTR [r14+r13*1+0x8],0x1000000
  18:	00 01 
  1a:	43 81 44 2e 0c 00 00 	add    DWORD PTR [r14+r13*1+0xc],0x1000000
  21:	00 01 
  23:	43 81 44 2e 10 00 00 	add    DWORD PTR [r14+r13*1+0x10],0x1000000
  2a:	00 01 
  2c:	43 81 44 2e 14 00 00 	add    DWORD PTR [r14+r13*1+0x14],0x1000000
  33:	00 01 
  35:	43 81 44 2e 18 00 00 	add    DWORD PTR [r14+r13*1+0x18],0x1000000
  3c:	00 01 
  3e:	43 81 44 2e 1c 00 00 	add    DWORD PTR [r14+r13*1+0x1c],0x1000000
  45:	00 01 
  47:	43 81 44 2e 20 00 00 	add    DWORD PTR [r14+r13*1+0x20],0x1000000
  4e:	00 01 
  50:	43 81 44 2e 24 00 00 	add    DWORD PTR [r14+r13*1+0x24],0x1000000
  57:	00 01 
  59:	43 81 44 2e 28 00 00 	add    DWORD PTR [r14+r13*1+0x28],0x1000000
  60:	00 01 
  62:	43 81 44 2e 2c 00 00 	add    DWORD PTR [r14+r13*1+0x2c],0x1000000
  69:	00 01 
  6b:	43 81 44 2e 30 00 00 	add    DWORD PTR [r14+r13*1+0x30],0x1000000
  72:	00 01 
  74:	43 81 44 2e 34 00 00 	add    DWORD PTR [r14+r13*1+0x34],0x1000000
  7b:	00 01 
  7d:	43 81 44 2e 38 00 00 	add    DWORD PTR [r14+r13*1+0x38],0x1000000
  84:	00 01 
  86:	43 81 44 2e 3c 00 00 	add    DWORD PTR [r14+r13*1+0x3c],0x1000000
  8d:	00 01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 16.11
- Reference cycles: 14.33
- UOPS_EXECUTED.THREAD: 64.11
- RETIRE_SLOTS: 64.1
- UOPS_MITE: 0.32
- UOPS_MS: 0.0
- UOPS_PORT_0: 6.43
- UOPS_PORT_1: 5.47
- UOPS_PORT_2: 15.99
- UOPS_PORT_3: 16.02
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 5.55
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.16

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
   8:	01 
   9:	40                   	rex
   a:	43 81 44 2e 04 00 00 	add    DWORD PTR [r14+r13*1+0x4],0x1000000
  11:	00 01 
  13:	40                   	rex
  14:	43 81 44 2e 08 00 00 	add    DWORD PTR [r14+r13*1+0x8],0x1000000
  1b:	00 01 
  1d:	40                   	rex
  1e:	43 81 44 2e 0c 00 00 	add    DWORD PTR [r14+r13*1+0xc],0x1000000
  25:	00 01 
  27:	40                   	rex
  28:	43 81 44 2e 10 00 00 	add    DWORD PTR [r14+r13*1+0x10],0x1000000
  2f:	00 01 
  31:	40                   	rex
  32:	43 81 44 2e 14 00 00 	add    DWORD PTR [r14+r13*1+0x14],0x1000000
  39:	00 01 
  3b:	40                   	rex
  3c:	43 81 44 2e 18 00 00 	add    DWORD PTR [r14+r13*1+0x18],0x1000000
  43:	00 01 
  45:	40                   	rex
  46:	43 81 44 2e 1c 00 00 	add    DWORD PTR [r14+r13*1+0x1c],0x1000000
  4d:	00 01 
  4f:	40                   	rex
  50:	43 81 44 2e 20 00 00 	add    DWORD PTR [r14+r13*1+0x20],0x1000000
  57:	00 01 
  59:	40                   	rex
  5a:	43 81 44 2e 24 00 00 	add    DWORD PTR [r14+r13*1+0x24],0x1000000
  61:	00 01 
  63:	40                   	rex
  64:	43 81 44 2e 28 00 00 	add    DWORD PTR [r14+r13*1+0x28],0x1000000
  6b:	00 01 
  6d:	40                   	rex
  6e:	43 81 44 2e 2c 00 00 	add    DWORD PTR [r14+r13*1+0x2c],0x1000000
  75:	00 01 
  77:	40                   	rex
  78:	43 81 44 2e 30 00 00 	add    DWORD PTR [r14+r13*1+0x30],0x1000000
  7f:	00 01 
  81:	40                   	rex
  82:	43 81 44 2e 34 00 00 	add    DWORD PTR [r14+r13*1+0x34],0x1000000
  89:	00 01 
  8b:	40                   	rex
  8c:	43 81 44 2e 38 00 00 	add    DWORD PTR [r14+r13*1+0x38],0x1000000
  93:	00 01 
  95:	40                   	rex
  96:	43 81 44 2e 3c 00 00 	add    DWORD PTR [r14+r13*1+0x3c],0x1000000
  9d:	00 01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 16.11
- Reference cycles: 14.33
- UOPS_EXECUTED.THREAD: 64.11
- RETIRE_SLOTS: 64.1
- UOPS_MITE: 0.32
- UOPS_MS: 0.0
- UOPS_PORT_0: 6.43
- UOPS_PORT_1: 5.47
- UOPS_PORT_2: 15.99
- UOPS_PORT_3: 16.02
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 5.55
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.16

ADD (M32, I32) - Throughput and Uops

With a non-indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

With loop_count=100 and unroll_count=100

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=1000, unroll_count=2, and padding (redundant prefixes)

With loop_count=100 and unroll_count=20

With loop_count=100, unroll_count=20, and padding (redundant prefixes)

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

With loop_count=100 and unroll_count=100

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=1000, unroll_count=2, and padding (redundant prefixes)

With loop_count=100 and unroll_count=20

With loop_count=100, unroll_count=20, and padding (redundant prefixes)

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (redundant prefixes)