VPTERNLOGD (XMM, XMM, XMM, I8)

With unroll_count=500 and no inner loop

Code:

   0:	62 f3 75 08 25 c2 02 	vpternlogd xmm0,xmm1,xmm2,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.34
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.33
- UOPS_PORT_1: 0.34
- UOPS_PORT_5: 0.33
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	62 f3 75 08 25 c2 02 	vpternlogd xmm0,xmm1,xmm2,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 0.33
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.33
- UOPS_PORT_1: 0.33
- UOPS_PORT_5: 0.34
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 f3 75 08 25 c2 02 	vpternlogd xmm0,xmm1,xmm2,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 0.33
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.33
- UOPS_PORT_1: 0.33
- UOPS_PORT_5: 0.34
- UOPS_PORT_6: 0.01
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 f3 75 08 25 c2 02 	vpternlogd xmm0,xmm1,xmm2,0x2
   7:	62 f3 75 08 25 da 02 	vpternlogd xmm3,xmm1,xmm2,0x2
   e:	62 f3 75 08 25 e2 02 	vpternlogd xmm4,xmm1,xmm2,0x2
  15:	62 f3 75 08 25 ea 02 	vpternlogd xmm5,xmm1,xmm2,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3;
VXORPS XMM4, XMM4, XMM4;
VXORPS XMM5, XMM5, XMM5

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 1.75
- Reference cycles: 0.57
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 3.96
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.3
- UOPS_PORT_1: 1.3
- UOPS_PORT_5: 1.4
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.75

With loop_count=1000 and unroll_count=2

Code:

   0:	62 f3 75 08 25 c2 02 	vpternlogd xmm0,xmm1,xmm2,0x2
   7:	62 f3 75 08 25 da 02 	vpternlogd xmm3,xmm1,xmm2,0x2
   e:	62 f3 75 08 25 e2 02 	vpternlogd xmm4,xmm1,xmm2,0x2
  15:	62 f3 75 08 25 ea 02 	vpternlogd xmm5,xmm1,xmm2,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3;
VXORPS XMM4, XMM4, XMM4;
VXORPS XMM5, XMM5, XMM5

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 1.49
- Reference cycles: 0.49
- UOPS_EXECUTED.THREAD: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.01
- UOPS_PORT_0: 1.32
- UOPS_PORT_1: 1.33
- UOPS_PORT_5: 1.35
- UOPS_PORT_6: 0.5
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	62 f3 75 08 25 c2 02 	vpternlogd xmm0,xmm1,xmm2,0x2
   7:	62 f3 75 08 25 da 02 	vpternlogd xmm3,xmm1,xmm2,0x2
   e:	62 f3 75 08 25 e2 02 	vpternlogd xmm4,xmm1,xmm2,0x2
  15:	62 f3 75 08 25 ea 02 	vpternlogd xmm5,xmm1,xmm2,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3;
VXORPS XMM4, XMM4, XMM4;
VXORPS XMM5, XMM5, XMM5

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 1.49
- Reference cycles: 0.49
- UOPS_EXECUTED.THREAD: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.01
- UOPS_PORT_0: 1.32
- UOPS_PORT_1: 1.33
- UOPS_PORT_5: 1.35
- UOPS_PORT_6: 0.05
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f3 75 08 25 c2 02 	vpternlogd xmm0,xmm1,xmm2,0x2
   7:	62 f3 75 08 25 da 02 	vpternlogd xmm3,xmm1,xmm2,0x2
   e:	62 f3 75 08 25 e2 02 	vpternlogd xmm4,xmm1,xmm2,0x2
  15:	62 f3 75 08 25 ea 02 	vpternlogd xmm5,xmm1,xmm2,0x2
  1c:	62 f3 75 08 25 f2 02 	vpternlogd xmm6,xmm1,xmm2,0x2
  23:	62 f3 75 08 25 fa 02 	vpternlogd xmm7,xmm1,xmm2,0x2
  2a:	62 73 75 08 25 c2 02 	vpternlogd xmm8,xmm1,xmm2,0x2
  31:	62 73 75 08 25 ca 02 	vpternlogd xmm9,xmm1,xmm2,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3;
VXORPS XMM4, XMM4, XMM4;
VXORPS XMM5, XMM5, XMM5;
VXORPS XMM6, XMM6, XMM6;
VXORPS XMM7, XMM7, XMM7;
VXORPS XMM8, XMM8, XMM8;
VXORPS XMM9, XMM9, XMM9

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 3.5
- Reference cycles: 1.24
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 7.99
- UOPS_MITE: 8.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.5
- UOPS_PORT_1: 2.74
- UOPS_PORT_5: 2.76
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 3.5

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f3 75 08 25 c2 02 	vpternlogd xmm0,xmm1,xmm2,0x2
   7:	62 f3 75 08 25 da 02 	vpternlogd xmm3,xmm1,xmm2,0x2
   e:	62 f3 75 08 25 e2 02 	vpternlogd xmm4,xmm1,xmm2,0x2
  15:	62 f3 75 08 25 ea 02 	vpternlogd xmm5,xmm1,xmm2,0x2
  1c:	62 f3 75 08 25 f2 02 	vpternlogd xmm6,xmm1,xmm2,0x2
  23:	62 f3 75 08 25 fa 02 	vpternlogd xmm7,xmm1,xmm2,0x2
  2a:	62 73 75 08 25 c2 02 	vpternlogd xmm8,xmm1,xmm2,0x2
  31:	62 73 75 08 25 ca 02 	vpternlogd xmm9,xmm1,xmm2,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3;
VXORPS XMM4, XMM4, XMM4;
VXORPS XMM5, XMM5, XMM5;
VXORPS XMM6, XMM6, XMM6;
VXORPS XMM7, XMM7, XMM7;
VXORPS XMM8, XMM8, XMM8;
VXORPS XMM9, XMM9, XMM9

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 2.68
- Reference cycles: 0.88
- UOPS_EXECUTED.THREAD: 9.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.02
- UOPS_PORT_0: 2.67
- UOPS_PORT_1: 2.67
- UOPS_PORT_5: 2.67
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	62 f3 75 08 25 c2 02 	vpternlogd xmm0,xmm1,xmm2,0x2
   7:	62 f3 75 08 25 da 02 	vpternlogd xmm3,xmm1,xmm2,0x2
   e:	62 f3 75 08 25 e2 02 	vpternlogd xmm4,xmm1,xmm2,0x2
  15:	62 f3 75 08 25 ea 02 	vpternlogd xmm5,xmm1,xmm2,0x2
  1c:	62 f3 75 08 25 f2 02 	vpternlogd xmm6,xmm1,xmm2,0x2
  23:	62 f3 75 08 25 fa 02 	vpternlogd xmm7,xmm1,xmm2,0x2
  2a:	62 73 75 08 25 c2 02 	vpternlogd xmm8,xmm1,xmm2,0x2
  31:	62 73 75 08 25 ca 02 	vpternlogd xmm9,xmm1,xmm2,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3;
VXORPS XMM4, XMM4, XMM4;
VXORPS XMM5, XMM5, XMM5;
VXORPS XMM6, XMM6, XMM6;
VXORPS XMM7, XMM7, XMM7;
VXORPS XMM8, XMM8, XMM8;
VXORPS XMM9, XMM9, XMM9

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 2.68
- Reference cycles: 0.96
- UOPS_EXECUTED.THREAD: 8.1
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.06
- UOPS_MS: 0.02
- UOPS_PORT_0: 2.67
- UOPS_PORT_1: 2.67
- UOPS_PORT_5: 2.67
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f3 75 08 25 c2 02 	vpternlogd xmm0,xmm1,xmm2,0x2
   7:	62 f3 75 08 25 da 02 	vpternlogd xmm3,xmm1,xmm2,0x2
   e:	62 f3 75 08 25 e2 02 	vpternlogd xmm4,xmm1,xmm2,0x2
  15:	62 f3 75 08 25 ea 02 	vpternlogd xmm5,xmm1,xmm2,0x2
  1c:	62 f3 75 08 25 f2 02 	vpternlogd xmm6,xmm1,xmm2,0x2
  23:	62 f3 75 08 25 fa 02 	vpternlogd xmm7,xmm1,xmm2,0x2
  2a:	62 73 75 08 25 c2 02 	vpternlogd xmm8,xmm1,xmm2,0x2
  31:	62 73 75 08 25 ca 02 	vpternlogd xmm9,xmm1,xmm2,0x2
  38:	62 73 75 08 25 d2 02 	vpternlogd xmm10,xmm1,xmm2,0x2
  3f:	62 73 75 08 25 da 02 	vpternlogd xmm11,xmm1,xmm2,0x2
  46:	62 73 75 08 25 e2 02 	vpternlogd xmm12,xmm1,xmm2,0x2
  4d:	62 e3 75 08 25 c2 02 	vpternlogd xmm16,xmm1,xmm2,0x2
  54:	62 e3 75 08 25 ca 02 	vpternlogd xmm17,xmm1,xmm2,0x2
  5b:	62 e3 75 08 25 d2 02 	vpternlogd xmm18,xmm1,xmm2,0x2
  62:	62 e3 75 08 25 da 02 	vpternlogd xmm19,xmm1,xmm2,0x2
  69:	62 e3 75 08 25 e2 02 	vpternlogd xmm20,xmm1,xmm2,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3;
VXORPS XMM4, XMM4, XMM4;
VXORPS XMM5, XMM5, XMM5;
VXORPS XMM6, XMM6, XMM6;
VXORPS XMM7, XMM7, XMM7;
VXORPS XMM8, XMM8, XMM8;
VXORPS XMM9, XMM9, XMM9;
VXORPS XMM10, XMM10, XMM10;
VXORPS XMM11, XMM11, XMM11;
VXORPS XMM12, XMM12, XMM12;
VXORPS XMM16, XMM16, XMM16;
VXORPS XMM17, XMM17, XMM17;
VXORPS XMM18, XMM18, XMM18;
VXORPS XMM19, XMM19, XMM19;
VXORPS XMM20, XMM20, XMM20

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 7.0
- Reference cycles: 2.58
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 5.01
- UOPS_PORT_1: 5.49
- UOPS_PORT_5: 5.5
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 7.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f3 75 08 25 c2 02 	vpternlogd xmm0,xmm1,xmm2,0x2
   7:	62 f3 75 08 25 da 02 	vpternlogd xmm3,xmm1,xmm2,0x2
   e:	62 f3 75 08 25 e2 02 	vpternlogd xmm4,xmm1,xmm2,0x2
  15:	62 f3 75 08 25 ea 02 	vpternlogd xmm5,xmm1,xmm2,0x2
  1c:	62 f3 75 08 25 f2 02 	vpternlogd xmm6,xmm1,xmm2,0x2
  23:	62 f3 75 08 25 fa 02 	vpternlogd xmm7,xmm1,xmm2,0x2
  2a:	62 73 75 08 25 c2 02 	vpternlogd xmm8,xmm1,xmm2,0x2
  31:	62 73 75 08 25 ca 02 	vpternlogd xmm9,xmm1,xmm2,0x2
  38:	62 73 75 08 25 d2 02 	vpternlogd xmm10,xmm1,xmm2,0x2
  3f:	62 73 75 08 25 da 02 	vpternlogd xmm11,xmm1,xmm2,0x2
  46:	62 73 75 08 25 e2 02 	vpternlogd xmm12,xmm1,xmm2,0x2
  4d:	62 e3 75 08 25 c2 02 	vpternlogd xmm16,xmm1,xmm2,0x2
  54:	62 e3 75 08 25 ca 02 	vpternlogd xmm17,xmm1,xmm2,0x2
  5b:	62 e3 75 08 25 d2 02 	vpternlogd xmm18,xmm1,xmm2,0x2
  62:	62 e3 75 08 25 da 02 	vpternlogd xmm19,xmm1,xmm2,0x2
  69:	62 e3 75 08 25 e2 02 	vpternlogd xmm20,xmm1,xmm2,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3;
VXORPS XMM4, XMM4, XMM4;
VXORPS XMM5, XMM5, XMM5;
VXORPS XMM6, XMM6, XMM6;
VXORPS XMM7, XMM7, XMM7;
VXORPS XMM8, XMM8, XMM8;
VXORPS XMM9, XMM9, XMM9;
VXORPS XMM10, XMM10, XMM10;
VXORPS XMM11, XMM11, XMM11;
VXORPS XMM12, XMM12, XMM12;
VXORPS XMM16, XMM16, XMM16;
VXORPS XMM17, XMM17, XMM17;
VXORPS XMM18, XMM18, XMM18;
VXORPS XMM19, XMM19, XMM19;
VXORPS XMM20, XMM20, XMM20

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 5.34
- Reference cycles: 1.93
- UOPS_EXECUTED.THREAD: 17.01
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.03
- UOPS_PORT_0: 5.33
- UOPS_PORT_1: 5.34
- UOPS_PORT_5: 5.34
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	62 f3 75 08 25 c2 02 	vpternlogd xmm0,xmm1,xmm2,0x2
   7:	62 f3 75 08 25 da 02 	vpternlogd xmm3,xmm1,xmm2,0x2
   e:	62 f3 75 08 25 e2 02 	vpternlogd xmm4,xmm1,xmm2,0x2
  15:	62 f3 75 08 25 ea 02 	vpternlogd xmm5,xmm1,xmm2,0x2
  1c:	62 f3 75 08 25 f2 02 	vpternlogd xmm6,xmm1,xmm2,0x2
  23:	62 f3 75 08 25 fa 02 	vpternlogd xmm7,xmm1,xmm2,0x2
  2a:	62 73 75 08 25 c2 02 	vpternlogd xmm8,xmm1,xmm2,0x2
  31:	62 73 75 08 25 ca 02 	vpternlogd xmm9,xmm1,xmm2,0x2
  38:	62 73 75 08 25 d2 02 	vpternlogd xmm10,xmm1,xmm2,0x2
  3f:	62 73 75 08 25 da 02 	vpternlogd xmm11,xmm1,xmm2,0x2
  46:	62 73 75 08 25 e2 02 	vpternlogd xmm12,xmm1,xmm2,0x2
  4d:	62 e3 75 08 25 c2 02 	vpternlogd xmm16,xmm1,xmm2,0x2
  54:	62 e3 75 08 25 ca 02 	vpternlogd xmm17,xmm1,xmm2,0x2
  5b:	62 e3 75 08 25 d2 02 	vpternlogd xmm18,xmm1,xmm2,0x2
  62:	62 e3 75 08 25 da 02 	vpternlogd xmm19,xmm1,xmm2,0x2
  69:	62 e3 75 08 25 e2 02 	vpternlogd xmm20,xmm1,xmm2,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3;
VXORPS XMM4, XMM4, XMM4;
VXORPS XMM5, XMM5, XMM5;
VXORPS XMM6, XMM6, XMM6;
VXORPS XMM7, XMM7, XMM7;
VXORPS XMM8, XMM8, XMM8;
VXORPS XMM9, XMM9, XMM9;
VXORPS XMM10, XMM10, XMM10;
VXORPS XMM11, XMM11, XMM11;
VXORPS XMM12, XMM12, XMM12;
VXORPS XMM16, XMM16, XMM16;
VXORPS XMM17, XMM17, XMM17;
VXORPS XMM18, XMM18, XMM18;
VXORPS XMM19, XMM19, XMM19;
VXORPS XMM20, XMM20, XMM20

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 5.35
- Reference cycles: 1.93
- UOPS_EXECUTED.THREAD: 16.1
- RETIRE_SLOTS: 16.11
- UOPS_MITE: 0.14
- UOPS_MS: 0.02
- UOPS_PORT_0: 5.33
- UOPS_PORT_1: 5.33
- UOPS_PORT_5: 5.33
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.05

With the same register for for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	62 f3 7d 08 25 c0 02 	vpternlogd xmm0,xmm0,xmm0,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.33
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.33
- UOPS_PORT_1: 0.34
- UOPS_PORT_5: 0.34
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	62 f3 7d 08 25 c0 02 	vpternlogd xmm0,xmm0,xmm0,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 0.33
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.33
- UOPS_PORT_1: 0.33
- UOPS_PORT_5: 0.34
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 f3 7d 08 25 c0 02 	vpternlogd xmm0,xmm0,xmm0,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 0.33
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.33
- UOPS_PORT_1: 0.33
- UOPS_PORT_5: 0.34
- UOPS_PORT_6: 0.01
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 f3 7d 08 25 c0 02 	vpternlogd xmm0,xmm0,xmm0,0x2
   7:	62 f3 75 08 25 c9 02 	vpternlogd xmm1,xmm1,xmm1,0x2
   e:	62 f3 6d 08 25 d2 02 	vpternlogd xmm2,xmm2,xmm2,0x2
  15:	62 f3 65 08 25 db 02 	vpternlogd xmm3,xmm3,xmm3,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 1.75
- Reference cycles: 0.62
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.25
- UOPS_PORT_1: 1.37
- UOPS_PORT_5: 1.38
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.75

With loop_count=1000 and unroll_count=2

Code:

   0:	62 f3 7d 08 25 c0 02 	vpternlogd xmm0,xmm0,xmm0,0x2
   7:	62 f3 75 08 25 c9 02 	vpternlogd xmm1,xmm1,xmm1,0x2
   e:	62 f3 6d 08 25 d2 02 	vpternlogd xmm2,xmm2,xmm2,0x2
  15:	62 f3 65 08 25 db 02 	vpternlogd xmm3,xmm3,xmm3,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 1.53
- Reference cycles: 0.5
- UOPS_EXECUTED.THREAD: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.01
- UOPS_PORT_0: 1.32
- UOPS_PORT_1: 1.33
- UOPS_PORT_5: 1.35
- UOPS_PORT_6: 0.5
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	62 f3 7d 08 25 c0 02 	vpternlogd xmm0,xmm0,xmm0,0x2
   7:	62 f3 75 08 25 c9 02 	vpternlogd xmm1,xmm1,xmm1,0x2
   e:	62 f3 6d 08 25 d2 02 	vpternlogd xmm2,xmm2,xmm2,0x2
  15:	62 f3 65 08 25 db 02 	vpternlogd xmm3,xmm3,xmm3,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 1.5
- Reference cycles: 0.5
- UOPS_EXECUTED.THREAD: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.01
- UOPS_PORT_0: 1.32
- UOPS_PORT_1: 1.34
- UOPS_PORT_5: 1.35
- UOPS_PORT_6: 0.05
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f3 7d 08 25 c0 02 	vpternlogd xmm0,xmm0,xmm0,0x2
   7:	62 f3 75 08 25 c9 02 	vpternlogd xmm1,xmm1,xmm1,0x2
   e:	62 f3 6d 08 25 d2 02 	vpternlogd xmm2,xmm2,xmm2,0x2
  15:	62 f3 65 08 25 db 02 	vpternlogd xmm3,xmm3,xmm3,0x2
  1c:	62 f3 5d 08 25 e4 02 	vpternlogd xmm4,xmm4,xmm4,0x2
  23:	62 f3 55 08 25 ed 02 	vpternlogd xmm5,xmm5,xmm5,0x2
  2a:	62 f3 4d 08 25 f6 02 	vpternlogd xmm6,xmm6,xmm6,0x2
  31:	62 f3 45 08 25 ff 02 	vpternlogd xmm7,xmm7,xmm7,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3;
VXORPS XMM4, XMM4, XMM4;
VXORPS XMM5, XMM5, XMM5;
VXORPS XMM6, XMM6, XMM6;
VXORPS XMM7, XMM7, XMM7

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 3.5
- Reference cycles: 1.19
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.51
- UOPS_PORT_1: 2.73
- UOPS_PORT_5: 2.76
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 3.5

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f3 7d 08 25 c0 02 	vpternlogd xmm0,xmm0,xmm0,0x2
   7:	62 f3 75 08 25 c9 02 	vpternlogd xmm1,xmm1,xmm1,0x2
   e:	62 f3 6d 08 25 d2 02 	vpternlogd xmm2,xmm2,xmm2,0x2
  15:	62 f3 65 08 25 db 02 	vpternlogd xmm3,xmm3,xmm3,0x2
  1c:	62 f3 5d 08 25 e4 02 	vpternlogd xmm4,xmm4,xmm4,0x2
  23:	62 f3 55 08 25 ed 02 	vpternlogd xmm5,xmm5,xmm5,0x2
  2a:	62 f3 4d 08 25 f6 02 	vpternlogd xmm6,xmm6,xmm6,0x2
  31:	62 f3 45 08 25 ff 02 	vpternlogd xmm7,xmm7,xmm7,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3;
VXORPS XMM4, XMM4, XMM4;
VXORPS XMM5, XMM5, XMM5;
VXORPS XMM6, XMM6, XMM6;
VXORPS XMM7, XMM7, XMM7

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 2.68
- Reference cycles: 0.87
- UOPS_EXECUTED.THREAD: 9.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.02
- UOPS_PORT_0: 2.67
- UOPS_PORT_1: 2.67
- UOPS_PORT_5: 2.66
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	62 f3 7d 08 25 c0 02 	vpternlogd xmm0,xmm0,xmm0,0x2
   7:	62 f3 75 08 25 c9 02 	vpternlogd xmm1,xmm1,xmm1,0x2
   e:	62 f3 6d 08 25 d2 02 	vpternlogd xmm2,xmm2,xmm2,0x2
  15:	62 f3 65 08 25 db 02 	vpternlogd xmm3,xmm3,xmm3,0x2
  1c:	62 f3 5d 08 25 e4 02 	vpternlogd xmm4,xmm4,xmm4,0x2
  23:	62 f3 55 08 25 ed 02 	vpternlogd xmm5,xmm5,xmm5,0x2
  2a:	62 f3 4d 08 25 f6 02 	vpternlogd xmm6,xmm6,xmm6,0x2
  31:	62 f3 45 08 25 ff 02 	vpternlogd xmm7,xmm7,xmm7,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3;
VXORPS XMM4, XMM4, XMM4;
VXORPS XMM5, XMM5, XMM5;
VXORPS XMM6, XMM6, XMM6;
VXORPS XMM7, XMM7, XMM7

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 2.68
- Reference cycles: 0.88
- UOPS_EXECUTED.THREAD: 8.11
- RETIRE_SLOTS: 8.11
- UOPS_MITE: 0.09
- UOPS_MS: 0.02
- UOPS_PORT_0: 2.67
- UOPS_PORT_1: 2.67
- UOPS_PORT_5: 2.66
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f3 7d 08 25 c0 02 	vpternlogd xmm0,xmm0,xmm0,0x2
   7:	62 f3 75 08 25 c9 02 	vpternlogd xmm1,xmm1,xmm1,0x2
   e:	62 f3 6d 08 25 d2 02 	vpternlogd xmm2,xmm2,xmm2,0x2
  15:	62 f3 65 08 25 db 02 	vpternlogd xmm3,xmm3,xmm3,0x2
  1c:	62 f3 5d 08 25 e4 02 	vpternlogd xmm4,xmm4,xmm4,0x2
  23:	62 f3 55 08 25 ed 02 	vpternlogd xmm5,xmm5,xmm5,0x2
  2a:	62 f3 4d 08 25 f6 02 	vpternlogd xmm6,xmm6,xmm6,0x2
  31:	62 f3 45 08 25 ff 02 	vpternlogd xmm7,xmm7,xmm7,0x2
  38:	62 53 3d 08 25 c0 02 	vpternlogd xmm8,xmm8,xmm8,0x2
  3f:	62 53 35 08 25 c9 02 	vpternlogd xmm9,xmm9,xmm9,0x2
  46:	62 53 2d 08 25 d2 02 	vpternlogd xmm10,xmm10,xmm10,0x2
  4d:	62 53 25 08 25 db 02 	vpternlogd xmm11,xmm11,xmm11,0x2
  54:	62 53 1d 08 25 e4 02 	vpternlogd xmm12,xmm12,xmm12,0x2
  5b:	62 a3 7d 00 25 c0 02 	vpternlogd xmm16,xmm16,xmm16,0x2
  62:	62 a3 75 00 25 c9 02 	vpternlogd xmm17,xmm17,xmm17,0x2
  69:	62 a3 6d 00 25 d2 02 	vpternlogd xmm18,xmm18,xmm18,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3;
VXORPS XMM4, XMM4, XMM4;
VXORPS XMM5, XMM5, XMM5;
VXORPS XMM6, XMM6, XMM6;
VXORPS XMM7, XMM7, XMM7;
VXORPS XMM8, XMM8, XMM8;
VXORPS XMM9, XMM9, XMM9;
VXORPS XMM10, XMM10, XMM10;
VXORPS XMM11, XMM11, XMM11;
VXORPS XMM12, XMM12, XMM12;
VXORPS XMM16, XMM16, XMM16;
VXORPS XMM17, XMM17, XMM17;
VXORPS XMM18, XMM18, XMM18

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 7.0
- Reference cycles: 2.17
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 5.0
- UOPS_PORT_1: 5.5
- UOPS_PORT_5: 5.5
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 7.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f3 7d 08 25 c0 02 	vpternlogd xmm0,xmm0,xmm0,0x2
   7:	62 f3 75 08 25 c9 02 	vpternlogd xmm1,xmm1,xmm1,0x2
   e:	62 f3 6d 08 25 d2 02 	vpternlogd xmm2,xmm2,xmm2,0x2
  15:	62 f3 65 08 25 db 02 	vpternlogd xmm3,xmm3,xmm3,0x2
  1c:	62 f3 5d 08 25 e4 02 	vpternlogd xmm4,xmm4,xmm4,0x2
  23:	62 f3 55 08 25 ed 02 	vpternlogd xmm5,xmm5,xmm5,0x2
  2a:	62 f3 4d 08 25 f6 02 	vpternlogd xmm6,xmm6,xmm6,0x2
  31:	62 f3 45 08 25 ff 02 	vpternlogd xmm7,xmm7,xmm7,0x2
  38:	62 53 3d 08 25 c0 02 	vpternlogd xmm8,xmm8,xmm8,0x2
  3f:	62 53 35 08 25 c9 02 	vpternlogd xmm9,xmm9,xmm9,0x2
  46:	62 53 2d 08 25 d2 02 	vpternlogd xmm10,xmm10,xmm10,0x2
  4d:	62 53 25 08 25 db 02 	vpternlogd xmm11,xmm11,xmm11,0x2
  54:	62 53 1d 08 25 e4 02 	vpternlogd xmm12,xmm12,xmm12,0x2
  5b:	62 a3 7d 00 25 c0 02 	vpternlogd xmm16,xmm16,xmm16,0x2
  62:	62 a3 75 00 25 c9 02 	vpternlogd xmm17,xmm17,xmm17,0x2
  69:	62 a3 6d 00 25 d2 02 	vpternlogd xmm18,xmm18,xmm18,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3;
VXORPS XMM4, XMM4, XMM4;
VXORPS XMM5, XMM5, XMM5;
VXORPS XMM6, XMM6, XMM6;
VXORPS XMM7, XMM7, XMM7;
VXORPS XMM8, XMM8, XMM8;
VXORPS XMM9, XMM9, XMM9;
VXORPS XMM10, XMM10, XMM10;
VXORPS XMM11, XMM11, XMM11;
VXORPS XMM12, XMM12, XMM12;
VXORPS XMM16, XMM16, XMM16;
VXORPS XMM17, XMM17, XMM17;
VXORPS XMM18, XMM18, XMM18

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 5.34
- Reference cycles: 1.79
- UOPS_EXECUTED.THREAD: 17.0
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.03
- UOPS_PORT_0: 5.33
- UOPS_PORT_1: 5.33
- UOPS_PORT_5: 5.33
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	62 f3 7d 08 25 c0 02 	vpternlogd xmm0,xmm0,xmm0,0x2
   7:	62 f3 75 08 25 c9 02 	vpternlogd xmm1,xmm1,xmm1,0x2
   e:	62 f3 6d 08 25 d2 02 	vpternlogd xmm2,xmm2,xmm2,0x2
  15:	62 f3 65 08 25 db 02 	vpternlogd xmm3,xmm3,xmm3,0x2
  1c:	62 f3 5d 08 25 e4 02 	vpternlogd xmm4,xmm4,xmm4,0x2
  23:	62 f3 55 08 25 ed 02 	vpternlogd xmm5,xmm5,xmm5,0x2
  2a:	62 f3 4d 08 25 f6 02 	vpternlogd xmm6,xmm6,xmm6,0x2
  31:	62 f3 45 08 25 ff 02 	vpternlogd xmm7,xmm7,xmm7,0x2
  38:	62 53 3d 08 25 c0 02 	vpternlogd xmm8,xmm8,xmm8,0x2
  3f:	62 53 35 08 25 c9 02 	vpternlogd xmm9,xmm9,xmm9,0x2
  46:	62 53 2d 08 25 d2 02 	vpternlogd xmm10,xmm10,xmm10,0x2
  4d:	62 53 25 08 25 db 02 	vpternlogd xmm11,xmm11,xmm11,0x2
  54:	62 53 1d 08 25 e4 02 	vpternlogd xmm12,xmm12,xmm12,0x2
  5b:	62 a3 7d 00 25 c0 02 	vpternlogd xmm16,xmm16,xmm16,0x2
  62:	62 a3 75 00 25 c9 02 	vpternlogd xmm17,xmm17,xmm17,0x2
  69:	62 a3 6d 00 25 d2 02 	vpternlogd xmm18,xmm18,xmm18,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3;
VXORPS XMM4, XMM4, XMM4;
VXORPS XMM5, XMM5, XMM5;
VXORPS XMM6, XMM6, XMM6;
VXORPS XMM7, XMM7, XMM7;
VXORPS XMM8, XMM8, XMM8;
VXORPS XMM9, XMM9, XMM9;
VXORPS XMM10, XMM10, XMM10;
VXORPS XMM11, XMM11, XMM11;
VXORPS XMM12, XMM12, XMM12;
VXORPS XMM16, XMM16, XMM16;
VXORPS XMM17, XMM17, XMM17;
VXORPS XMM18, XMM18, XMM18

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 5.35
- Reference cycles: 1.76
- UOPS_EXECUTED.THREAD: 16.1
- RETIRE_SLOTS: 16.11
- UOPS_MITE: 0.16
- UOPS_MS: 0.02
- UOPS_PORT_0: 5.33
- UOPS_PORT_1: 5.33
- UOPS_PORT_5: 5.33
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.05

VPTERNLOGD (XMM, XMM, XMM, I8) - Throughput and Uops

With different registers for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With the same register for for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10