VPADDD (ZMM, ZMM, ZMM)

With unroll_count=500 and no inner loop

Code:

   0:	62 f1 75 48 fe c2    	vpaddd zmm0,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 0.5
- Reference cycles: 0.19
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	62 f1 75 48 fe c2    	vpaddd zmm0,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 0.5
- Reference cycles: 0.17
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 f1 75 48 fe c2    	vpaddd zmm0,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 0.5
- Reference cycles: 0.17
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.01
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 f1 75 48 fe c2    	vpaddd zmm0,zmm1,zmm2
   6:	62 f1 75 48 fe da    	vpaddd zmm3,zmm1,zmm2
   c:	62 f1 75 48 fe e2    	vpaddd zmm4,zmm1,zmm2
  12:	62 f1 75 48 fe ea    	vpaddd zmm5,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 2.0
- Reference cycles: 0.75
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 3.99
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 0.02
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	62 f1 75 48 fe c2    	vpaddd zmm0,zmm1,zmm2
   6:	62 f1 75 48 fe da    	vpaddd zmm3,zmm1,zmm2
   c:	62 f1 75 48 fe e2    	vpaddd zmm4,zmm1,zmm2
  12:	62 f1 75 48 fe ea    	vpaddd zmm5,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 2.0
- Reference cycles: 0.68
- UOPS_EXECUTED.THREAD: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.01
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	62 f1 75 48 fe c2    	vpaddd zmm0,zmm1,zmm2
   6:	62 f1 75 48 fe da    	vpaddd zmm3,zmm1,zmm2
   c:	62 f1 75 48 fe e2    	vpaddd zmm4,zmm1,zmm2
  12:	62 f1 75 48 fe ea    	vpaddd zmm5,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 2.0
- Reference cycles: 0.68
- UOPS_EXECUTED.THREAD: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.01
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f1 75 48 fe c2    	vpaddd zmm0,zmm1,zmm2
   6:	62 f1 75 48 fe da    	vpaddd zmm3,zmm1,zmm2
   c:	62 f1 75 48 fe e2    	vpaddd zmm4,zmm1,zmm2
  12:	62 f1 75 48 fe ea    	vpaddd zmm5,zmm1,zmm2
  18:	62 f1 75 48 fe f2    	vpaddd zmm6,zmm1,zmm2
  1e:	62 f1 75 48 fe fa    	vpaddd zmm7,zmm1,zmm2
  24:	62 71 75 48 fe c2    	vpaddd zmm8,zmm1,zmm2
  2a:	62 71 75 48 fe ca    	vpaddd zmm9,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 4.0
- Reference cycles: 1.5
- UOPS_EXECUTED.THREAD: 8.01
- RETIRE_SLOTS: 7.96
- UOPS_MITE: 7.99
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.01
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.01

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f1 75 48 fe c2    	vpaddd zmm0,zmm1,zmm2
   6:	62 f1 75 48 fe da    	vpaddd zmm3,zmm1,zmm2
   c:	62 f1 75 48 fe e2    	vpaddd zmm4,zmm1,zmm2
  12:	62 f1 75 48 fe ea    	vpaddd zmm5,zmm1,zmm2
  18:	62 f1 75 48 fe f2    	vpaddd zmm6,zmm1,zmm2
  1e:	62 f1 75 48 fe fa    	vpaddd zmm7,zmm1,zmm2
  24:	62 71 75 48 fe c2    	vpaddd zmm8,zmm1,zmm2
  2a:	62 71 75 48 fe ca    	vpaddd zmm9,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 4.01
- Reference cycles: 1.37
- UOPS_EXECUTED.THREAD: 9.01
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.03
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	62 f1 75 48 fe c2    	vpaddd zmm0,zmm1,zmm2
   6:	62 f1 75 48 fe da    	vpaddd zmm3,zmm1,zmm2
   c:	62 f1 75 48 fe e2    	vpaddd zmm4,zmm1,zmm2
  12:	62 f1 75 48 fe ea    	vpaddd zmm5,zmm1,zmm2
  18:	62 f1 75 48 fe f2    	vpaddd zmm6,zmm1,zmm2
  1e:	62 f1 75 48 fe fa    	vpaddd zmm7,zmm1,zmm2
  24:	62 71 75 48 fe c2    	vpaddd zmm8,zmm1,zmm2
  2a:	62 71 75 48 fe ca    	vpaddd zmm9,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 4.01
- Reference cycles: 1.37
- UOPS_EXECUTED.THREAD: 8.1
- RETIRE_SLOTS: 8.11
- UOPS_MITE: 0.08
- UOPS_MS: 0.02
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f1 75 48 fe c2    	vpaddd zmm0,zmm1,zmm2
   6:	62 f1 75 48 fe da    	vpaddd zmm3,zmm1,zmm2
   c:	62 f1 75 48 fe e2    	vpaddd zmm4,zmm1,zmm2
  12:	62 f1 75 48 fe ea    	vpaddd zmm5,zmm1,zmm2
  18:	62 f1 75 48 fe f2    	vpaddd zmm6,zmm1,zmm2
  1e:	62 f1 75 48 fe fa    	vpaddd zmm7,zmm1,zmm2
  24:	62 71 75 48 fe c2    	vpaddd zmm8,zmm1,zmm2
  2a:	62 71 75 48 fe ca    	vpaddd zmm9,zmm1,zmm2
  30:	62 71 75 48 fe d2    	vpaddd zmm10,zmm1,zmm2
  36:	62 71 75 48 fe da    	vpaddd zmm11,zmm1,zmm2
  3c:	62 71 75 48 fe e2    	vpaddd zmm12,zmm1,zmm2
  42:	62 e1 75 48 fe c2    	vpaddd zmm16,zmm1,zmm2
  48:	62 e1 75 48 fe ca    	vpaddd zmm17,zmm1,zmm2
  4e:	62 e1 75 48 fe d2    	vpaddd zmm18,zmm1,zmm2
  54:	62 e1 75 48 fe da    	vpaddd zmm19,zmm1,zmm2
  5a:	62 e1 75 48 fe e2    	vpaddd zmm20,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 8.0
- Reference cycles: 2.79
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f1 75 48 fe c2    	vpaddd zmm0,zmm1,zmm2
   6:	62 f1 75 48 fe da    	vpaddd zmm3,zmm1,zmm2
   c:	62 f1 75 48 fe e2    	vpaddd zmm4,zmm1,zmm2
  12:	62 f1 75 48 fe ea    	vpaddd zmm5,zmm1,zmm2
  18:	62 f1 75 48 fe f2    	vpaddd zmm6,zmm1,zmm2
  1e:	62 f1 75 48 fe fa    	vpaddd zmm7,zmm1,zmm2
  24:	62 71 75 48 fe c2    	vpaddd zmm8,zmm1,zmm2
  2a:	62 71 75 48 fe ca    	vpaddd zmm9,zmm1,zmm2
  30:	62 71 75 48 fe d2    	vpaddd zmm10,zmm1,zmm2
  36:	62 71 75 48 fe da    	vpaddd zmm11,zmm1,zmm2
  3c:	62 71 75 48 fe e2    	vpaddd zmm12,zmm1,zmm2
  42:	62 e1 75 48 fe c2    	vpaddd zmm16,zmm1,zmm2
  48:	62 e1 75 48 fe ca    	vpaddd zmm17,zmm1,zmm2
  4e:	62 e1 75 48 fe d2    	vpaddd zmm18,zmm1,zmm2
  54:	62 e1 75 48 fe da    	vpaddd zmm19,zmm1,zmm2
  5a:	62 e1 75 48 fe e2    	vpaddd zmm20,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 8.01
- Reference cycles: 2.72
- UOPS_EXECUTED.THREAD: 17.0
- RETIRE_SLOTS: 17.01
- UOPS_MITE: 0.02
- UOPS_MS: 0.02
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	62 f1 75 48 fe c2    	vpaddd zmm0,zmm1,zmm2
   6:	62 f1 75 48 fe da    	vpaddd zmm3,zmm1,zmm2
   c:	62 f1 75 48 fe e2    	vpaddd zmm4,zmm1,zmm2
  12:	62 f1 75 48 fe ea    	vpaddd zmm5,zmm1,zmm2
  18:	62 f1 75 48 fe f2    	vpaddd zmm6,zmm1,zmm2
  1e:	62 f1 75 48 fe fa    	vpaddd zmm7,zmm1,zmm2
  24:	62 71 75 48 fe c2    	vpaddd zmm8,zmm1,zmm2
  2a:	62 71 75 48 fe ca    	vpaddd zmm9,zmm1,zmm2
  30:	62 71 75 48 fe d2    	vpaddd zmm10,zmm1,zmm2
  36:	62 71 75 48 fe da    	vpaddd zmm11,zmm1,zmm2
  3c:	62 71 75 48 fe e2    	vpaddd zmm12,zmm1,zmm2
  42:	62 e1 75 48 fe c2    	vpaddd zmm16,zmm1,zmm2
  48:	62 e1 75 48 fe ca    	vpaddd zmm17,zmm1,zmm2
  4e:	62 e1 75 48 fe d2    	vpaddd zmm18,zmm1,zmm2
  54:	62 e1 75 48 fe da    	vpaddd zmm19,zmm1,zmm2
  5a:	62 e1 75 48 fe e2    	vpaddd zmm20,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 8.01
- Reference cycles: 2.73
- UOPS_EXECUTED.THREAD: 16.1
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.17
- UOPS_MS: 0.02
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.05

With the same register for for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	62 f1 7d 48 fe c0    	vpaddd zmm0,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.36
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	62 f1 7d 48 fe c0    	vpaddd zmm0,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 0.34
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 f1 7d 48 fe c0    	vpaddd zmm0,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 0.34
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.01
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 f1 7d 48 fe c0    	vpaddd zmm0,zmm0,zmm0
   6:	62 f1 75 48 fe c9    	vpaddd zmm1,zmm1,zmm1
   c:	62 f1 6d 48 fe d2    	vpaddd zmm2,zmm2,zmm2
  12:	62 f1 65 48 fe db    	vpaddd zmm3,zmm3,zmm3

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 2.0
- Reference cycles: 0.78
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 3.98
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 2.01
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	62 f1 7d 48 fe c0    	vpaddd zmm0,zmm0,zmm0
   6:	62 f1 75 48 fe c9    	vpaddd zmm1,zmm1,zmm1
   c:	62 f1 6d 48 fe d2    	vpaddd zmm2,zmm2,zmm2
  12:	62 f1 65 48 fe db    	vpaddd zmm3,zmm3,zmm3

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 2.0
- Reference cycles: 0.68
- UOPS_EXECUTED.THREAD: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.01
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	62 f1 7d 48 fe c0    	vpaddd zmm0,zmm0,zmm0
   6:	62 f1 75 48 fe c9    	vpaddd zmm1,zmm1,zmm1
   c:	62 f1 6d 48 fe d2    	vpaddd zmm2,zmm2,zmm2
  12:	62 f1 65 48 fe db    	vpaddd zmm3,zmm3,zmm3

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 2.01
- Reference cycles: 0.68
- UOPS_EXECUTED.THREAD: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.01
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f1 7d 48 fe c0    	vpaddd zmm0,zmm0,zmm0
   6:	62 f1 75 48 fe c9    	vpaddd zmm1,zmm1,zmm1
   c:	62 f1 6d 48 fe d2    	vpaddd zmm2,zmm2,zmm2
  12:	62 f1 65 48 fe db    	vpaddd zmm3,zmm3,zmm3
  18:	62 f1 5d 48 fe e4    	vpaddd zmm4,zmm4,zmm4
  1e:	62 f1 55 48 fe ed    	vpaddd zmm5,zmm5,zmm5
  24:	62 f1 4d 48 fe f6    	vpaddd zmm6,zmm6,zmm6
  2a:	62 f1 45 48 fe ff    	vpaddd zmm7,zmm7,zmm7

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 4.0
- Reference cycles: 1.29
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.03
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.99

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f1 7d 48 fe c0    	vpaddd zmm0,zmm0,zmm0
   6:	62 f1 75 48 fe c9    	vpaddd zmm1,zmm1,zmm1
   c:	62 f1 6d 48 fe d2    	vpaddd zmm2,zmm2,zmm2
  12:	62 f1 65 48 fe db    	vpaddd zmm3,zmm3,zmm3
  18:	62 f1 5d 48 fe e4    	vpaddd zmm4,zmm4,zmm4
  1e:	62 f1 55 48 fe ed    	vpaddd zmm5,zmm5,zmm5
  24:	62 f1 4d 48 fe f6    	vpaddd zmm6,zmm6,zmm6
  2a:	62 f1 45 48 fe ff    	vpaddd zmm7,zmm7,zmm7

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 4.01
- Reference cycles: 1.36
- UOPS_EXECUTED.THREAD: 9.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.03
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	62 f1 7d 48 fe c0    	vpaddd zmm0,zmm0,zmm0
   6:	62 f1 75 48 fe c9    	vpaddd zmm1,zmm1,zmm1
   c:	62 f1 6d 48 fe d2    	vpaddd zmm2,zmm2,zmm2
  12:	62 f1 65 48 fe db    	vpaddd zmm3,zmm3,zmm3
  18:	62 f1 5d 48 fe e4    	vpaddd zmm4,zmm4,zmm4
  1e:	62 f1 55 48 fe ed    	vpaddd zmm5,zmm5,zmm5
  24:	62 f1 4d 48 fe f6    	vpaddd zmm6,zmm6,zmm6
  2a:	62 f1 45 48 fe ff    	vpaddd zmm7,zmm7,zmm7

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 4.01
- Reference cycles: 1.36
- UOPS_EXECUTED.THREAD: 8.1
- RETIRE_SLOTS: 8.11
- UOPS_MITE: 0.06
- UOPS_MS: 0.02
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f1 7d 48 fe c0    	vpaddd zmm0,zmm0,zmm0
   6:	62 f1 75 48 fe c9    	vpaddd zmm1,zmm1,zmm1
   c:	62 f1 6d 48 fe d2    	vpaddd zmm2,zmm2,zmm2
  12:	62 f1 65 48 fe db    	vpaddd zmm3,zmm3,zmm3
  18:	62 f1 5d 48 fe e4    	vpaddd zmm4,zmm4,zmm4
  1e:	62 f1 55 48 fe ed    	vpaddd zmm5,zmm5,zmm5
  24:	62 f1 4d 48 fe f6    	vpaddd zmm6,zmm6,zmm6
  2a:	62 f1 45 48 fe ff    	vpaddd zmm7,zmm7,zmm7
  30:	62 51 3d 48 fe c0    	vpaddd zmm8,zmm8,zmm8
  36:	62 51 35 48 fe c9    	vpaddd zmm9,zmm9,zmm9
  3c:	62 51 2d 48 fe d2    	vpaddd zmm10,zmm10,zmm10
  42:	62 51 25 48 fe db    	vpaddd zmm11,zmm11,zmm11
  48:	62 51 1d 48 fe e4    	vpaddd zmm12,zmm12,zmm12
  4e:	62 a1 7d 40 fe c0    	vpaddd zmm16,zmm16,zmm16
  54:	62 a1 75 40 fe c9    	vpaddd zmm17,zmm17,zmm17
  5a:	62 a1 6d 40 fe d2    	vpaddd zmm18,zmm18,zmm18

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7;
VXORPS ZMM8, ZMM8, ZMM8;
VXORPS ZMM9, ZMM9, ZMM9;
VXORPS ZMM10, ZMM10, ZMM10;
VXORPS ZMM11, ZMM11, ZMM11;
VXORPS ZMM12, ZMM12, ZMM12;
VXORPS ZMM16, ZMM16, ZMM16;
VXORPS ZMM17, ZMM17, ZMM17;
VXORPS ZMM18, ZMM18, ZMM18

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 8.0
- Reference cycles: 2.69
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 15.97
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.01
- UOPS_PORT_1: 0.02
- UOPS_PORT_5: 7.99
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 3.98

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f1 7d 48 fe c0    	vpaddd zmm0,zmm0,zmm0
   6:	62 f1 75 48 fe c9    	vpaddd zmm1,zmm1,zmm1
   c:	62 f1 6d 48 fe d2    	vpaddd zmm2,zmm2,zmm2
  12:	62 f1 65 48 fe db    	vpaddd zmm3,zmm3,zmm3
  18:	62 f1 5d 48 fe e4    	vpaddd zmm4,zmm4,zmm4
  1e:	62 f1 55 48 fe ed    	vpaddd zmm5,zmm5,zmm5
  24:	62 f1 4d 48 fe f6    	vpaddd zmm6,zmm6,zmm6
  2a:	62 f1 45 48 fe ff    	vpaddd zmm7,zmm7,zmm7
  30:	62 51 3d 48 fe c0    	vpaddd zmm8,zmm8,zmm8
  36:	62 51 35 48 fe c9    	vpaddd zmm9,zmm9,zmm9
  3c:	62 51 2d 48 fe d2    	vpaddd zmm10,zmm10,zmm10
  42:	62 51 25 48 fe db    	vpaddd zmm11,zmm11,zmm11
  48:	62 51 1d 48 fe e4    	vpaddd zmm12,zmm12,zmm12
  4e:	62 a1 7d 40 fe c0    	vpaddd zmm16,zmm16,zmm16
  54:	62 a1 75 40 fe c9    	vpaddd zmm17,zmm17,zmm17
  5a:	62 a1 6d 40 fe d2    	vpaddd zmm18,zmm18,zmm18

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7;
VXORPS ZMM8, ZMM8, ZMM8;
VXORPS ZMM9, ZMM9, ZMM9;
VXORPS ZMM10, ZMM10, ZMM10;
VXORPS ZMM11, ZMM11, ZMM11;
VXORPS ZMM12, ZMM12, ZMM12;
VXORPS ZMM16, ZMM16, ZMM16;
VXORPS ZMM17, ZMM17, ZMM17;
VXORPS ZMM18, ZMM18, ZMM18

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 8.01
- Reference cycles: 2.73
- UOPS_EXECUTED.THREAD: 17.0
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.02
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	62 f1 7d 48 fe c0    	vpaddd zmm0,zmm0,zmm0
   6:	62 f1 75 48 fe c9    	vpaddd zmm1,zmm1,zmm1
   c:	62 f1 6d 48 fe d2    	vpaddd zmm2,zmm2,zmm2
  12:	62 f1 65 48 fe db    	vpaddd zmm3,zmm3,zmm3
  18:	62 f1 5d 48 fe e4    	vpaddd zmm4,zmm4,zmm4
  1e:	62 f1 55 48 fe ed    	vpaddd zmm5,zmm5,zmm5
  24:	62 f1 4d 48 fe f6    	vpaddd zmm6,zmm6,zmm6
  2a:	62 f1 45 48 fe ff    	vpaddd zmm7,zmm7,zmm7
  30:	62 51 3d 48 fe c0    	vpaddd zmm8,zmm8,zmm8
  36:	62 51 35 48 fe c9    	vpaddd zmm9,zmm9,zmm9
  3c:	62 51 2d 48 fe d2    	vpaddd zmm10,zmm10,zmm10
  42:	62 51 25 48 fe db    	vpaddd zmm11,zmm11,zmm11
  48:	62 51 1d 48 fe e4    	vpaddd zmm12,zmm12,zmm12
  4e:	62 a1 7d 40 fe c0    	vpaddd zmm16,zmm16,zmm16
  54:	62 a1 75 40 fe c9    	vpaddd zmm17,zmm17,zmm17
  5a:	62 a1 6d 40 fe d2    	vpaddd zmm18,zmm18,zmm18

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7;
VXORPS ZMM8, ZMM8, ZMM8;
VXORPS ZMM9, ZMM9, ZMM9;
VXORPS ZMM10, ZMM10, ZMM10;
VXORPS ZMM11, ZMM11, ZMM11;
VXORPS ZMM12, ZMM12, ZMM12;
VXORPS ZMM16, ZMM16, ZMM16;
VXORPS ZMM17, ZMM17, ZMM17;
VXORPS ZMM18, ZMM18, ZMM18

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 8.01
- Reference cycles: 2.73
- UOPS_EXECUTED.THREAD: 16.1
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.16
- UOPS_MS: 0.02
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.05

VPADDD (ZMM, ZMM, ZMM) - Throughput and Uops

With different registers for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With the same register for for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10