VMOVDQU8 (M128, K, XMM)

With unroll_count=500 and no inner loop

Code:

   0:	62 d1 7f 09 7f 06    	vmovdqu8 XMMWORD PTR [r14]{k1},xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 0.5
- Reference cycles: 0.13
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 0.97
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 1.0
- UOPS_PORT_78: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	62 d1 7f 09 7f 06    	vmovdqu8 XMMWORD PTR [r14]{k1},xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 0.5
- Reference cycles: 0.17
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 1.0
- UOPS_PORT_78: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 d1 7f 09 7f 06    	vmovdqu8 XMMWORD PTR [r14]{k1},xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 0.5
- Reference cycles: 0.16
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 1.0
- UOPS_PORT_78: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 d1 7f 09 7f 06    	vmovdqu8 XMMWORD PTR [r14]{k1},xmm0
   6:	62 d1 7f 09 7f 46 01 	vmovdqu8 XMMWORD PTR [r14+0x10]{k1},xmm0
   d:	62 d1 7f 09 7f 46 02 	vmovdqu8 XMMWORD PTR [r14+0x20]{k1},xmm0
  14:	62 d1 7f 09 7f 46 03 	vmovdqu8 XMMWORD PTR [r14+0x30]{k1},xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 2.0
- Reference cycles: 0.67
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 4.0
- UOPS_PORT_78: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	62 d1 7f 09 7f 06    	vmovdqu8 XMMWORD PTR [r14]{k1},xmm0
   6:	62 d1 7f 09 7f 46 01 	vmovdqu8 XMMWORD PTR [r14+0x10]{k1},xmm0
   d:	62 d1 7f 09 7f 46 02 	vmovdqu8 XMMWORD PTR [r14+0x20]{k1},xmm0
  14:	62 d1 7f 09 7f 46 03 	vmovdqu8 XMMWORD PTR [r14+0x30]{k1},xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 2.01
- Reference cycles: 0.68
- UOPS_EXECUTED.THREAD: 8.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.01
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 4.0
- UOPS_PORT_78: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	62 d1 7f 09 7f 06    	vmovdqu8 XMMWORD PTR [r14]{k1},xmm0
   6:	62 d1 7f 09 7f 46 01 	vmovdqu8 XMMWORD PTR [r14+0x10]{k1},xmm0
   d:	62 d1 7f 09 7f 46 02 	vmovdqu8 XMMWORD PTR [r14+0x20]{k1},xmm0
  14:	62 d1 7f 09 7f 46 03 	vmovdqu8 XMMWORD PTR [r14+0x30]{k1},xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 2.0
- Reference cycles: 0.65
- UOPS_EXECUTED.THREAD: 8.05
- RETIRE_SLOTS: 4.06
- UOPS_MITE: 0.04
- UOPS_MS: 0.01
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 4.0
- UOPS_PORT_78: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 d1 7f 09 7f 06    	vmovdqu8 XMMWORD PTR [r14]{k1},xmm0
   6:	62 d1 7f 09 7f 46 01 	vmovdqu8 XMMWORD PTR [r14+0x10]{k1},xmm0
   d:	62 d1 7f 09 7f 46 02 	vmovdqu8 XMMWORD PTR [r14+0x20]{k1},xmm0
  14:	62 d1 7f 09 7f 46 03 	vmovdqu8 XMMWORD PTR [r14+0x30]{k1},xmm0
  1b:	62 d1 7f 09 7f 46 04 	vmovdqu8 XMMWORD PTR [r14+0x40]{k1},xmm0
  22:	62 d1 7f 09 7f 46 05 	vmovdqu8 XMMWORD PTR [r14+0x50]{k1},xmm0
  29:	62 d1 7f 09 7f 46 06 	vmovdqu8 XMMWORD PTR [r14+0x60]{k1},xmm0
  30:	62 d1 7f 09 7f 46 07 	vmovdqu8 XMMWORD PTR [r14+0x70]{k1},xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 3.99
- Reference cycles: 1.34
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 7.84
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 8.0
- UOPS_PORT_78: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 d1 7f 09 7f 06    	vmovdqu8 XMMWORD PTR [r14]{k1},xmm0
   6:	62 d1 7f 09 7f 46 01 	vmovdqu8 XMMWORD PTR [r14+0x10]{k1},xmm0
   d:	62 d1 7f 09 7f 46 02 	vmovdqu8 XMMWORD PTR [r14+0x20]{k1},xmm0
  14:	62 d1 7f 09 7f 46 03 	vmovdqu8 XMMWORD PTR [r14+0x30]{k1},xmm0
  1b:	62 d1 7f 09 7f 46 04 	vmovdqu8 XMMWORD PTR [r14+0x40]{k1},xmm0
  22:	62 d1 7f 09 7f 46 05 	vmovdqu8 XMMWORD PTR [r14+0x50]{k1},xmm0
  29:	62 d1 7f 09 7f 46 06 	vmovdqu8 XMMWORD PTR [r14+0x60]{k1},xmm0
  30:	62 d1 7f 09 7f 46 07 	vmovdqu8 XMMWORD PTR [r14+0x70]{k1},xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 4.02
- Reference cycles: 1.33
- UOPS_EXECUTED.THREAD: 17.01
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.02
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 8.0
- UOPS_PORT_78: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	62 d1 7f 09 7f 06    	vmovdqu8 XMMWORD PTR [r14]{k1},xmm0
   6:	62 d1 7f 09 7f 46 01 	vmovdqu8 XMMWORD PTR [r14+0x10]{k1},xmm0
   d:	62 d1 7f 09 7f 46 02 	vmovdqu8 XMMWORD PTR [r14+0x20]{k1},xmm0
  14:	62 d1 7f 09 7f 46 03 	vmovdqu8 XMMWORD PTR [r14+0x30]{k1},xmm0
  1b:	62 d1 7f 09 7f 46 04 	vmovdqu8 XMMWORD PTR [r14+0x40]{k1},xmm0
  22:	62 d1 7f 09 7f 46 05 	vmovdqu8 XMMWORD PTR [r14+0x50]{k1},xmm0
  29:	62 d1 7f 09 7f 46 06 	vmovdqu8 XMMWORD PTR [r14+0x60]{k1},xmm0
  30:	62 d1 7f 09 7f 46 07 	vmovdqu8 XMMWORD PTR [r14+0x70]{k1},xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 4.01
- Reference cycles: 1.31
- UOPS_EXECUTED.THREAD: 16.1
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.07
- UOPS_MS: 0.02
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 8.0
- UOPS_PORT_78: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 d1 7f 09 7f 06    	vmovdqu8 XMMWORD PTR [r14]{k1},xmm0
   6:	62 d1 7f 09 7f 46 01 	vmovdqu8 XMMWORD PTR [r14+0x10]{k1},xmm0
   d:	62 d1 7f 09 7f 46 02 	vmovdqu8 XMMWORD PTR [r14+0x20]{k1},xmm0
  14:	62 d1 7f 09 7f 46 03 	vmovdqu8 XMMWORD PTR [r14+0x30]{k1},xmm0
  1b:	62 d1 7f 09 7f 46 04 	vmovdqu8 XMMWORD PTR [r14+0x40]{k1},xmm0
  22:	62 d1 7f 09 7f 46 05 	vmovdqu8 XMMWORD PTR [r14+0x50]{k1},xmm0
  29:	62 d1 7f 09 7f 46 06 	vmovdqu8 XMMWORD PTR [r14+0x60]{k1},xmm0
  30:	62 d1 7f 09 7f 46 07 	vmovdqu8 XMMWORD PTR [r14+0x70]{k1},xmm0
  37:	62 d1 7f 09 7f 46 08 	vmovdqu8 XMMWORD PTR [r14+0x80]{k1},xmm0
  3e:	62 d1 7f 09 7f 46 09 	vmovdqu8 XMMWORD PTR [r14+0x90]{k1},xmm0
  45:	62 d1 7f 09 7f 46 0a 	vmovdqu8 XMMWORD PTR [r14+0xa0]{k1},xmm0
  4c:	62 d1 7f 09 7f 46 0b 	vmovdqu8 XMMWORD PTR [r14+0xb0]{k1},xmm0
  53:	62 d1 7f 09 7f 46 0c 	vmovdqu8 XMMWORD PTR [r14+0xc0]{k1},xmm0
  5a:	62 d1 7f 09 7f 46 0d 	vmovdqu8 XMMWORD PTR [r14+0xd0]{k1},xmm0
  61:	62 d1 7f 09 7f 46 0e 	vmovdqu8 XMMWORD PTR [r14+0xe0]{k1},xmm0
  68:	62 d1 7f 09 7f 46 0f 	vmovdqu8 XMMWORD PTR [r14+0xf0]{k1},xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 8.0
- Reference cycles: 2.58
- UOPS_EXECUTED.THREAD: 32.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 15.84
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 16.0
- UOPS_PORT_78: 16.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 d1 7f 09 7f 06    	vmovdqu8 XMMWORD PTR [r14]{k1},xmm0
   6:	62 d1 7f 09 7f 46 01 	vmovdqu8 XMMWORD PTR [r14+0x10]{k1},xmm0
   d:	62 d1 7f 09 7f 46 02 	vmovdqu8 XMMWORD PTR [r14+0x20]{k1},xmm0
  14:	62 d1 7f 09 7f 46 03 	vmovdqu8 XMMWORD PTR [r14+0x30]{k1},xmm0
  1b:	62 d1 7f 09 7f 46 04 	vmovdqu8 XMMWORD PTR [r14+0x40]{k1},xmm0
  22:	62 d1 7f 09 7f 46 05 	vmovdqu8 XMMWORD PTR [r14+0x50]{k1},xmm0
  29:	62 d1 7f 09 7f 46 06 	vmovdqu8 XMMWORD PTR [r14+0x60]{k1},xmm0
  30:	62 d1 7f 09 7f 46 07 	vmovdqu8 XMMWORD PTR [r14+0x70]{k1},xmm0
  37:	62 d1 7f 09 7f 46 08 	vmovdqu8 XMMWORD PTR [r14+0x80]{k1},xmm0
  3e:	62 d1 7f 09 7f 46 09 	vmovdqu8 XMMWORD PTR [r14+0x90]{k1},xmm0
  45:	62 d1 7f 09 7f 46 0a 	vmovdqu8 XMMWORD PTR [r14+0xa0]{k1},xmm0
  4c:	62 d1 7f 09 7f 46 0b 	vmovdqu8 XMMWORD PTR [r14+0xb0]{k1},xmm0
  53:	62 d1 7f 09 7f 46 0c 	vmovdqu8 XMMWORD PTR [r14+0xc0]{k1},xmm0
  5a:	62 d1 7f 09 7f 46 0d 	vmovdqu8 XMMWORD PTR [r14+0xd0]{k1},xmm0
  61:	62 d1 7f 09 7f 46 0e 	vmovdqu8 XMMWORD PTR [r14+0xe0]{k1},xmm0
  68:	62 d1 7f 09 7f 46 0f 	vmovdqu8 XMMWORD PTR [r14+0xf0]{k1},xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 8.02
- Reference cycles: 2.65
- UOPS_EXECUTED.THREAD: 33.01
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.03
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 16.0
- UOPS_PORT_78: 16.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	62 d1 7f 09 7f 06    	vmovdqu8 XMMWORD PTR [r14]{k1},xmm0
   6:	62 d1 7f 09 7f 46 01 	vmovdqu8 XMMWORD PTR [r14+0x10]{k1},xmm0
   d:	62 d1 7f 09 7f 46 02 	vmovdqu8 XMMWORD PTR [r14+0x20]{k1},xmm0
  14:	62 d1 7f 09 7f 46 03 	vmovdqu8 XMMWORD PTR [r14+0x30]{k1},xmm0
  1b:	62 d1 7f 09 7f 46 04 	vmovdqu8 XMMWORD PTR [r14+0x40]{k1},xmm0
  22:	62 d1 7f 09 7f 46 05 	vmovdqu8 XMMWORD PTR [r14+0x50]{k1},xmm0
  29:	62 d1 7f 09 7f 46 06 	vmovdqu8 XMMWORD PTR [r14+0x60]{k1},xmm0
  30:	62 d1 7f 09 7f 46 07 	vmovdqu8 XMMWORD PTR [r14+0x70]{k1},xmm0
  37:	62 d1 7f 09 7f 46 08 	vmovdqu8 XMMWORD PTR [r14+0x80]{k1},xmm0
  3e:	62 d1 7f 09 7f 46 09 	vmovdqu8 XMMWORD PTR [r14+0x90]{k1},xmm0
  45:	62 d1 7f 09 7f 46 0a 	vmovdqu8 XMMWORD PTR [r14+0xa0]{k1},xmm0
  4c:	62 d1 7f 09 7f 46 0b 	vmovdqu8 XMMWORD PTR [r14+0xb0]{k1},xmm0
  53:	62 d1 7f 09 7f 46 0c 	vmovdqu8 XMMWORD PTR [r14+0xc0]{k1},xmm0
  5a:	62 d1 7f 09 7f 46 0d 	vmovdqu8 XMMWORD PTR [r14+0xd0]{k1},xmm0
  61:	62 d1 7f 09 7f 46 0e 	vmovdqu8 XMMWORD PTR [r14+0xe0]{k1},xmm0
  68:	62 d1 7f 09 7f 46 0f 	vmovdqu8 XMMWORD PTR [r14+0xf0]{k1},xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 8.01
- Reference cycles: 2.66
- UOPS_EXECUTED.THREAD: 32.1
- RETIRE_SLOTS: 16.09
- UOPS_MITE: 0.17
- UOPS_MS: 0.02
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 16.0
- UOPS_PORT_78: 16.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	62 91 7f 09 7f 04 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1]{k1},xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 0.5
- Reference cycles: 0.17
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 1.0
- UOPS_PORT_78: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	62 91 7f 09 7f 04 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1]{k1},xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 0.5
- Reference cycles: 0.17
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 1.0
- UOPS_PORT_78: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 91 7f 09 7f 04 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1]{k1},xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 0.5
- Reference cycles: 0.17
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 1.0
- UOPS_PORT_78: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 91 7f 09 7f 04 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1]{k1},xmm0
   7:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x10]{k1},xmm0
   e:	01 
   f:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x20]{k1},xmm0
  16:	02 
  17:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x30]{k1},xmm0
  1e:	03

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 2.0
- Reference cycles: 0.7
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 4.0
- UOPS_PORT_78: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	62 91 7f 09 7f 04 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1]{k1},xmm0
   7:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x10]{k1},xmm0
   e:	01 
   f:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x20]{k1},xmm0
  16:	02 
  17:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x30]{k1},xmm0
  1e:	03

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 2.01
- Reference cycles: 0.67
- UOPS_EXECUTED.THREAD: 8.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.01
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 4.0
- UOPS_PORT_78: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	62 91 7f 09 7f 04 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1]{k1},xmm0
   7:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x10]{k1},xmm0
   e:	01 
   f:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x20]{k1},xmm0
  16:	02 
  17:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x30]{k1},xmm0
  1e:	03

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 2.0
- Reference cycles: 0.66
- UOPS_EXECUTED.THREAD: 8.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.03
- UOPS_MS: 0.01
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 4.0
- UOPS_PORT_78: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 91 7f 09 7f 04 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1]{k1},xmm0
   7:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x10]{k1},xmm0
   e:	01 
   f:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x20]{k1},xmm0
  16:	02 
  17:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x30]{k1},xmm0
  1e:	03 
  1f:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x40]{k1},xmm0
  26:	04 
  27:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x50]{k1},xmm0
  2e:	05 
  2f:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x60]{k1},xmm0
  36:	06 
  37:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x70]{k1},xmm0
  3e:	07

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 4.0
- Reference cycles: 1.34
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 7.84
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 8.0
- UOPS_PORT_78: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 91 7f 09 7f 04 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1]{k1},xmm0
   7:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x10]{k1},xmm0
   e:	01 
   f:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x20]{k1},xmm0
  16:	02 
  17:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x30]{k1},xmm0
  1e:	03 
  1f:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x40]{k1},xmm0
  26:	04 
  27:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x50]{k1},xmm0
  2e:	05 
  2f:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x60]{k1},xmm0
  36:	06 
  37:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x70]{k1},xmm0
  3e:	07

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 4.02
- Reference cycles: 1.35
- UOPS_EXECUTED.THREAD: 17.01
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.0
- UOPS_MS: 0.02
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 8.0
- UOPS_PORT_78: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	62 91 7f 09 7f 04 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1]{k1},xmm0
   7:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x10]{k1},xmm0
   e:	01 
   f:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x20]{k1},xmm0
  16:	02 
  17:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x30]{k1},xmm0
  1e:	03 
  1f:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x40]{k1},xmm0
  26:	04 
  27:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x50]{k1},xmm0
  2e:	05 
  2f:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x60]{k1},xmm0
  36:	06 
  37:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x70]{k1},xmm0
  3e:	07

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 4.01
- Reference cycles: 1.33
- UOPS_EXECUTED.THREAD: 16.1
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.07
- UOPS_MS: 0.02
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 8.0
- UOPS_PORT_78: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 91 7f 09 7f 04 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1]{k1},xmm0
   7:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x10]{k1},xmm0
   e:	01 
   f:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x20]{k1},xmm0
  16:	02 
  17:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x30]{k1},xmm0
  1e:	03 
  1f:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x40]{k1},xmm0
  26:	04 
  27:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x50]{k1},xmm0
  2e:	05 
  2f:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x60]{k1},xmm0
  36:	06 
  37:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x70]{k1},xmm0
  3e:	07 
  3f:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x80]{k1},xmm0
  46:	08 
  47:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x90]{k1},xmm0
  4e:	09 
  4f:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0xa0]{k1},xmm0
  56:	0a 
  57:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0xb0]{k1},xmm0
  5e:	0b 
  5f:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0xc0]{k1},xmm0
  66:	0c 
  67:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0xd0]{k1},xmm0
  6e:	0d 
  6f:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0xe0]{k1},xmm0
  76:	0e 
  77:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0xf0]{k1},xmm0
  7e:	0f

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 8.0
- Reference cycles: 2.74
- UOPS_EXECUTED.THREAD: 32.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 16.0
- UOPS_PORT_78: 16.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 91 7f 09 7f 04 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1]{k1},xmm0
   7:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x10]{k1},xmm0
   e:	01 
   f:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x20]{k1},xmm0
  16:	02 
  17:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x30]{k1},xmm0
  1e:	03 
  1f:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x40]{k1},xmm0
  26:	04 
  27:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x50]{k1},xmm0
  2e:	05 
  2f:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x60]{k1},xmm0
  36:	06 
  37:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x70]{k1},xmm0
  3e:	07 
  3f:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x80]{k1},xmm0
  46:	08 
  47:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x90]{k1},xmm0
  4e:	09 
  4f:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0xa0]{k1},xmm0
  56:	0a 
  57:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0xb0]{k1},xmm0
  5e:	0b 
  5f:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0xc0]{k1},xmm0
  66:	0c 
  67:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0xd0]{k1},xmm0
  6e:	0d 
  6f:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0xe0]{k1},xmm0
  76:	0e 
  77:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0xf0]{k1},xmm0
  7e:	0f

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 8.02
- Reference cycles: 2.66
- UOPS_EXECUTED.THREAD: 33.01
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.03
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 16.0
- UOPS_PORT_78: 16.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	62 91 7f 09 7f 04 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1]{k1},xmm0
   7:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x10]{k1},xmm0
   e:	01 
   f:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x20]{k1},xmm0
  16:	02 
  17:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x30]{k1},xmm0
  1e:	03 
  1f:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x40]{k1},xmm0
  26:	04 
  27:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x50]{k1},xmm0
  2e:	05 
  2f:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x60]{k1},xmm0
  36:	06 
  37:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x70]{k1},xmm0
  3e:	07 
  3f:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x80]{k1},xmm0
  46:	08 
  47:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0x90]{k1},xmm0
  4e:	09 
  4f:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0xa0]{k1},xmm0
  56:	0a 
  57:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0xb0]{k1},xmm0
  5e:	0b 
  5f:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0xc0]{k1},xmm0
  66:	0c 
  67:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0xd0]{k1},xmm0
  6e:	0d 
  6f:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0xe0]{k1},xmm0
  76:	0e 
  77:	62 91 7f 09 7f 44 2e 	vmovdqu8 XMMWORD PTR [r14+r13*1+0xf0]{k1},xmm0
  7e:	0f

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 8.01
- Reference cycles: 2.66
- UOPS_EXECUTED.THREAD: 32.11
- RETIRE_SLOTS: 16.11
- UOPS_MITE: 0.15
- UOPS_MS: 0.02
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 16.0
- UOPS_PORT_78: 16.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.05

VMOVDQU8 (M128, K, XMM) - Throughput and Uops

With a non-indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10