VADDPD (ZMM, K, ZMM, ZMM)

With unroll_count=500 and no inner loop

Code:

   0:	62 f1 f5 49 58 c2    	vaddpd zmm0{k1},zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 4.0
- Reference cycles: 1.36
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 0.98
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	62 f1 f5 49 58 c2    	vaddpd zmm0{k1},zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 4.0
- Reference cycles: 1.36
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 f1 f5 49 58 c2    	vaddpd zmm0{k1},zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 4.0
- Reference cycles: 1.36
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 f1 f5 49 58 c2    	vaddpd zmm0{k1},zmm1,zmm2
   6:	62 f1 f5 49 58 da    	vaddpd zmm3{k1},zmm1,zmm2
   c:	62 f1 f5 49 58 e2    	vaddpd zmm4{k1},zmm1,zmm2
  12:	62 f1 f5 49 58 ea    	vaddpd zmm5{k1},zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14]

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 1.34
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.03
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	62 f1 f5 49 58 c2    	vaddpd zmm0{k1},zmm1,zmm2
   6:	62 f1 f5 49 58 da    	vaddpd zmm3{k1},zmm1,zmm2
   c:	62 f1 f5 49 58 e2    	vaddpd zmm4{k1},zmm1,zmm2
  12:	62 f1 f5 49 58 ea    	vaddpd zmm5{k1},zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14]

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.01
- Reference cycles: 1.36
- UOPS_EXECUTED.THREAD: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.01
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	62 f1 f5 49 58 c2    	vaddpd zmm0{k1},zmm1,zmm2
   6:	62 f1 f5 49 58 da    	vaddpd zmm3{k1},zmm1,zmm2
   c:	62 f1 f5 49 58 e2    	vaddpd zmm4{k1},zmm1,zmm2
  12:	62 f1 f5 49 58 ea    	vaddpd zmm5{k1},zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14]

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.01
- Reference cycles: 1.37
- UOPS_EXECUTED.THREAD: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.01
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f1 f5 49 58 c2    	vaddpd zmm0{k1},zmm1,zmm2
   6:	62 f1 f5 49 58 da    	vaddpd zmm3{k1},zmm1,zmm2
   c:	62 f1 f5 49 58 e2    	vaddpd zmm4{k1},zmm1,zmm2
  12:	62 f1 f5 49 58 ea    	vaddpd zmm5{k1},zmm1,zmm2
  18:	62 f1 f5 49 58 f2    	vaddpd zmm6{k1},zmm1,zmm2
  1e:	62 f1 f5 49 58 fa    	vaddpd zmm7{k1},zmm1,zmm2
  24:	62 71 f5 49 58 c2    	vaddpd zmm8{k1},zmm1,zmm2
  2a:	62 71 f5 49 58 ca    	vaddpd zmm9{k1},zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14];
VMOVUPD ZMM6, [R14];
VMOVUPD ZMM7, [R14];
VMOVUPD ZMM8, [R14];
VMOVUPD ZMM9, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 2.69
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f1 f5 49 58 c2    	vaddpd zmm0{k1},zmm1,zmm2
   6:	62 f1 f5 49 58 da    	vaddpd zmm3{k1},zmm1,zmm2
   c:	62 f1 f5 49 58 e2    	vaddpd zmm4{k1},zmm1,zmm2
  12:	62 f1 f5 49 58 ea    	vaddpd zmm5{k1},zmm1,zmm2
  18:	62 f1 f5 49 58 f2    	vaddpd zmm6{k1},zmm1,zmm2
  1e:	62 f1 f5 49 58 fa    	vaddpd zmm7{k1},zmm1,zmm2
  24:	62 71 f5 49 58 c2    	vaddpd zmm8{k1},zmm1,zmm2
  2a:	62 71 f5 49 58 ca    	vaddpd zmm9{k1},zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14];
VMOVUPD ZMM6, [R14];
VMOVUPD ZMM7, [R14];
VMOVUPD ZMM8, [R14];
VMOVUPD ZMM9, [R14]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.01
- Reference cycles: 2.73
- UOPS_EXECUTED.THREAD: 9.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.03
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	62 f1 f5 49 58 c2    	vaddpd zmm0{k1},zmm1,zmm2
   6:	62 f1 f5 49 58 da    	vaddpd zmm3{k1},zmm1,zmm2
   c:	62 f1 f5 49 58 e2    	vaddpd zmm4{k1},zmm1,zmm2
  12:	62 f1 f5 49 58 ea    	vaddpd zmm5{k1},zmm1,zmm2
  18:	62 f1 f5 49 58 f2    	vaddpd zmm6{k1},zmm1,zmm2
  1e:	62 f1 f5 49 58 fa    	vaddpd zmm7{k1},zmm1,zmm2
  24:	62 71 f5 49 58 c2    	vaddpd zmm8{k1},zmm1,zmm2
  2a:	62 71 f5 49 58 ca    	vaddpd zmm9{k1},zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14];
VMOVUPD ZMM6, [R14];
VMOVUPD ZMM7, [R14];
VMOVUPD ZMM8, [R14];
VMOVUPD ZMM9, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.01
- Reference cycles: 2.73
- UOPS_EXECUTED.THREAD: 8.1
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.07
- UOPS_MS: 0.02
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f1 f5 49 58 c2    	vaddpd zmm0{k1},zmm1,zmm2
   6:	62 f1 f5 49 58 da    	vaddpd zmm3{k1},zmm1,zmm2
   c:	62 f1 f5 49 58 e2    	vaddpd zmm4{k1},zmm1,zmm2
  12:	62 f1 f5 49 58 ea    	vaddpd zmm5{k1},zmm1,zmm2
  18:	62 f1 f5 49 58 f2    	vaddpd zmm6{k1},zmm1,zmm2
  1e:	62 f1 f5 49 58 fa    	vaddpd zmm7{k1},zmm1,zmm2
  24:	62 71 f5 49 58 c2    	vaddpd zmm8{k1},zmm1,zmm2
  2a:	62 71 f5 49 58 ca    	vaddpd zmm9{k1},zmm1,zmm2
  30:	62 71 f5 49 58 d2    	vaddpd zmm10{k1},zmm1,zmm2
  36:	62 71 f5 49 58 da    	vaddpd zmm11{k1},zmm1,zmm2
  3c:	62 71 f5 49 58 e2    	vaddpd zmm12{k1},zmm1,zmm2
  42:	62 e1 f5 49 58 c2    	vaddpd zmm16{k1},zmm1,zmm2
  48:	62 e1 f5 49 58 ca    	vaddpd zmm17{k1},zmm1,zmm2
  4e:	62 e1 f5 49 58 d2    	vaddpd zmm18{k1},zmm1,zmm2
  54:	62 e1 f5 49 58 da    	vaddpd zmm19{k1},zmm1,zmm2
  5a:	62 e1 f5 49 58 e2    	vaddpd zmm20{k1},zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14];
VMOVUPD ZMM6, [R14];
VMOVUPD ZMM7, [R14];
VMOVUPD ZMM8, [R14];
VMOVUPD ZMM9, [R14];
VMOVUPD ZMM10, [R14];
VMOVUPD ZMM11, [R14];
VMOVUPD ZMM12, [R14];
VMOVUPD ZMM16, [R14];
VMOVUPD ZMM17, [R14];
VMOVUPD ZMM18, [R14];
VMOVUPD ZMM19, [R14];
VMOVUPD ZMM20, [R14]

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 16.01
- Reference cycles: 5.37
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 16.01
- UOPS_MITE: 16.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 16.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 3.98

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f1 f5 49 58 c2    	vaddpd zmm0{k1},zmm1,zmm2
   6:	62 f1 f5 49 58 da    	vaddpd zmm3{k1},zmm1,zmm2
   c:	62 f1 f5 49 58 e2    	vaddpd zmm4{k1},zmm1,zmm2
  12:	62 f1 f5 49 58 ea    	vaddpd zmm5{k1},zmm1,zmm2
  18:	62 f1 f5 49 58 f2    	vaddpd zmm6{k1},zmm1,zmm2
  1e:	62 f1 f5 49 58 fa    	vaddpd zmm7{k1},zmm1,zmm2
  24:	62 71 f5 49 58 c2    	vaddpd zmm8{k1},zmm1,zmm2
  2a:	62 71 f5 49 58 ca    	vaddpd zmm9{k1},zmm1,zmm2
  30:	62 71 f5 49 58 d2    	vaddpd zmm10{k1},zmm1,zmm2
  36:	62 71 f5 49 58 da    	vaddpd zmm11{k1},zmm1,zmm2
  3c:	62 71 f5 49 58 e2    	vaddpd zmm12{k1},zmm1,zmm2
  42:	62 e1 f5 49 58 c2    	vaddpd zmm16{k1},zmm1,zmm2
  48:	62 e1 f5 49 58 ca    	vaddpd zmm17{k1},zmm1,zmm2
  4e:	62 e1 f5 49 58 d2    	vaddpd zmm18{k1},zmm1,zmm2
  54:	62 e1 f5 49 58 da    	vaddpd zmm19{k1},zmm1,zmm2
  5a:	62 e1 f5 49 58 e2    	vaddpd zmm20{k1},zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14];
VMOVUPD ZMM6, [R14];
VMOVUPD ZMM7, [R14];
VMOVUPD ZMM8, [R14];
VMOVUPD ZMM9, [R14];
VMOVUPD ZMM10, [R14];
VMOVUPD ZMM11, [R14];
VMOVUPD ZMM12, [R14];
VMOVUPD ZMM16, [R14];
VMOVUPD ZMM17, [R14];
VMOVUPD ZMM18, [R14];
VMOVUPD ZMM19, [R14];
VMOVUPD ZMM20, [R14]

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 16.01
- Reference cycles: 5.46
- UOPS_EXECUTED.THREAD: 17.0
- RETIRE_SLOTS: 17.01
- UOPS_MITE: 0.02
- UOPS_MS: 0.02
- UOPS_PORT_0: 16.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	62 f1 f5 49 58 c2    	vaddpd zmm0{k1},zmm1,zmm2
   6:	62 f1 f5 49 58 da    	vaddpd zmm3{k1},zmm1,zmm2
   c:	62 f1 f5 49 58 e2    	vaddpd zmm4{k1},zmm1,zmm2
  12:	62 f1 f5 49 58 ea    	vaddpd zmm5{k1},zmm1,zmm2
  18:	62 f1 f5 49 58 f2    	vaddpd zmm6{k1},zmm1,zmm2
  1e:	62 f1 f5 49 58 fa    	vaddpd zmm7{k1},zmm1,zmm2
  24:	62 71 f5 49 58 c2    	vaddpd zmm8{k1},zmm1,zmm2
  2a:	62 71 f5 49 58 ca    	vaddpd zmm9{k1},zmm1,zmm2
  30:	62 71 f5 49 58 d2    	vaddpd zmm10{k1},zmm1,zmm2
  36:	62 71 f5 49 58 da    	vaddpd zmm11{k1},zmm1,zmm2
  3c:	62 71 f5 49 58 e2    	vaddpd zmm12{k1},zmm1,zmm2
  42:	62 e1 f5 49 58 c2    	vaddpd zmm16{k1},zmm1,zmm2
  48:	62 e1 f5 49 58 ca    	vaddpd zmm17{k1},zmm1,zmm2
  4e:	62 e1 f5 49 58 d2    	vaddpd zmm18{k1},zmm1,zmm2
  54:	62 e1 f5 49 58 da    	vaddpd zmm19{k1},zmm1,zmm2
  5a:	62 e1 f5 49 58 e2    	vaddpd zmm20{k1},zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14];
VMOVUPD ZMM6, [R14];
VMOVUPD ZMM7, [R14];
VMOVUPD ZMM8, [R14];
VMOVUPD ZMM9, [R14];
VMOVUPD ZMM10, [R14];
VMOVUPD ZMM11, [R14];
VMOVUPD ZMM12, [R14];
VMOVUPD ZMM16, [R14];
VMOVUPD ZMM17, [R14];
VMOVUPD ZMM18, [R14];
VMOVUPD ZMM19, [R14];
VMOVUPD ZMM20, [R14]

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 16.01
- Reference cycles: 5.47
- UOPS_EXECUTED.THREAD: 16.1
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.17
- UOPS_MS: 0.02
- UOPS_PORT_0: 16.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.05

With the same register for for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	62 f1 fd 49 58 c0    	vaddpd zmm0{k1},zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 4.0
- Reference cycles: 1.36
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 0.98
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	62 f1 fd 49 58 c0    	vaddpd zmm0{k1},zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 4.0
- Reference cycles: 1.36
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 f1 fd 49 58 c0    	vaddpd zmm0{k1},zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 4.0
- Reference cycles: 1.36
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 f1 fd 49 58 c0    	vaddpd zmm0{k1},zmm0,zmm0
   6:	62 f1 f5 49 58 c9    	vaddpd zmm1{k1},zmm1,zmm1
   c:	62 f1 ed 49 58 d2    	vaddpd zmm2{k1},zmm2,zmm2
  12:	62 f1 e5 49 58 db    	vaddpd zmm3{k1},zmm3,zmm3

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14]

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 1.34
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	62 f1 fd 49 58 c0    	vaddpd zmm0{k1},zmm0,zmm0
   6:	62 f1 f5 49 58 c9    	vaddpd zmm1{k1},zmm1,zmm1
   c:	62 f1 ed 49 58 d2    	vaddpd zmm2{k1},zmm2,zmm2
  12:	62 f1 e5 49 58 db    	vaddpd zmm3{k1},zmm3,zmm3

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14]

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.0
- Reference cycles: 1.36
- UOPS_EXECUTED.THREAD: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.01
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	62 f1 fd 49 58 c0    	vaddpd zmm0{k1},zmm0,zmm0
   6:	62 f1 f5 49 58 c9    	vaddpd zmm1{k1},zmm1,zmm1
   c:	62 f1 ed 49 58 d2    	vaddpd zmm2{k1},zmm2,zmm2
  12:	62 f1 e5 49 58 db    	vaddpd zmm3{k1},zmm3,zmm3

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14]

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.01
- Reference cycles: 1.36
- UOPS_EXECUTED.THREAD: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.01
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f1 fd 49 58 c0    	vaddpd zmm0{k1},zmm0,zmm0
   6:	62 f1 f5 49 58 c9    	vaddpd zmm1{k1},zmm1,zmm1
   c:	62 f1 ed 49 58 d2    	vaddpd zmm2{k1},zmm2,zmm2
  12:	62 f1 e5 49 58 db    	vaddpd zmm3{k1},zmm3,zmm3
  18:	62 f1 dd 49 58 e4    	vaddpd zmm4{k1},zmm4,zmm4
  1e:	62 f1 d5 49 58 ed    	vaddpd zmm5{k1},zmm5,zmm5
  24:	62 f1 cd 49 58 f6    	vaddpd zmm6{k1},zmm6,zmm6
  2a:	62 f1 c5 49 58 ff    	vaddpd zmm7{k1},zmm7,zmm7

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14];
VMOVUPD ZMM6, [R14];
VMOVUPD ZMM7, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 2.74
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.02
- UOPS_MITE: 7.93
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f1 fd 49 58 c0    	vaddpd zmm0{k1},zmm0,zmm0
   6:	62 f1 f5 49 58 c9    	vaddpd zmm1{k1},zmm1,zmm1
   c:	62 f1 ed 49 58 d2    	vaddpd zmm2{k1},zmm2,zmm2
  12:	62 f1 e5 49 58 db    	vaddpd zmm3{k1},zmm3,zmm3
  18:	62 f1 dd 49 58 e4    	vaddpd zmm4{k1},zmm4,zmm4
  1e:	62 f1 d5 49 58 ed    	vaddpd zmm5{k1},zmm5,zmm5
  24:	62 f1 cd 49 58 f6    	vaddpd zmm6{k1},zmm6,zmm6
  2a:	62 f1 c5 49 58 ff    	vaddpd zmm7{k1},zmm7,zmm7

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14];
VMOVUPD ZMM6, [R14];
VMOVUPD ZMM7, [R14]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.01
- Reference cycles: 2.73
- UOPS_EXECUTED.THREAD: 9.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.03
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	62 f1 fd 49 58 c0    	vaddpd zmm0{k1},zmm0,zmm0
   6:	62 f1 f5 49 58 c9    	vaddpd zmm1{k1},zmm1,zmm1
   c:	62 f1 ed 49 58 d2    	vaddpd zmm2{k1},zmm2,zmm2
  12:	62 f1 e5 49 58 db    	vaddpd zmm3{k1},zmm3,zmm3
  18:	62 f1 dd 49 58 e4    	vaddpd zmm4{k1},zmm4,zmm4
  1e:	62 f1 d5 49 58 ed    	vaddpd zmm5{k1},zmm5,zmm5
  24:	62 f1 cd 49 58 f6    	vaddpd zmm6{k1},zmm6,zmm6
  2a:	62 f1 c5 49 58 ff    	vaddpd zmm7{k1},zmm7,zmm7

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14];
VMOVUPD ZMM6, [R14];
VMOVUPD ZMM7, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.01
- Reference cycles: 2.73
- UOPS_EXECUTED.THREAD: 8.1
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.07
- UOPS_MS: 0.02
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f1 fd 49 58 c0    	vaddpd zmm0{k1},zmm0,zmm0
   6:	62 f1 f5 49 58 c9    	vaddpd zmm1{k1},zmm1,zmm1
   c:	62 f1 ed 49 58 d2    	vaddpd zmm2{k1},zmm2,zmm2
  12:	62 f1 e5 49 58 db    	vaddpd zmm3{k1},zmm3,zmm3
  18:	62 f1 dd 49 58 e4    	vaddpd zmm4{k1},zmm4,zmm4
  1e:	62 f1 d5 49 58 ed    	vaddpd zmm5{k1},zmm5,zmm5
  24:	62 f1 cd 49 58 f6    	vaddpd zmm6{k1},zmm6,zmm6
  2a:	62 f1 c5 49 58 ff    	vaddpd zmm7{k1},zmm7,zmm7
  30:	62 51 bd 49 58 c0    	vaddpd zmm8{k1},zmm8,zmm8
  36:	62 51 b5 49 58 c9    	vaddpd zmm9{k1},zmm9,zmm9
  3c:	62 51 ad 49 58 d2    	vaddpd zmm10{k1},zmm10,zmm10
  42:	62 51 a5 49 58 db    	vaddpd zmm11{k1},zmm11,zmm11
  48:	62 51 9d 49 58 e4    	vaddpd zmm12{k1},zmm12,zmm12
  4e:	62 a1 fd 41 58 c0    	vaddpd zmm16{k1},zmm16,zmm16
  54:	62 a1 f5 41 58 c9    	vaddpd zmm17{k1},zmm17,zmm17
  5a:	62 a1 ed 41 58 d2    	vaddpd zmm18{k1},zmm18,zmm18

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14];
VMOVUPD ZMM6, [R14];
VMOVUPD ZMM7, [R14];
VMOVUPD ZMM8, [R14];
VMOVUPD ZMM9, [R14];
VMOVUPD ZMM10, [R14];
VMOVUPD ZMM11, [R14];
VMOVUPD ZMM12, [R14];
VMOVUPD ZMM16, [R14];
VMOVUPD ZMM17, [R14];
VMOVUPD ZMM18, [R14]

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 16.01
- Reference cycles: 5.63
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 16.04
- UOPS_MITE: 16.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 16.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f1 fd 49 58 c0    	vaddpd zmm0{k1},zmm0,zmm0
   6:	62 f1 f5 49 58 c9    	vaddpd zmm1{k1},zmm1,zmm1
   c:	62 f1 ed 49 58 d2    	vaddpd zmm2{k1},zmm2,zmm2
  12:	62 f1 e5 49 58 db    	vaddpd zmm3{k1},zmm3,zmm3
  18:	62 f1 dd 49 58 e4    	vaddpd zmm4{k1},zmm4,zmm4
  1e:	62 f1 d5 49 58 ed    	vaddpd zmm5{k1},zmm5,zmm5
  24:	62 f1 cd 49 58 f6    	vaddpd zmm6{k1},zmm6,zmm6
  2a:	62 f1 c5 49 58 ff    	vaddpd zmm7{k1},zmm7,zmm7
  30:	62 51 bd 49 58 c0    	vaddpd zmm8{k1},zmm8,zmm8
  36:	62 51 b5 49 58 c9    	vaddpd zmm9{k1},zmm9,zmm9
  3c:	62 51 ad 49 58 d2    	vaddpd zmm10{k1},zmm10,zmm10
  42:	62 51 a5 49 58 db    	vaddpd zmm11{k1},zmm11,zmm11
  48:	62 51 9d 49 58 e4    	vaddpd zmm12{k1},zmm12,zmm12
  4e:	62 a1 fd 41 58 c0    	vaddpd zmm16{k1},zmm16,zmm16
  54:	62 a1 f5 41 58 c9    	vaddpd zmm17{k1},zmm17,zmm17
  5a:	62 a1 ed 41 58 d2    	vaddpd zmm18{k1},zmm18,zmm18

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14];
VMOVUPD ZMM6, [R14];
VMOVUPD ZMM7, [R14];
VMOVUPD ZMM8, [R14];
VMOVUPD ZMM9, [R14];
VMOVUPD ZMM10, [R14];
VMOVUPD ZMM11, [R14];
VMOVUPD ZMM12, [R14];
VMOVUPD ZMM16, [R14];
VMOVUPD ZMM17, [R14];
VMOVUPD ZMM18, [R14]

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 16.01
- Reference cycles: 5.47
- UOPS_EXECUTED.THREAD: 17.0
- RETIRE_SLOTS: 17.01
- UOPS_MITE: 0.02
- UOPS_MS: 0.02
- UOPS_PORT_0: 16.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	62 f1 fd 49 58 c0    	vaddpd zmm0{k1},zmm0,zmm0
   6:	62 f1 f5 49 58 c9    	vaddpd zmm1{k1},zmm1,zmm1
   c:	62 f1 ed 49 58 d2    	vaddpd zmm2{k1},zmm2,zmm2
  12:	62 f1 e5 49 58 db    	vaddpd zmm3{k1},zmm3,zmm3
  18:	62 f1 dd 49 58 e4    	vaddpd zmm4{k1},zmm4,zmm4
  1e:	62 f1 d5 49 58 ed    	vaddpd zmm5{k1},zmm5,zmm5
  24:	62 f1 cd 49 58 f6    	vaddpd zmm6{k1},zmm6,zmm6
  2a:	62 f1 c5 49 58 ff    	vaddpd zmm7{k1},zmm7,zmm7
  30:	62 51 bd 49 58 c0    	vaddpd zmm8{k1},zmm8,zmm8
  36:	62 51 b5 49 58 c9    	vaddpd zmm9{k1},zmm9,zmm9
  3c:	62 51 ad 49 58 d2    	vaddpd zmm10{k1},zmm10,zmm10
  42:	62 51 a5 49 58 db    	vaddpd zmm11{k1},zmm11,zmm11
  48:	62 51 9d 49 58 e4    	vaddpd zmm12{k1},zmm12,zmm12
  4e:	62 a1 fd 41 58 c0    	vaddpd zmm16{k1},zmm16,zmm16
  54:	62 a1 f5 41 58 c9    	vaddpd zmm17{k1},zmm17,zmm17
  5a:	62 a1 ed 41 58 d2    	vaddpd zmm18{k1},zmm18,zmm18

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14];
VMOVUPD ZMM6, [R14];
VMOVUPD ZMM7, [R14];
VMOVUPD ZMM8, [R14];
VMOVUPD ZMM9, [R14];
VMOVUPD ZMM10, [R14];
VMOVUPD ZMM11, [R14];
VMOVUPD ZMM12, [R14];
VMOVUPD ZMM16, [R14];
VMOVUPD ZMM17, [R14];
VMOVUPD ZMM18, [R14]

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 16.02
- Reference cycles: 5.62
- UOPS_EXECUTED.THREAD: 16.1
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.17
- UOPS_MS: 0.02
- UOPS_PORT_0: 16.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.05

VADDPD (ZMM, K, ZMM, ZMM) - Throughput and Uops

With different registers for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With the same register for for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10