DIV (R32)

With unroll_count=500 and no inner loop

Code:

   0:	48 c7 c0 00 00 00 00 	mov    rax,0x0
   7:	48 c7 c2 00 00 00 00 	mov    rdx,0x0
   e:	f7 f3                	div    ebx

Init:
```
MOV EBX, 1;
MOV RAX, 0;
MOV RDX, 0
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 6.0
- Reference cycles: 1.98
- UOPS_EXECUTED.THREAD: 5.99
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 5.99
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.05
- UOPS_PORT_1: 2.0
- UOPS_PORT_5: 1.96
- UOPS_PORT_6: 0.99
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 6.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With unroll_count=500 and no inner loop

Code:

   0:	48 c7 c0 00 00 00 00 	mov    rax,0x0
   7:	48 c7 c2 00 00 00 00 	mov    rdx,0x0
   e:	f7 f3                	div    ebx
  10:	0f ae e8             	lfence

Init:
```
MOV EBX, 1;
MOV RAX, 0;
MOV RDX, 0
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 27.4
- Reference cycles: 9.1
- UOPS_EXECUTED.THREAD: 6.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 6.0
- UOPS_MS: 2.0
- UOPS_PORT_0: 0.8
- UOPS_PORT_1: 3.0
- UOPS_PORT_5: 1.2
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 6.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	48 c7 c0 00 00 00 00 	mov    rax,0x0
   7:	48 c7 c2 00 00 00 00 	mov    rdx,0x0
   e:	f7 f3                	div    ebx

Init:
```
MOV EBX, 1;
MOV RAX, 0;
MOV RDX, 0
```
Show nanoBench command
Results:
- Instructions retired: 3.2
- Core cycles: 6.0
- Reference cycles: 1.99
- UOPS_EXECUTED.THREAD: 6.1
- RETIRE_SLOTS: 6.1
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.99
- UOPS_PORT_1: 2.0
- UOPS_PORT_5: 1.94
- UOPS_PORT_6: 1.17
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 6.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	48 c7 c0 00 00 00 00 	mov    rax,0x0
   7:	48 c7 c2 00 00 00 00 	mov    rdx,0x0
   e:	40                   	rex
   f:	40                   	rex
  10:	40                   	rex
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	40                   	rex
  15:	40                   	rex
  16:	40                   	rex
  17:	40                   	rex
  18:	40                   	rex
  19:	40 f7 f3             	rex div ebx

Init:
```
MOV EBX, 1;
MOV RAX, 0;
MOV RDX, 0
```
Show nanoBench command
Results:
- Instructions retired: 3.2
- Core cycles: 6.0
- Reference cycles: 1.99
- UOPS_EXECUTED.THREAD: 6.1
- RETIRE_SLOTS: 6.1
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.99
- UOPS_PORT_1: 2.0
- UOPS_PORT_5: 1.94
- UOPS_PORT_6: 1.17
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 6.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	48 c7 c0 00 00 00 00 	mov    rax,0x0
   7:	48 c7 c2 00 00 00 00 	mov    rdx,0x0
   e:	f7 f3                	div    ebx

Init:
```
MOV EBX, 1;
MOV RAX, 0;
MOV RDX, 0
```
Show nanoBench command
Results:
- Instructions retired: 3.02
- Core cycles: 6.0
- Reference cycles: 1.99
- UOPS_EXECUTED.THREAD: 6.01
- RETIRE_SLOTS: 6.01
- UOPS_MITE: 0.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 2.0
- UOPS_PORT_5: 1.96
- UOPS_PORT_6: 1.05
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 6.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

Code:

   0:	48 c7 c0 00 00 00 00 	mov    rax,0x0
   7:	48 c7 c2 00 00 00 00 	mov    rdx,0x0
   e:	40                   	rex
   f:	40                   	rex
  10:	40                   	rex
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	40                   	rex
  15:	40                   	rex
  16:	40                   	rex
  17:	40                   	rex
  18:	40                   	rex
  19:	40 f7 f3             	rex div ebx

Init:
```
MOV EBX, 1;
MOV RAX, 0;
MOV RDX, 0
```
Show nanoBench command
Results:
- Instructions retired: 3.02
- Core cycles: 6.0
- Reference cycles: 1.99
- UOPS_EXECUTED.THREAD: 6.01
- RETIRE_SLOTS: 6.01
- UOPS_MITE: 0.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.99
- UOPS_PORT_1: 2.0
- UOPS_PORT_5: 1.96
- UOPS_PORT_6: 1.06
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 6.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With unroll_count=500 and no inner loop

Code:

   0:	b8 85 00 00 00       	mov    eax,0x85
   5:	ba d7 9e 3a 34       	mov    edx,0x343a9ed7
   a:	f7 f3                	div    ebx

Init:
```
MOV EBX, 0x75e6e44f
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 6.0
- Reference cycles: 1.98
- UOPS_EXECUTED.THREAD: 5.99
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 6.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.96
- UOPS_PORT_1: 2.0
- UOPS_PORT_5: 1.97
- UOPS_PORT_6: 1.07
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 6.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With unroll_count=500 and no inner loop

Code:

   0:	b8 85 00 00 00       	mov    eax,0x85
   5:	ba d7 9e 3a 34       	mov    edx,0x343a9ed7
   a:	f7 f3                	div    ebx
   c:	0f ae e8             	lfence

Init:
```
MOV EBX, 0x75e6e44f
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 27.4
- Reference cycles: 9.1
- UOPS_EXECUTED.THREAD: 6.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 5.98
- UOPS_MS: 2.0
- UOPS_PORT_0: 0.8
- UOPS_PORT_1: 3.0
- UOPS_PORT_5: 1.2
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 6.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	b8 85 00 00 00       	mov    eax,0x85
   5:	ba d7 9e 3a 34       	mov    edx,0x343a9ed7
   a:	f7 f3                	div    ebx

Init:
```
MOV EBX, 0x75e6e44f
```
Show nanoBench command
Results:
- Instructions retired: 3.2
- Core cycles: 6.0
- Reference cycles: 1.99
- UOPS_EXECUTED.THREAD: 6.1
- RETIRE_SLOTS: 6.1
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 2.0
- UOPS_PORT_5: 1.94
- UOPS_PORT_6: 1.16
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 6.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	b8 85 00 00 00       	mov    eax,0x85
   5:	ba d7 9e 3a 34       	mov    edx,0x343a9ed7
   a:	40                   	rex
   b:	40                   	rex
   c:	40                   	rex
   d:	40                   	rex
   e:	40                   	rex
   f:	40                   	rex
  10:	40                   	rex
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	40                   	rex
  15:	40 f7 f3             	rex div ebx

Init:
```
MOV EBX, 0x75e6e44f
```
Show nanoBench command
Results:
- Instructions retired: 3.2
- Core cycles: 6.0
- Reference cycles: 1.99
- UOPS_EXECUTED.THREAD: 6.1
- RETIRE_SLOTS: 6.1
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 2.0
- UOPS_PORT_5: 1.93
- UOPS_PORT_6: 1.17
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 6.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	b8 85 00 00 00       	mov    eax,0x85
   5:	ba d7 9e 3a 34       	mov    edx,0x343a9ed7
   a:	f7 f3                	div    ebx

Init:
```
MOV EBX, 0x75e6e44f
```
Show nanoBench command
Results:
- Instructions retired: 3.02
- Core cycles: 6.0
- Reference cycles: 1.99
- UOPS_EXECUTED.THREAD: 6.01
- RETIRE_SLOTS: 6.01
- UOPS_MITE: 0.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.99
- UOPS_PORT_1: 2.0
- UOPS_PORT_5: 1.96
- UOPS_PORT_6: 1.06
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 6.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

Code:

   0:	b8 85 00 00 00       	mov    eax,0x85
   5:	ba d7 9e 3a 34       	mov    edx,0x343a9ed7
   a:	40                   	rex
   b:	40                   	rex
   c:	40                   	rex
   d:	40                   	rex
   e:	40                   	rex
   f:	40                   	rex
  10:	40                   	rex
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	40                   	rex
  15:	40 f7 f3             	rex div ebx

Init:
```
MOV EBX, 0x75e6e44f
```
Show nanoBench command
Results:
- Instructions retired: 3.02
- Core cycles: 6.0
- Reference cycles: 1.99
- UOPS_EXECUTED.THREAD: 6.01
- RETIRE_SLOTS: 6.01
- UOPS_MITE: 0.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 2.0
- UOPS_PORT_5: 1.95
- UOPS_PORT_6: 1.06
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 6.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

DIV (R32) - Throughput and Uops

Fast division

With unroll_count=500 and no inner loop

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

With loop_count=100 and unroll_count=100

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

Slow division

With unroll_count=500 and no inner loop

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

With loop_count=100 and unroll_count=100

With loop_count=100, unroll_count=100, and padding (redundant prefixes)