VSQRTSS (XMM, XMM, XMM) - Throughput and Uops

With unroll_count=500 and no inner loop

• Code:

     0:	c5 f2 51 d0          	vsqrtss xmm2,xmm1,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x3f8000003f800000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 1.0
  • Core cycles: 7.03
  • Reference cycles: 6.99
  • UOPS_EXECUTED.CORE: 1.0
  • RETIRE_SLOTS: 1.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 1.97
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.25

With unroll_count=500 and no inner loop

• Code:

     0:	c5 f2 51 d0          	vsqrtss xmm2,xmm1,xmm0
     4:	0f ae e8             	lfence 
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x3f8000003f800000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 18.25
  • Reference cycles: 18.27
  • UOPS_EXECUTED.CORE: 1.0
  • RETIRE_SLOTS: 3.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 2.0
  • UOPS_PORT_0: 1.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 9.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=10

• Code:

     0:	c5 f2 51 d0          	vsqrtss xmm2,xmm1,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x3f8000003f800000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 1.2
  • Core cycles: 7.04
  • Reference cycles: 7.04
  • UOPS_EXECUTED.CORE: 1.1
  • RETIRE_SLOTS: 1.1
  • UOPS_MITE: 0.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.1
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 1.96
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

• Code:

     0:	c5 f2 51 d0          	vsqrtss xmm2,xmm1,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x3f8000003f800000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 1.02
  • Core cycles: 7.03
  • Reference cycles: 7.03
  • UOPS_EXECUTED.CORE: 1.01
  • RETIRE_SLOTS: 1.01
  • UOPS_MITE: 0.01
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.01
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 1.97
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With unroll_count=200 and no inner loop

• Code:

     0:	c5 f2 51 d0          	vsqrtss xmm2,xmm1,xmm0
     4:	c5 f2 51 d8          	vsqrtss xmm3,xmm1,xmm0
     8:	c5 f2 51 e0          	vsqrtss xmm4,xmm1,xmm0
     c:	c5 f2 51 e8          	vsqrtss xmm5,xmm1,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x3f8000003f800000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 28.1
  • Reference cycles: 28.03
  • UOPS_EXECUTED.CORE: 4.0
  • RETIRE_SLOTS: 4.0
  • UOPS_MITE: 4.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 4.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 7.89
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

• Code:

     0:	c5 f2 51 d0          	vsqrtss xmm2,xmm1,xmm0
     4:	c5 f2 51 d8          	vsqrtss xmm3,xmm1,xmm0
     8:	c5 f2 51 e0          	vsqrtss xmm4,xmm1,xmm0
     c:	c5 f2 51 e8          	vsqrtss xmm5,xmm1,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x3f8000003f800000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 28.17
  • Reference cycles: 28.16
  • UOPS_EXECUTED.CORE: 4.5
  • RETIRE_SLOTS: 4.5
  • UOPS_MITE: 0.01
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 4.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.5
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 7.83
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

• Code:

     0:	c5 f2 51 d0          	vsqrtss xmm2,xmm1,xmm0
     4:	c5 f2 51 d8          	vsqrtss xmm3,xmm1,xmm0
     8:	c5 f2 51 e0          	vsqrtss xmm4,xmm1,xmm0
     c:	c5 f2 51 e8          	vsqrtss xmm5,xmm1,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x3f8000003f800000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 4.1
  • Core cycles: 28.11
  • Reference cycles: 28.1
  • UOPS_EXECUTED.CORE: 4.05
  • RETIRE_SLOTS: 4.05
  • UOPS_MITE: 0.04
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 4.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.05
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 7.89
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With unroll_count=100 and no inner loop

• Code:

     0:	c5 f2 51 d0          	vsqrtss xmm2,xmm1,xmm0
     4:	c5 f2 51 d8          	vsqrtss xmm3,xmm1,xmm0
     8:	c5 f2 51 e0          	vsqrtss xmm4,xmm1,xmm0
     c:	c5 f2 51 e8          	vsqrtss xmm5,xmm1,xmm0
    10:	c5 f2 51 f0          	vsqrtss xmm6,xmm1,xmm0
    14:	c5 f2 51 f8          	vsqrtss xmm7,xmm1,xmm0
    18:	c5 72 51 c0          	vsqrtss xmm8,xmm1,xmm0
    1c:	c5 72 51 c8          	vsqrtss xmm9,xmm1,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x3f8000003f800000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 8.0
  • Core cycles: 56.24
  • Reference cycles: 56.05
  • UOPS_EXECUTED.CORE: 8.0
  • RETIRE_SLOTS: 8.0
  • UOPS_MITE: 8.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 8.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 15.78
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	c5 f2 51 d0          	vsqrtss xmm2,xmm1,xmm0
     4:	c5 f2 51 d8          	vsqrtss xmm3,xmm1,xmm0
     8:	c5 f2 51 e0          	vsqrtss xmm4,xmm1,xmm0
     c:	c5 f2 51 e8          	vsqrtss xmm5,xmm1,xmm0
    10:	c5 f2 51 f0          	vsqrtss xmm6,xmm1,xmm0
    14:	c5 f2 51 f8          	vsqrtss xmm7,xmm1,xmm0
    18:	c5 72 51 c0          	vsqrtss xmm8,xmm1,xmm0
    1c:	c5 72 51 c8          	vsqrtss xmm9,xmm1,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x3f8000003f800000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 10.0
  • Core cycles: 56.35
  • Reference cycles: 56.32
  • UOPS_EXECUTED.CORE: 9.0
  • RETIRE_SLOTS: 9.0
  • UOPS_MITE: 0.01
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 8.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 15.67
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

• Code:

     0:	c5 f2 51 d0          	vsqrtss xmm2,xmm1,xmm0
     4:	c5 f2 51 d8          	vsqrtss xmm3,xmm1,xmm0
     8:	c5 f2 51 e0          	vsqrtss xmm4,xmm1,xmm0
     c:	c5 f2 51 e8          	vsqrtss xmm5,xmm1,xmm0
    10:	c5 f2 51 f0          	vsqrtss xmm6,xmm1,xmm0
    14:	c5 f2 51 f8          	vsqrtss xmm7,xmm1,xmm0
    18:	c5 72 51 c0          	vsqrtss xmm8,xmm1,xmm0
    1c:	c5 72 51 c8          	vsqrtss xmm9,xmm1,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x3f8000003f800000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 8.2
  • Core cycles: 56.23
  • Reference cycles: 56.25
  • UOPS_EXECUTED.CORE: 8.1
  • RETIRE_SLOTS: 8.1
  • UOPS_MITE: 0.08
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 8.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.1
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 15.79
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.02

With unroll_count=500 and no inner loop

• Code:

     0:	c5 f2 51 d0          	vsqrtss xmm2,xmm1,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x72d30ff172d30ff1;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 1.0
  • Core cycles: 7.09
  • Reference cycles: 7.05
  • UOPS_EXECUTED.CORE: 1.0
  • RETIRE_SLOTS: 1.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 4.91
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.25

With unroll_count=500 and no inner loop

• Code:

     0:	c5 f2 51 d0          	vsqrtss xmm2,xmm1,xmm0
     4:	0f ae e8             	lfence 
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x72d30ff172d30ff1;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 21.25
  • Reference cycles: 21.25
  • UOPS_EXECUTED.CORE: 1.0
  • RETIRE_SLOTS: 3.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 2.0
  • UOPS_PORT_0: 1.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 12.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=10

• Code:

     0:	c5 f2 51 d0          	vsqrtss xmm2,xmm1,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x72d30ff172d30ff1;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 1.2
  • Core cycles: 7.08
  • Reference cycles: 7.08
  • UOPS_EXECUTED.CORE: 1.1
  • RETIRE_SLOTS: 1.1
  • UOPS_MITE: 0.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.1
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 4.92
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

• Code:

     0:	c5 f2 51 d0          	vsqrtss xmm2,xmm1,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x72d30ff172d30ff1;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 1.02
  • Core cycles: 7.08
  • Reference cycles: 7.08
  • UOPS_EXECUTED.CORE: 1.01
  • RETIRE_SLOTS: 1.01
  • UOPS_MITE: 0.01
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.01
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 4.92
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With unroll_count=200 and no inner loop

• Code:

     0:	c5 f2 51 d0          	vsqrtss xmm2,xmm1,xmm0
     4:	c5 f2 51 d8          	vsqrtss xmm3,xmm1,xmm0
     8:	c5 f2 51 e0          	vsqrtss xmm4,xmm1,xmm0
     c:	c5 f2 51 e8          	vsqrtss xmm5,xmm1,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x72d30ff172d30ff1;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 28.44
  • Reference cycles: 28.48
  • UOPS_EXECUTED.CORE: 4.0
  • RETIRE_SLOTS: 4.0
  • UOPS_MITE: 4.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 4.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 19.63
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

• Code:

     0:	c5 f2 51 d0          	vsqrtss xmm2,xmm1,xmm0
     4:	c5 f2 51 d8          	vsqrtss xmm3,xmm1,xmm0
     8:	c5 f2 51 e0          	vsqrtss xmm4,xmm1,xmm0
     c:	c5 f2 51 e8          	vsqrtss xmm5,xmm1,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x72d30ff172d30ff1;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 28.41
  • Reference cycles: 28.42
  • UOPS_EXECUTED.CORE: 4.5
  • RETIRE_SLOTS: 4.5
  • UOPS_MITE: 0.01
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 4.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.5
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 19.58
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

• Code:

     0:	c5 f2 51 d0          	vsqrtss xmm2,xmm1,xmm0
     4:	c5 f2 51 d8          	vsqrtss xmm3,xmm1,xmm0
     8:	c5 f2 51 e0          	vsqrtss xmm4,xmm1,xmm0
     c:	c5 f2 51 e8          	vsqrtss xmm5,xmm1,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x72d30ff172d30ff1;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 4.1
  • Core cycles: 28.32
  • Reference cycles: 28.31
  • UOPS_EXECUTED.CORE: 4.05
  • RETIRE_SLOTS: 4.05
  • UOPS_MITE: 0.04
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 4.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.05
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 19.7
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With unroll_count=100 and no inner loop

• Code:

     0:	c5 f2 51 d0          	vsqrtss xmm2,xmm1,xmm0
     4:	c5 f2 51 d8          	vsqrtss xmm3,xmm1,xmm0
     8:	c5 f2 51 e0          	vsqrtss xmm4,xmm1,xmm0
     c:	c5 f2 51 e8          	vsqrtss xmm5,xmm1,xmm0
    10:	c5 f2 51 f0          	vsqrtss xmm6,xmm1,xmm0
    14:	c5 f2 51 f8          	vsqrtss xmm7,xmm1,xmm0
    18:	c5 72 51 c0          	vsqrtss xmm8,xmm1,xmm0
    1c:	c5 72 51 c8          	vsqrtss xmm9,xmm1,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x72d30ff172d30ff1;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 8.0
  • Core cycles: 56.85
  • Reference cycles: 57.01
  • UOPS_EXECUTED.CORE: 8.0
  • RETIRE_SLOTS: 8.0
  • UOPS_MITE: 8.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 8.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 39.24
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	c5 f2 51 d0          	vsqrtss xmm2,xmm1,xmm0
     4:	c5 f2 51 d8          	vsqrtss xmm3,xmm1,xmm0
     8:	c5 f2 51 e0          	vsqrtss xmm4,xmm1,xmm0
     c:	c5 f2 51 e8          	vsqrtss xmm5,xmm1,xmm0
    10:	c5 f2 51 f0          	vsqrtss xmm6,xmm1,xmm0
    14:	c5 f2 51 f8          	vsqrtss xmm7,xmm1,xmm0
    18:	c5 72 51 c0          	vsqrtss xmm8,xmm1,xmm0
    1c:	c5 72 51 c8          	vsqrtss xmm9,xmm1,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x72d30ff172d30ff1;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 10.0
  • Core cycles: 56.82
  • Reference cycles: 56.81
  • UOPS_EXECUTED.CORE: 9.0
  • RETIRE_SLOTS: 9.0
  • UOPS_MITE: 0.01
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 8.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 39.15
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

• Code:

     0:	c5 f2 51 d0          	vsqrtss xmm2,xmm1,xmm0
     4:	c5 f2 51 d8          	vsqrtss xmm3,xmm1,xmm0
     8:	c5 f2 51 e0          	vsqrtss xmm4,xmm1,xmm0
     c:	c5 f2 51 e8          	vsqrtss xmm5,xmm1,xmm0
    10:	c5 f2 51 f0          	vsqrtss xmm6,xmm1,xmm0
    14:	c5 f2 51 f8          	vsqrtss xmm7,xmm1,xmm0
    18:	c5 72 51 c0          	vsqrtss xmm8,xmm1,xmm0
    1c:	c5 72 51 c8          	vsqrtss xmm9,xmm1,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x72d30ff172d30ff1;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 8.2
  • Core cycles: 56.61
  • Reference cycles: 56.63
  • UOPS_EXECUTED.CORE: 8.1
  • RETIRE_SLOTS: 8.1
  • UOPS_MITE: 0.08
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 8.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.1
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 39.39
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.02