VMULPS (YMM, YMM, YMM) - Throughput and Uops (IACA 2.3)

With different registers for different operands

With 1 independent instruction

Throughput Analysis Report
--------------------------
Block Throughput: 0.50 Cycles       Throughput Bottleneck: FrontEnd

Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |  6   |  7   |
---------------------------------------------------------------------------------------
| Cycles | 0.5    0.0  | 0.5  | 0.0    0.0  | 0.0    0.0  | 0.0  | 0.0  | 0.0  | 0.0  |
---------------------------------------------------------------------------------------


| Num Of |                    Ports pressure in cycles                     |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |  6  |  7  |    |
---------------------------------------------------------------------------------
|   1    | 0.5       | 0.5 |           |           |     |     |     |     | CP | vmulps ymm0, ymm1, ymm2
Total Num Of Uops: 1

With 11 independent instructions

Throughput Analysis Report
--------------------------
Block Throughput: 5.50 Cycles       Throughput Bottleneck: Backend. Port0, Port1

Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |  6   |  7   |
---------------------------------------------------------------------------------------
| Cycles | 5.5    0.0  | 5.5  | 0.0    0.0  | 0.0    0.0  | 0.0  | 0.0  | 0.0  | 0.0  |
---------------------------------------------------------------------------------------


| Num Of |                    Ports pressure in cycles                     |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |  6  |  7  |    |
---------------------------------------------------------------------------------
|   1    | 0.5       | 0.5 |           |           |     |     |     |     | CP | vmulps ymm0, ymm1, ymm2
|   1    | 0.5       | 0.5 |           |           |     |     |     |     | CP | vmulps ymm3, ymm1, ymm2
|   1    | 0.5       | 0.5 |           |           |     |     |     |     | CP | vmulps ymm4, ymm1, ymm2
|   1    | 0.5       | 0.5 |           |           |     |     |     |     | CP | vmulps ymm5, ymm1, ymm2
|   1    | 0.5       | 0.5 |           |           |     |     |     |     | CP | vmulps ymm6, ymm1, ymm2
|   1    | 0.5       | 0.5 |           |           |     |     |     |     | CP | vmulps ymm7, ymm1, ymm2
|   1    | 0.5       | 0.5 |           |           |     |     |     |     | CP | vmulps ymm8, ymm1, ymm2
|   1    | 0.5       | 0.5 |           |           |     |     |     |     | CP | vmulps ymm9, ymm1, ymm2
|   1    | 0.5       | 0.5 |           |           |     |     |     |     | CP | vmulps ymm10, ymm1, ymm2
|   1    | 0.5       | 0.5 |           |           |     |     |     |     | CP | vmulps ymm11, ymm1, ymm2
|   1    | 0.5       | 0.5 |           |           |     |     |     |     | CP | vmulps ymm12, ymm1, ymm2
Total Num Of Uops: 11

With the same register for for different operands

Throughput Analysis Report
--------------------------
Block Throughput: 4.76 Cycles       Throughput Bottleneck: FrontEnd

Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |  6   |  7   |
---------------------------------------------------------------------------------------
| Cycles | 0.5    0.0  | 0.5  | 0.0    0.0  | 0.0    0.0  | 0.0  | 0.0  | 0.0  | 0.0  |
---------------------------------------------------------------------------------------


| Num Of |                    Ports pressure in cycles                     |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |  6  |  7  |    |
---------------------------------------------------------------------------------
|   1    | 0.5       | 0.5 |           |           |     |     |     |     | CP | vmulps ymm0, ymm0, ymm0
Total Num Of Uops: 1