SQRTSD (XMM, XMM)

With unroll_count=500 and no inner loop

Code:

   0:	f2 0f 51 d0          	sqrtsd xmm2,xmm0

Init:

VZEROALL;
MOV RAX, 0x3ff0000000000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 10.02
- Reference cycles: 8.86
- UOPS_EXECUTED.CORE: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 9.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With unroll_count=500 and no inner loop

Code:

   0:	f2 0f 51 d0          	sqrtsd xmm2,xmm0
   4:	0f ae e8             	lfence

Init:

VZEROALL;
MOV RAX, 0x3ff0000000000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 18.5
- Reference cycles: 16.45
- UOPS_EXECUTED.CORE: 1.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 1.0
- UOPS_MS: 2.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 9.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=10

Code:

   0:	f2 0f 51 d0          	sqrtsd xmm2,xmm0

Init:

VZEROALL;
MOV RAX, 0x3ff0000000000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 10.02
- Reference cycles: 8.91
- UOPS_EXECUTED.CORE: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 9.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	f2 0f 51 d0          	sqrtsd xmm2,xmm0

Init:

VZEROALL;
MOV RAX, 0x3ff0000000000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 10.01
- Reference cycles: 8.9
- UOPS_EXECUTED.CORE: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 9.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	f2 0f 51 d0          	sqrtsd xmm2,xmm0
   4:	f2 0f 51 d8          	sqrtsd xmm3,xmm0
   8:	f2 0f 51 e0          	sqrtsd xmm4,xmm0
   c:	f2 0f 51 e8          	sqrtsd xmm5,xmm0

Init:

VZEROALL;
MOV RAX, 0x3ff0000000000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 32.1
- Reference cycles: 28.64
- UOPS_EXECUTED.CORE: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 4.58
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	f2 0f 51 d0          	sqrtsd xmm2,xmm0
   4:	f2 0f 51 d8          	sqrtsd xmm3,xmm0
   8:	f2 0f 51 e0          	sqrtsd xmm4,xmm0
   c:	f2 0f 51 e8          	sqrtsd xmm5,xmm0

Init:

VZEROALL;
MOV RAX, 0x3ff0000000000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 32.11
- Reference cycles: 28.54
- UOPS_EXECUTED.CORE: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 4.72
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	f2 0f 51 d0          	sqrtsd xmm2,xmm0
   4:	f2 0f 51 d8          	sqrtsd xmm3,xmm0
   8:	f2 0f 51 e0          	sqrtsd xmm4,xmm0
   c:	f2 0f 51 e8          	sqrtsd xmm5,xmm0

Init:

VZEROALL;
MOV RAX, 0x3ff0000000000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 32.06
- Reference cycles: 28.5
- UOPS_EXECUTED.CORE: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 4.44
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	f2 0f 51 d0          	sqrtsd xmm2,xmm0
   4:	f2 0f 51 d8          	sqrtsd xmm3,xmm0
   8:	f2 0f 51 e0          	sqrtsd xmm4,xmm0
   c:	f2 0f 51 e8          	sqrtsd xmm5,xmm0
  10:	f2 0f 51 f0          	sqrtsd xmm6,xmm0
  14:	f2 0f 51 f8          	sqrtsd xmm7,xmm0
  18:	f2 44 0f 51 c0       	sqrtsd xmm8,xmm0
  1d:	f2 44 0f 51 c8       	sqrtsd xmm9,xmm0

Init:

VZEROALL;
MOV RAX, 0x3ff0000000000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 64.24
- Reference cycles: 57.01
- UOPS_EXECUTED.CORE: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 9.23
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

Code:

   0:	f2 0f 51 d0          	sqrtsd xmm2,xmm0
   4:	f2 0f 51 d8          	sqrtsd xmm3,xmm0
   8:	f2 0f 51 e0          	sqrtsd xmm4,xmm0
   c:	f2 0f 51 e8          	sqrtsd xmm5,xmm0
  10:	f2 0f 51 f0          	sqrtsd xmm6,xmm0
  14:	f2 0f 51 f8          	sqrtsd xmm7,xmm0
  18:	f2 44 0f 51 c0       	sqrtsd xmm8,xmm0
  1d:	f2 44 0f 51 c8       	sqrtsd xmm9,xmm0

Init:

VZEROALL;
MOV RAX, 0x3ff0000000000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 64.2
- Reference cycles: 57.07
- UOPS_EXECUTED.CORE: 9.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 9.43
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	f2 0f 51 d0          	sqrtsd xmm2,xmm0
   4:	f2 0f 51 d8          	sqrtsd xmm3,xmm0
   8:	f2 0f 51 e0          	sqrtsd xmm4,xmm0
   c:	f2 0f 51 e8          	sqrtsd xmm5,xmm0
  10:	f2 0f 51 f0          	sqrtsd xmm6,xmm0
  14:	f2 0f 51 f8          	sqrtsd xmm7,xmm0
  18:	f2 44 0f 51 c0       	sqrtsd xmm8,xmm0
  1d:	f2 44 0f 51 c8       	sqrtsd xmm9,xmm0

Init:

VZEROALL;
MOV RAX, 0x3ff0000000000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 64.13
- Reference cycles: 57.02
- UOPS_EXECUTED.CORE: 8.1
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 8.89
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

Slow division

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	f2 0f 51 d0          	sqrtsd xmm2,xmm0

Init:

VZEROALL;
MOV RAX, 0x465a61fe1acdc21c;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 20.02
- Reference cycles: 17.79
- UOPS_EXECUTED.CORE: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 19.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With unroll_count=500 and no inner loop

Code:

   0:	f2 0f 51 d0          	sqrtsd xmm2,xmm0
   4:	0f ae e8             	lfence

Init:

VZEROALL;
MOV RAX, 0x465a61fe1acdc21c;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 28.5
- Reference cycles: 25.33
- UOPS_EXECUTED.CORE: 1.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 1.0
- UOPS_MS: 2.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 19.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=10

Code:

   0:	f2 0f 51 d0          	sqrtsd xmm2,xmm0

Init:

VZEROALL;
MOV RAX, 0x465a61fe1acdc21c;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 20.02
- Reference cycles: 17.79
- UOPS_EXECUTED.CORE: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 19.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	f2 0f 51 d0          	sqrtsd xmm2,xmm0

Init:

VZEROALL;
MOV RAX, 0x465a61fe1acdc21c;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 20.01
- Reference cycles: 18.3
- UOPS_EXECUTED.CORE: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 19.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	f2 0f 51 d0          	sqrtsd xmm2,xmm0
   4:	f2 0f 51 d8          	sqrtsd xmm3,xmm0
   8:	f2 0f 51 e0          	sqrtsd xmm4,xmm0
   c:	f2 0f 51 e8          	sqrtsd xmm5,xmm0

Init:

VZEROALL;
MOV RAX, 0x465a61fe1acdc21c;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 56.11
- Reference cycles: 49.87
- UOPS_EXECUTED.CORE: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 19.92
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	f2 0f 51 d0          	sqrtsd xmm2,xmm0
   4:	f2 0f 51 d8          	sqrtsd xmm3,xmm0
   8:	f2 0f 51 e0          	sqrtsd xmm4,xmm0
   c:	f2 0f 51 e8          	sqrtsd xmm5,xmm0

Init:

VZEROALL;
MOV RAX, 0x465a61fe1acdc21c;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 56.11
- Reference cycles: 49.87
- UOPS_EXECUTED.CORE: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 19.9
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	f2 0f 51 d0          	sqrtsd xmm2,xmm0
   4:	f2 0f 51 d8          	sqrtsd xmm3,xmm0
   8:	f2 0f 51 e0          	sqrtsd xmm4,xmm0
   c:	f2 0f 51 e8          	sqrtsd xmm5,xmm0

Init:

VZEROALL;
MOV RAX, 0x465a61fe1acdc21c;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 56.06
- Reference cycles: 49.83
- UOPS_EXECUTED.CORE: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 19.95
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	f2 0f 51 d0          	sqrtsd xmm2,xmm0
   4:	f2 0f 51 d8          	sqrtsd xmm3,xmm0
   8:	f2 0f 51 e0          	sqrtsd xmm4,xmm0
   c:	f2 0f 51 e8          	sqrtsd xmm5,xmm0
  10:	f2 0f 51 f0          	sqrtsd xmm6,xmm0
  14:	f2 0f 51 f8          	sqrtsd xmm7,xmm0
  18:	f2 44 0f 51 c0       	sqrtsd xmm8,xmm0
  1d:	f2 44 0f 51 c8       	sqrtsd xmm9,xmm0

Init:

VZEROALL;
MOV RAX, 0x465a61fe1acdc21c;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 112.22
- Reference cycles: 99.68
- UOPS_EXECUTED.CORE: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 39.83
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

Code:

   0:	f2 0f 51 d0          	sqrtsd xmm2,xmm0
   4:	f2 0f 51 d8          	sqrtsd xmm3,xmm0
   8:	f2 0f 51 e0          	sqrtsd xmm4,xmm0
   c:	f2 0f 51 e8          	sqrtsd xmm5,xmm0
  10:	f2 0f 51 f0          	sqrtsd xmm6,xmm0
  14:	f2 0f 51 f8          	sqrtsd xmm7,xmm0
  18:	f2 44 0f 51 c0       	sqrtsd xmm8,xmm0
  1d:	f2 44 0f 51 c8       	sqrtsd xmm9,xmm0

Init:

VZEROALL;
MOV RAX, 0x465a61fe1acdc21c;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 112.21
- Reference cycles: 99.74
- UOPS_EXECUTED.CORE: 9.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 39.81
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	f2 0f 51 d0          	sqrtsd xmm2,xmm0
   4:	f2 0f 51 d8          	sqrtsd xmm3,xmm0
   8:	f2 0f 51 e0          	sqrtsd xmm4,xmm0
   c:	f2 0f 51 e8          	sqrtsd xmm5,xmm0
  10:	f2 0f 51 f0          	sqrtsd xmm6,xmm0
  14:	f2 0f 51 f8          	sqrtsd xmm7,xmm0
  18:	f2 44 0f 51 c0       	sqrtsd xmm8,xmm0
  1d:	f2 44 0f 51 c8       	sqrtsd xmm9,xmm0

Init:

VZEROALL;
MOV RAX, 0x465a61fe1acdc21c;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 112.12
- Reference cycles: 99.66
- UOPS_EXECUTED.CORE: 8.1
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 39.9
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

SQRTSD (XMM, XMM) - Throughput and Uops

Fast division

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

Slow division

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10