SHLX (R64, R64, R64) - Throughput and Uops (IACA 2.1)
With different registers for different operands
With 1 independent instruction
Throughput Analysis Report
--------------------------
Block Throughput: 0.50 Cycles Throughput Bottleneck: Port0, Port6
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 0.5 0.0 | 0.0 | 0.0 0.0 | 0.0 0.0 | 0.0 | 0.0 | 0.5 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 1 | 0.5 | | | | | | 0.5 | | CP | shlx r8, r9, r10
Total Num Of Uops: 1
With 11 independent instructions
Throughput Analysis Report
--------------------------
Block Throughput: 5.50 Cycles Throughput Bottleneck: Port0, Port6
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 5.5 0.0 | 0.0 | 0.0 0.0 | 0.0 0.0 | 0.0 | 0.0 | 5.5 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 1 | 0.5 | | | | | | 0.5 | | CP | shlx r8, r9, r10
| 1 | 0.5 | | | | | | 0.5 | | CP | shlx r11, r9, r10
| 1 | 0.5 | | | | | | 0.5 | | CP | shlx r12, r9, r10
| 1 | 0.5 | | | | | | 0.5 | | CP | shlx r13, r9, r10
| 1 | 0.5 | | | | | | 0.5 | | CP | shlx r14, r9, r10
| 1 | 0.5 | | | | | | 0.5 | | CP | shlx rbx, r9, r10
| 1 | 0.5 | | | | | | 0.5 | | CP | shlx rcx, r9, r10
| 1 | 0.5 | | | | | | 0.5 | | CP | shlx rdx, r9, r10
| 1 | 0.5 | | | | | | 0.5 | | CP | shlx rdi, r9, r10
| 1 | 0.5 | | | | | | 0.5 | | CP | shlx rsi, r9, r10
| 1 | 0.5 | | | | | | 0.5 | | CP | shlx rbp, r9, r10
Total Num Of Uops: 11
With the same register for for different operands
With 1 independent instruction
Throughput Analysis Report
--------------------------
Block Throughput: 1.00 Cycles Throughput Bottleneck: InterIteration
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 0.5 0.0 | 0.0 | 0.0 0.0 | 0.0 0.0 | 0.0 | 0.0 | 0.5 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 1 | 0.5 | | | | | | 0.5 | | CP | shlx r8, r8, r8
Total Num Of Uops: 1
With 13 independent instructions
Throughput Analysis Report
--------------------------
Block Throughput: 6.50 Cycles Throughput Bottleneck: Port0, Port6
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 6.5 0.0 | 0.0 | 0.0 0.0 | 0.0 0.0 | 0.0 | 0.0 | 6.5 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 1 | 0.5 | | | | | | 0.5 | | CP | shlx r8, r8, r8
| 1 | 0.5 | | | | | | 0.5 | | CP | shlx r9, r9, r9
| 1 | 0.5 | | | | | | 0.5 | | CP | shlx r10, r10, r10
| 1 | 0.5 | | | | | | 0.5 | | CP | shlx r11, r11, r11
| 1 | 0.5 | | | | | | 0.5 | | CP | shlx r12, r12, r12
| 1 | 0.5 | | | | | | 0.5 | | CP | shlx r13, r13, r13
| 1 | 0.5 | | | | | | 0.5 | | CP | shlx r14, r14, r14
| 1 | 0.5 | | | | | | 0.5 | | CP | shlx rbx, rbx, rbx
| 1 | 0.5 | | | | | | 0.5 | | CP | shlx rcx, rcx, rcx
| 1 | 0.5 | | | | | | 0.5 | | CP | shlx rdx, rdx, rdx
| 1 | 0.5 | | | | | | 0.5 | | CP | shlx rdi, rdi, rdi
| 1 | 0.5 | | | | | | 0.5 | | CP | shlx rsi, rsi, rsi
| 1 | 0.5 | | | | | | 0.5 | | CP | shlx rbp, rbp, rbp
Total Num Of Uops: 13
With the -no_interiteration flag
Throughput Analysis Report
--------------------------
Block Throughput: 0.50 Cycles Throughput Bottleneck: Port0, Port6
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 0.5 0.0 | 0.0 | 0.0 0.0 | 0.0 0.0 | 0.0 | 0.0 | 0.5 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 1 | 0.5 | | | | | | 0.5 | | CP | shlx r8, r9, r10
Total Num Of Uops: 1