SFENCE

With unroll_count=500 and no inner loop

Code:
```
   0:	0f ae f8             	sfence 
```
Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 6.0
- Reference cycles: 5.34
- UOPS_EXECUTED.CORE: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 1.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	0f ae f8             	sfence 
   3:	90                   	nop

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 6.0
- Reference cycles: 5.34
- UOPS_EXECUTED.CORE: 2.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 3.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.25
- UOPS_PORT_3: 0.75
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:
```
   0:	0f ae f8             	sfence 
```
Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 5.98
- Reference cycles: 5.32
- UOPS_EXECUTED.CORE: 2.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 2.11
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.48
- UOPS_PORT_3: 0.53
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.1

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	40 0f ae f8          	rex sfence

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 5.98
- Reference cycles: 5.32
- UOPS_EXECUTED.CORE: 2.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:
```
   0:	0f ae f8             	sfence 
```
Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 5.98
- Reference cycles: 5.32
- UOPS_EXECUTED.CORE: 2.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 2.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.75
- UOPS_PORT_3: 0.25
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.01

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	40 0f ae f8          	rex sfence

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 5.98
- Reference cycles: 5.32
- UOPS_EXECUTED.CORE: 2.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.75
- UOPS_PORT_3: 0.25
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

SFENCE - Throughput and Uops

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With loop_count=1000 and unroll_count=10

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

With loop_count=100 and unroll_count=100

With loop_count=100, unroll_count=100, and padding (redundant prefixes)