PDEP (R64, R64, M64)

With unroll_count=500 and no inner loop

Code:

   0:	c4 42 b3 f5 06       	pdep   r8,r9,QWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 1.0
- UOPS_EXECUTED.CORE: 2.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	c4 42 b3 f5 06       	pdep   r8,r9,QWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 1.0
- UOPS_EXECUTED.CORE: 2.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	c4 42 b3 f5 06       	pdep   r8,r9,QWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 1.0
- UOPS_EXECUTED.CORE: 2.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	c4 42 b3 f5 06       	pdep   r8,r9,QWORD PTR [r14]
   5:	c4 42 b3 f5 56 08    	pdep   r10,r9,QWORD PTR [r14+0x8]
   b:	c4 42 b3 f5 5e 10    	pdep   r11,r9,QWORD PTR [r14+0x10]
  11:	c4 42 b3 f5 66 18    	pdep   r12,r9,QWORD PTR [r14+0x18]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 4.0
- UOPS_EXECUTED.CORE: 8.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	c4 42 b3 f5 06       	pdep   r8,r9,QWORD PTR [r14]
   5:	c4 42 b3 f5 56 08    	pdep   r10,r9,QWORD PTR [r14+0x8]
   b:	c4 42 b3 f5 5e 10    	pdep   r11,r9,QWORD PTR [r14+0x10]
  11:	c4 42 b3 f5 66 18    	pdep   r12,r9,QWORD PTR [r14+0x18]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.01
- Reference cycles: 4.01
- UOPS_EXECUTED.CORE: 8.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	c4 42 b3 f5 06       	pdep   r8,r9,QWORD PTR [r14]
   5:	c4 42 b3 f5 56 08    	pdep   r10,r9,QWORD PTR [r14+0x8]
   b:	c4 42 b3 f5 5e 10    	pdep   r11,r9,QWORD PTR [r14+0x10]
  11:	c4 42 b3 f5 66 18    	pdep   r12,r9,QWORD PTR [r14+0x18]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.01
- Reference cycles: 4.01
- UOPS_EXECUTED.CORE: 8.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 7 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 42 b3 f5 06       	pdep   r8,r9,QWORD PTR [r14]
   5:	c4 42 b3 f5 56 08    	pdep   r10,r9,QWORD PTR [r14+0x8]
   b:	c4 42 b3 f5 5e 10    	pdep   r11,r9,QWORD PTR [r14+0x10]
  11:	c4 42 b3 f5 66 18    	pdep   r12,r9,QWORD PTR [r14+0x18]
  17:	c4 c2 b3 f5 5e 20    	pdep   rbx,r9,QWORD PTR [r14+0x20]
  1d:	c4 c2 b3 f5 4e 28    	pdep   rcx,r9,QWORD PTR [r14+0x28]
  23:	c4 c2 b3 f5 56 30    	pdep   rdx,r9,QWORD PTR [r14+0x30]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 7.0
- Reference cycles: 6.99
- UOPS_EXECUTED.CORE: 14.0
- RETIRE_SLOTS: 7.0
- UOPS_MITE: 7.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 7.0
- UOPS_PORT_2: 3.5
- UOPS_PORT_3: 3.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.75

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 42 b3 f5 06       	pdep   r8,r9,QWORD PTR [r14]
   5:	c4 42 b3 f5 56 08    	pdep   r10,r9,QWORD PTR [r14+0x8]
   b:	c4 42 b3 f5 5e 10    	pdep   r11,r9,QWORD PTR [r14+0x10]
  11:	c4 42 b3 f5 66 18    	pdep   r12,r9,QWORD PTR [r14+0x18]
  17:	c4 c2 b3 f5 5e 20    	pdep   rbx,r9,QWORD PTR [r14+0x20]
  1d:	c4 c2 b3 f5 4e 28    	pdep   rcx,r9,QWORD PTR [r14+0x28]
  23:	c4 c2 b3 f5 56 30    	pdep   rdx,r9,QWORD PTR [r14+0x30]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 7.01
- Reference cycles: 7.02
- UOPS_EXECUTED.CORE: 15.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 7.0
- UOPS_PORT_2: 3.5
- UOPS_PORT_3: 3.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	c4 42 b3 f5 06       	pdep   r8,r9,QWORD PTR [r14]
   5:	c4 42 b3 f5 56 08    	pdep   r10,r9,QWORD PTR [r14+0x8]
   b:	c4 42 b3 f5 5e 10    	pdep   r11,r9,QWORD PTR [r14+0x10]
  11:	c4 42 b3 f5 66 18    	pdep   r12,r9,QWORD PTR [r14+0x18]
  17:	c4 c2 b3 f5 5e 20    	pdep   rbx,r9,QWORD PTR [r14+0x20]
  1d:	c4 c2 b3 f5 4e 28    	pdep   rcx,r9,QWORD PTR [r14+0x28]
  23:	c4 c2 b3 f5 56 30    	pdep   rdx,r9,QWORD PTR [r14+0x30]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 7.2
- Core cycles: 7.01
- Reference cycles: 7.02
- UOPS_EXECUTED.CORE: 14.11
- RETIRE_SLOTS: 7.1
- UOPS_MITE: 0.07
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 7.0
- UOPS_PORT_2: 3.5
- UOPS_PORT_3: 3.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	c4 02 b3 f5 04 2e    	pdep   r8,r9,QWORD PTR [r14+r13*1]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.99
- UOPS_EXECUTED.CORE: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	c4 02 b3 f5 04 2e    	pdep   r8,r9,QWORD PTR [r14+r13*1]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 1.0
- UOPS_EXECUTED.CORE: 2.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	c4 02 b3 f5 04 2e    	pdep   r8,r9,QWORD PTR [r14+r13*1]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 1.0
- UOPS_EXECUTED.CORE: 2.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	c4 02 b3 f5 04 2e    	pdep   r8,r9,QWORD PTR [r14+r13*1]
   6:	c4 02 b3 f5 54 2e 08 	pdep   r10,r9,QWORD PTR [r14+r13*1+0x8]
   d:	c4 02 b3 f5 5c 2e 10 	pdep   r11,r9,QWORD PTR [r14+r13*1+0x10]
  14:	c4 02 b3 f5 64 2e 18 	pdep   r12,r9,QWORD PTR [r14+r13*1+0x18]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 4.0
- UOPS_EXECUTED.CORE: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 2.01
- UOPS_PORT_3: 2.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	c4 02 b3 f5 04 2e    	pdep   r8,r9,QWORD PTR [r14+r13*1]
   6:	c4 02 b3 f5 54 2e 08 	pdep   r10,r9,QWORD PTR [r14+r13*1+0x8]
   d:	c4 02 b3 f5 5c 2e 10 	pdep   r11,r9,QWORD PTR [r14+r13*1+0x10]
  14:	c4 02 b3 f5 64 2e 18 	pdep   r12,r9,QWORD PTR [r14+r13*1+0x18]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.01
- Reference cycles: 4.01
- UOPS_EXECUTED.CORE: 8.5
- RETIRE_SLOTS: 8.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	c4 02 b3 f5 04 2e    	pdep   r8,r9,QWORD PTR [r14+r13*1]
   6:	c4 02 b3 f5 54 2e 08 	pdep   r10,r9,QWORD PTR [r14+r13*1+0x8]
   d:	c4 02 b3 f5 5c 2e 10 	pdep   r11,r9,QWORD PTR [r14+r13*1+0x10]
  14:	c4 02 b3 f5 64 2e 18 	pdep   r12,r9,QWORD PTR [r14+r13*1+0x18]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.01
- Reference cycles: 4.01
- UOPS_EXECUTED.CORE: 8.05
- RETIRE_SLOTS: 8.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 7 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 02 b3 f5 04 2e    	pdep   r8,r9,QWORD PTR [r14+r13*1]
   6:	c4 02 b3 f5 54 2e 08 	pdep   r10,r9,QWORD PTR [r14+r13*1+0x8]
   d:	c4 02 b3 f5 5c 2e 10 	pdep   r11,r9,QWORD PTR [r14+r13*1+0x10]
  14:	c4 02 b3 f5 64 2e 18 	pdep   r12,r9,QWORD PTR [r14+r13*1+0x18]
  1b:	c4 82 b3 f5 5c 2e 20 	pdep   rbx,r9,QWORD PTR [r14+r13*1+0x20]
  22:	c4 82 b3 f5 4c 2e 28 	pdep   rcx,r9,QWORD PTR [r14+r13*1+0x28]
  29:	c4 82 b3 f5 54 2e 30 	pdep   rdx,r9,QWORD PTR [r14+r13*1+0x30]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 7.0
- Reference cycles: 7.04
- UOPS_EXECUTED.CORE: 14.0
- RETIRE_SLOTS: 14.0
- UOPS_MITE: 7.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 7.0
- UOPS_PORT_2: 3.51
- UOPS_PORT_3: 3.51
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.75

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 02 b3 f5 04 2e    	pdep   r8,r9,QWORD PTR [r14+r13*1]
   6:	c4 02 b3 f5 54 2e 08 	pdep   r10,r9,QWORD PTR [r14+r13*1+0x8]
   d:	c4 02 b3 f5 5c 2e 10 	pdep   r11,r9,QWORD PTR [r14+r13*1+0x10]
  14:	c4 02 b3 f5 64 2e 18 	pdep   r12,r9,QWORD PTR [r14+r13*1+0x18]
  1b:	c4 82 b3 f5 5c 2e 20 	pdep   rbx,r9,QWORD PTR [r14+r13*1+0x20]
  22:	c4 82 b3 f5 4c 2e 28 	pdep   rcx,r9,QWORD PTR [r14+r13*1+0x28]
  29:	c4 82 b3 f5 54 2e 30 	pdep   rdx,r9,QWORD PTR [r14+r13*1+0x30]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 7.01
- Reference cycles: 7.02
- UOPS_EXECUTED.CORE: 15.0
- RETIRE_SLOTS: 15.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 7.0
- UOPS_PORT_2: 3.5
- UOPS_PORT_3: 3.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	c4 02 b3 f5 04 2e    	pdep   r8,r9,QWORD PTR [r14+r13*1]
   6:	c4 02 b3 f5 54 2e 08 	pdep   r10,r9,QWORD PTR [r14+r13*1+0x8]
   d:	c4 02 b3 f5 5c 2e 10 	pdep   r11,r9,QWORD PTR [r14+r13*1+0x10]
  14:	c4 02 b3 f5 64 2e 18 	pdep   r12,r9,QWORD PTR [r14+r13*1+0x18]
  1b:	c4 82 b3 f5 5c 2e 20 	pdep   rbx,r9,QWORD PTR [r14+r13*1+0x20]
  22:	c4 82 b3 f5 4c 2e 28 	pdep   rcx,r9,QWORD PTR [r14+r13*1+0x28]
  29:	c4 82 b3 f5 54 2e 30 	pdep   rdx,r9,QWORD PTR [r14+r13*1+0x30]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 7.2
- Core cycles: 7.01
- Reference cycles: 7.02
- UOPS_EXECUTED.CORE: 14.11
- RETIRE_SLOTS: 14.1
- UOPS_MITE: 0.07
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 7.0
- UOPS_PORT_2: 3.5
- UOPS_PORT_3: 3.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

PDEP (R64, R64, M64) - Throughput and Uops

With a non-indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 7 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 7 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10