PCLMULQDQ (XMM, XMM, I8) - Throughput and Uops (IACA 2.3)
With different registers for different operands
With 1 independent instruction
Throughput Analysis Report
--------------------------
Block Throughput: 10.52 Cycles Throughput Bottleneck: FrontEnd
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 2.0 0.0 | 0.0 | 0.0 0.0 | 0.0 0.0 | 0.0 | 1.0 | 0.0 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 3 | 2.0 | | | | | 1.0 | | | CP | pclmulqdq xmm0, xmm1, 0x2
Total Num Of Uops: 3
With 12 independent instructions
Throughput Analysis Report
--------------------------
Block Throughput: 24.00 Cycles Throughput Bottleneck: Backend. Port0
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 24.0 0.0 | 0.0 | 0.0 0.0 | 0.0 0.0 | 0.0 | 12.0 | 0.0 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 3 | 2.0 | | | | | 1.0 | | | CP | pclmulqdq xmm0, xmm1, 0x2
| 3 | 2.0 | | | | | 1.0 | | | CP | pclmulqdq xmm2, xmm1, 0x2
| 3 | 2.0 | | | | | 1.0 | | | CP | pclmulqdq xmm3, xmm1, 0x2
| 3 | 2.0 | | | | | 1.0 | | | CP | pclmulqdq xmm4, xmm1, 0x2
| 3 | 2.0 | | | | | 1.0 | | | CP | pclmulqdq xmm5, xmm1, 0x2
| 3 | 2.0 | | | | | 1.0 | | | CP | pclmulqdq xmm6, xmm1, 0x2
| 3 | 2.0 | | | | | 1.0 | | | CP | pclmulqdq xmm7, xmm1, 0x2
| 3 | 2.0 | | | | | 1.0 | | | CP | pclmulqdq xmm8, xmm1, 0x2
| 3 | 2.0 | | | | | 1.0 | | | CP | pclmulqdq xmm9, xmm1, 0x2
| 3 | 2.0 | | | | | 1.0 | | | CP | pclmulqdq xmm10, xmm1, 0x2
| 3 | 2.0 | | | | | 1.0 | | | CP | pclmulqdq xmm11, xmm1, 0x2
| 3 | 2.0 | | | | | 1.0 | | | CP | pclmulqdq xmm12, xmm1, 0x2
Total Num Of Uops: 36
With the same register for for different operands
With 1 independent instruction
Throughput Analysis Report
--------------------------
Block Throughput: 10.52 Cycles Throughput Bottleneck: FrontEnd
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 2.0 0.0 | 0.0 | 0.0 0.0 | 0.0 0.0 | 0.0 | 1.0 | 0.0 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 3 | 2.0 | | | | | 1.0 | | | CP | pclmulqdq xmm0, xmm0, 0x2
Total Num Of Uops: 3
With 13 independent instructions
Throughput Analysis Report
--------------------------
Block Throughput: 26.00 Cycles Throughput Bottleneck: Backend. Port0
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 26.0 0.0 | 0.0 | 0.0 0.0 | 0.0 0.0 | 0.0 | 13.0 | 0.0 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 3 | 2.0 | | | | | 1.0 | | | CP | pclmulqdq xmm0, xmm0, 0x2
| 3 | 2.0 | | | | | 1.0 | | | CP | pclmulqdq xmm1, xmm1, 0x2
| 3 | 2.0 | | | | | 1.0 | | | CP | pclmulqdq xmm2, xmm2, 0x2
| 3 | 2.0 | | | | | 1.0 | | | CP | pclmulqdq xmm3, xmm3, 0x2
| 3 | 2.0 | | | | | 1.0 | | | CP | pclmulqdq xmm4, xmm4, 0x2
| 3 | 2.0 | | | | | 1.0 | | | CP | pclmulqdq xmm5, xmm5, 0x2
| 3 | 2.0 | | | | | 1.0 | | | CP | pclmulqdq xmm6, xmm6, 0x2
| 3 | 2.0 | | | | | 1.0 | | | CP | pclmulqdq xmm7, xmm7, 0x2
| 3 | 2.0 | | | | | 1.0 | | | CP | pclmulqdq xmm8, xmm8, 0x2
| 3 | 2.0 | | | | | 1.0 | | | CP | pclmulqdq xmm9, xmm9, 0x2
| 3 | 2.0 | | | | | 1.0 | | | CP | pclmulqdq xmm10, xmm10, 0x2
| 3 | 2.0 | | | | | 1.0 | | | CP | pclmulqdq xmm11, xmm11, 0x2
| 3 | 2.0 | | | | | 1.0 | | | CP | pclmulqdq xmm12, xmm12, 0x2
Total Num Of Uops: 39