MOVQ (M64, XMM) - Throughput and Uops (IACA 2.3)


With a non-indexed addressing mode

With 1 independent instruction

Throughput Analysis Report
--------------------------
Block Throughput: 1.00 Cycles       Throughput Bottleneck: FrontEnd

Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |  6   |  7   |
---------------------------------------------------------------------------------------
| Cycles | 0.0    0.0  | 0.0  | 0.3    0.0  | 0.3    0.0  | 1.0  | 0.0  | 0.0  | 0.3  |
---------------------------------------------------------------------------------------


| Num Of |                    Ports pressure in cycles                     |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |  6  |  7  |    |
---------------------------------------------------------------------------------
|   2^   |           |     | 0.3       | 0.3       | 1.0 |     |     | 0.3 | CP | movq qword ptr [r14], xmm0
Total Num Of Uops: 2

With 16 independent instructions


Throughput Analysis Report
--------------------------
Block Throughput: 16.00 Cycles       Throughput Bottleneck: Backend. Port4

Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |  6   |  7   |
---------------------------------------------------------------------------------------
| Cycles | 0.0    0.0  | 0.0  | 5.3    0.0  | 5.3    0.0  | 16.0 | 0.0  | 0.0  | 5.3  |
---------------------------------------------------------------------------------------


| Num Of |                    Ports pressure in cycles                     |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |  6  |  7  |    |
---------------------------------------------------------------------------------
|   2^   |           |     | 0.3       | 0.3       | 1.0 |     |     | 0.3 | CP | movq qword ptr [r14], xmm0
|   2^   |           |     | 0.3       | 0.3       | 1.0 |     |     | 0.3 | CP | movq qword ptr [r14+0x8], xmm0
|   2^   |           |     | 0.3       | 0.3       | 1.0 |     |     | 0.3 | CP | movq qword ptr [r14+0x10], xmm0
|   2^   |           |     | 0.3       | 0.3       | 1.0 |     |     | 0.3 | CP | movq qword ptr [r14+0x18], xmm0
|   2^   |           |     | 0.3       | 0.3       | 1.0 |     |     | 0.3 | CP | movq qword ptr [r14+0x20], xmm0
|   2^   |           |     | 0.3       | 0.3       | 1.0 |     |     | 0.3 | CP | movq qword ptr [r14+0x28], xmm0
|   2^   |           |     | 0.3       | 0.3       | 1.0 |     |     | 0.3 | CP | movq qword ptr [r14+0x30], xmm0
|   2^   |           |     | 0.3       | 0.3       | 1.0 |     |     | 0.3 | CP | movq qword ptr [r14+0x38], xmm0
|   2^   |           |     | 0.3       | 0.3       | 1.0 |     |     | 0.3 | CP | movq qword ptr [r14+0x40], xmm0
|   2^   |           |     | 0.3       | 0.3       | 1.0 |     |     | 0.3 | CP | movq qword ptr [r14+0x48], xmm0
|   2^   |           |     | 0.3       | 0.3       | 1.0 |     |     | 0.3 | CP | movq qword ptr [r14+0x50], xmm0
|   2^   |           |     | 0.3       | 0.3       | 1.0 |     |     | 0.3 | CP | movq qword ptr [r14+0x58], xmm0
|   2^   |           |     | 0.3       | 0.3       | 1.0 |     |     | 0.3 | CP | movq qword ptr [r14+0x60], xmm0
|   2^   |           |     | 0.3       | 0.3       | 1.0 |     |     | 0.3 | CP | movq qword ptr [r14+0x68], xmm0
|   2^   |           |     | 0.3       | 0.3       | 1.0 |     |     | 0.3 | CP | movq qword ptr [r14+0x70], xmm0
|   2^   |           |     | 0.3       | 0.3       | 1.0 |     |     | 0.3 | CP | movq qword ptr [r14+0x78], xmm0
Total Num Of Uops: 32

With an indexed addressing mode

With 1 independent instruction

Throughput Analysis Report
--------------------------
Block Throughput: 1.00 Cycles       Throughput Bottleneck: FrontEnd

Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |  6   |  7   |
---------------------------------------------------------------------------------------
| Cycles | 0.0    0.0  | 0.0  | 0.5    0.0  | 0.5    0.0  | 1.0  | 0.0  | 0.0  | 0.0  |
---------------------------------------------------------------------------------------


| Num Of |                    Ports pressure in cycles                     |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |  6  |  7  |    |
---------------------------------------------------------------------------------
|   2    |           |     | 0.5       | 0.5       | 1.0 |     |     |     | CP | movq qword ptr [r14+r13*1], xmm0
Total Num Of Uops: 2

With 16 independent instructions


Throughput Analysis Report
--------------------------
Block Throughput: 16.00 Cycles       Throughput Bottleneck: Backend. Port4

Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |  6   |  7   |
---------------------------------------------------------------------------------------
| Cycles | 0.0    0.0  | 0.0  | 8.0    0.0  | 8.0    0.0  | 16.0 | 0.0  | 0.0  | 0.0  |
---------------------------------------------------------------------------------------


| Num Of |                    Ports pressure in cycles                     |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |  6  |  7  |    |
---------------------------------------------------------------------------------
|   2    |           |     | 1.0       |           | 1.0 |     |     |     | CP | movq qword ptr [r14+r13*1], xmm0
|   2    |           |     |           | 1.0       | 1.0 |     |     |     | CP | movq qword ptr [r14+r13*1+0x8], xmm0
|   2    |           |     | 1.0       |           | 1.0 |     |     |     | CP | movq qword ptr [r14+r13*1+0x10], xmm0
|   2    |           |     |           | 1.0       | 1.0 |     |     |     | CP | movq qword ptr [r14+r13*1+0x18], xmm0
|   2    |           |     | 1.0       |           | 1.0 |     |     |     | CP | movq qword ptr [r14+r13*1+0x20], xmm0
|   2    |           |     |           | 1.0       | 1.0 |     |     |     | CP | movq qword ptr [r14+r13*1+0x28], xmm0
|   2    |           |     | 1.0       |           | 1.0 |     |     |     | CP | movq qword ptr [r14+r13*1+0x30], xmm0
|   2    |           |     |           | 1.0       | 1.0 |     |     |     | CP | movq qword ptr [r14+r13*1+0x38], xmm0
|   2    |           |     | 1.0       |           | 1.0 |     |     |     | CP | movq qword ptr [r14+r13*1+0x40], xmm0
|   2    |           |     |           | 1.0       | 1.0 |     |     |     | CP | movq qword ptr [r14+r13*1+0x48], xmm0
|   2    |           |     | 1.0       |           | 1.0 |     |     |     | CP | movq qword ptr [r14+r13*1+0x50], xmm0
|   2    |           |     |           | 1.0       | 1.0 |     |     |     | CP | movq qword ptr [r14+r13*1+0x58], xmm0
|   2    |           |     | 1.0       |           | 1.0 |     |     |     | CP | movq qword ptr [r14+r13*1+0x60], xmm0
|   2    |           |     |           | 1.0       | 1.0 |     |     |     | CP | movq qword ptr [r14+r13*1+0x68], xmm0
|   2    |           |     | 1.0       |           | 1.0 |     |     |     | CP | movq qword ptr [r14+r13*1+0x70], xmm0
|   2    |           |     |           | 1.0       | 1.0 |     |     |     | CP | movq qword ptr [r14+r13*1+0x78], xmm0
Total Num Of Uops: 32