CVTSI2SS (XMM, R32) - Throughput and Uops (IACA 3.0)

With 1 independent instruction

Throughput Analysis Report
--------------------------
Block Throughput: 0.97 Cycles       Throughput Bottleneck: Dependency chains
Loop Count:  32
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
|  Port  |   0   -  DV   |   1   |   2   -  D    |   3   -  D    |   4   |   5   |   6   |   7   |
--------------------------------------------------------------------------------------------------
| Cycles |  0.0     0.0  |  1.0  |  0.0     0.0  |  0.0     0.0  |  0.0  |  1.0  |  0.0  |  0.0  |
--------------------------------------------------------------------------------------------------

| Num Of   |                    Ports pressure in cycles                         |      |
|  Uops    |  0  - DV    |  1   |  2  -  D    |  3  -  D    |  4   |  5   |  6   |  7   |
-----------------------------------------------------------------------------------------
|   2      |             | 1.0  |             |             |      | 1.0  |      |      | cvtsi2ss xmm0, r8d
Total Num Of Uops: 2

With 13 independent instructions

Throughput Analysis Report
--------------------------
Block Throughput: 12.95 Cycles       Throughput Bottleneck: Backend
Loop Count:  22
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
|  Port  |   0   -  DV   |   1   |   2   -  D    |   3   -  D    |   4   |   5   |   6   |   7   |
--------------------------------------------------------------------------------------------------
| Cycles |  0.0     0.0  | 13.0  |  0.0     0.0  |  0.0     0.0  |  0.0  | 13.0  |  0.0  |  0.0  |
--------------------------------------------------------------------------------------------------

| Num Of   |                    Ports pressure in cycles                         |      |
|  Uops    |  0  - DV    |  1   |  2  -  D    |  3  -  D    |  4   |  5   |  6   |  7   |
-----------------------------------------------------------------------------------------
|   2      |             | 1.0  |             |             |      | 1.0  |      |      | cvtsi2ss xmm0, r8d
|   2      |             | 1.0  |             |             |      | 1.0  |      |      | cvtsi2ss xmm1, r8d
|   2      |             | 1.0  |             |             |      | 1.0  |      |      | cvtsi2ss xmm2, r8d
|   2      |             | 1.0  |             |             |      | 1.0  |      |      | cvtsi2ss xmm3, r8d
|   2      |             | 1.0  |             |             |      | 1.0  |      |      | cvtsi2ss xmm4, r8d
|   2      |             | 1.0  |             |             |      | 1.0  |      |      | cvtsi2ss xmm5, r8d
|   2      |             | 1.0  |             |             |      | 1.0  |      |      | cvtsi2ss xmm6, r8d
|   2      |             | 1.0  |             |             |      | 1.0  |      |      | cvtsi2ss xmm7, r8d
|   2      |             | 1.0  |             |             |      | 1.0  |      |      | cvtsi2ss xmm8, r8d
|   2      |             | 1.0  |             |             |      | 1.0  |      |      | cvtsi2ss xmm9, r8d
|   2      |             | 1.0  |             |             |      | 1.0  |      |      | cvtsi2ss xmm10, r8d
|   2      |             | 1.0  |             |             |      | 1.0  |      |      | cvtsi2ss xmm11, r8d
|   2      |             | 1.0  |             |             |      | 1.0  |      |      | cvtsi2ss xmm12, r8d
Total Num Of Uops: 26