BSR (R64, M64) - Throughput and Uops (IACA 3.0)
With a non-indexed addressing mode
With 1 independent instruction
Throughput Analysis Report
--------------------------
Block Throughput: 1.00 Cycles Throughput Bottleneck: Backend
Loop Count: 54
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
--------------------------------------------------------------------------------------------------
| Cycles | 0.0 0.0 | 1.0 | 0.5 0.5 | 0.5 0.5 | 0.0 | 0.0 | 0.0 | 0.0 |
--------------------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
-----------------------------------------------------------------------------------------
| 2^ | | 1.0 | 0.5 0.5 | 0.5 0.5 | | | | | bsr r8, qword ptr [r14]
Total Num Of Uops: 2
With 8 independent instructions
Throughput Analysis Report
--------------------------
Block Throughput: 8.00 Cycles Throughput Bottleneck: Backend
Loop Count: 22
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
--------------------------------------------------------------------------------------------------
| Cycles | 0.0 0.0 | 8.0 | 4.0 4.0 | 4.0 4.0 | 0.0 | 0.0 | 0.0 | 0.0 |
--------------------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
-----------------------------------------------------------------------------------------
| 2^ | | 1.0 | 1.0 1.0 | | | | | | bsr r8, qword ptr [r14]
| 2^ | | 1.0 | | 1.0 1.0 | | | | | bsr r9, qword ptr [r14+0x8]
| 2^ | | 1.0 | 1.0 1.0 | | | | | | bsr r10, qword ptr [r14+0x10]
| 2^ | | 1.0 | | 1.0 1.0 | | | | | bsr r11, qword ptr [r14+0x18]
| 2^ | | 1.0 | 1.0 1.0 | | | | | | bsr r12, qword ptr [r14+0x20]
| 2^ | | 1.0 | | 1.0 1.0 | | | | | bsr rbx, qword ptr [r14+0x28]
| 2^ | | 1.0 | 1.0 1.0 | | | | | | bsr rcx, qword ptr [r14+0x30]
| 2^ | | 1.0 | | 1.0 1.0 | | | | | bsr rdx, qword ptr [r14+0x38]
Total Num Of Uops: 16
With an indexed addressing mode
With 1 independent instruction
Throughput Analysis Report
--------------------------
Block Throughput: 1.00 Cycles Throughput Bottleneck: Dependency chains
Loop Count: 46
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
--------------------------------------------------------------------------------------------------
| Cycles | 0.0 0.0 | 1.0 | 0.5 0.5 | 0.5 0.5 | 0.0 | 0.0 | 0.0 | 0.0 |
--------------------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
-----------------------------------------------------------------------------------------
| 2 | | 1.0 | 0.5 0.5 | 0.5 0.5 | | | | | bsr r8, qword ptr [r14+r13*1]
Total Num Of Uops: 2
With 8 independent instructions
Throughput Analysis Report
--------------------------
Block Throughput: 8.00 Cycles Throughput Bottleneck: Backend
Loop Count: 22
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
--------------------------------------------------------------------------------------------------
| Cycles | 0.0 0.0 | 8.0 | 4.0 4.0 | 4.0 4.0 | 0.0 | 0.0 | 0.0 | 0.0 |
--------------------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
-----------------------------------------------------------------------------------------
| 2 | | 1.0 | 1.0 1.0 | | | | | | bsr r8, qword ptr [r14+r13*1]
| 2 | | 1.0 | | 1.0 1.0 | | | | | bsr r9, qword ptr [r14+r13*1+0x8]
| 2 | | 1.0 | 1.0 1.0 | | | | | | bsr r10, qword ptr [r14+r13*1+0x10]
| 2 | | 1.0 | | 1.0 1.0 | | | | | bsr r11, qword ptr [r14+r13*1+0x18]
| 2 | | 1.0 | 1.0 1.0 | | | | | | bsr r12, qword ptr [r14+r13*1+0x20]
| 2 | | 1.0 | | 1.0 1.0 | | | | | bsr rbx, qword ptr [r14+r13*1+0x28]
| 2 | | 1.0 | 1.0 1.0 | | | | | | bsr rcx, qword ptr [r14+r13*1+0x30]
| 2 | | 1.0 | | 1.0 1.0 | | | | | bsr rdx, qword ptr [r14+r13*1+0x38]
Total Num Of Uops: 16