ADD_03 (R64, R64) - Throughput and Uops (IACA 2.1)


With different registers for different operands

With 1 independent instruction

Throughput Analysis Report
--------------------------
Block Throughput: 1.00 Cycles       Throughput Bottleneck: InterIteration

Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |  6   |  7   |
---------------------------------------------------------------------------------------
| Cycles | 0.2    0.0  | 0.2  | 0.0    0.0  | 0.0    0.0  | 0.0  | 0.2  | 0.2  | 0.0  |
---------------------------------------------------------------------------------------


| Num Of |                    Ports pressure in cycles                     |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |  6  |  7  |    |
---------------------------------------------------------------------------------
|   1    | 0.2       | 0.2 |           |           |     | 0.2 | 0.2 |     | CP | add r8, r9
Total Num Of Uops: 1

With 12 independent instructions


Throughput Analysis Report
--------------------------
Block Throughput: 3.00 Cycles       Throughput Bottleneck: FrontEnd, Port0, Port1, Port5, Port6

Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |  6   |  7   |
---------------------------------------------------------------------------------------
| Cycles | 3.0    0.0  | 3.0  | 0.0    0.0  | 0.0    0.0  | 0.0  | 3.0  | 3.0  | 0.0  |
---------------------------------------------------------------------------------------


| Num Of |                    Ports pressure in cycles                     |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |  6  |  7  |    |
---------------------------------------------------------------------------------
|   1    | 1.0       |     |           |           |     |     |     |     | CP | add r8, r9
|   1    |           | 1.0 |           |           |     |     |     |     | CP | add r10, r9
|   1    |           |     |           |           |     | 1.0 |     |     | CP | add r11, r9
|   1    |           |     |           |           |     |     | 1.0 |     | CP | add r12, r9
|   1    | 1.0       |     |           |           |     |     |     |     | CP | add r13, r9
|   1    |           | 1.0 |           |           |     |     |     |     | CP | add r14, r9
|   1    |           |     |           |           |     | 1.0 |     |     | CP | add rbx, r9
|   1    |           |     |           |           |     |     | 1.0 |     | CP | add rcx, r9
|   1    | 1.0       |     |           |           |     |     |     |     | CP | add rdx, r9
|   1    |           | 1.0 |           |           |     |     |     |     | CP | add rdi, r9
|   1    |           |     |           |           |     | 1.0 |     |     | CP | add rsi, r9
|   1    |           |     |           |           |     |     | 1.0 |     | CP | add rbp, r9
Total Num Of Uops: 12

With the same register for for different operands

With 1 independent instruction

Throughput Analysis Report
--------------------------
Block Throughput: 1.00 Cycles       Throughput Bottleneck: InterIteration

Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |  6   |  7   |
---------------------------------------------------------------------------------------
| Cycles | 0.2    0.0  | 0.2  | 0.0    0.0  | 0.0    0.0  | 0.0  | 0.2  | 0.2  | 0.0  |
---------------------------------------------------------------------------------------


| Num Of |                    Ports pressure in cycles                     |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |  6  |  7  |    |
---------------------------------------------------------------------------------
|   1    | 0.2       | 0.2 |           |           |     | 0.2 | 0.2 |     | CP | add r8, r8
Total Num Of Uops: 1

With 13 independent instructions


Throughput Analysis Report
--------------------------
Block Throughput: 3.25 Cycles       Throughput Bottleneck: FrontEnd, Port0, Port1, Port5, Port6

Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |  6   |  7   |
---------------------------------------------------------------------------------------
| Cycles | 3.2    0.0  | 3.2  | 0.0    0.0  | 0.0    0.0  | 0.0  | 3.2  | 3.2  | 0.0  |
---------------------------------------------------------------------------------------


| Num Of |                    Ports pressure in cycles                     |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |  6  |  7  |    |
---------------------------------------------------------------------------------
|   1    | 0.2       | 0.2 |           |           |     | 0.2 | 0.2 |     | CP | add r8, r8
|   1    | 0.2       | 0.2 |           |           |     | 0.2 | 0.2 |     | CP | add r9, r9
|   1    | 0.2       | 0.2 |           |           |     | 0.2 | 0.2 |     | CP | add r10, r10
|   1    | 0.2       | 0.2 |           |           |     | 0.2 | 0.2 |     | CP | add r11, r11
|   1    | 0.2       | 0.2 |           |           |     | 0.2 | 0.2 |     | CP | add r12, r12
|   1    | 0.2       | 0.2 |           |           |     | 0.2 | 0.2 |     | CP | add r13, r13
|   1    | 0.2       | 0.2 |           |           |     | 0.2 | 0.2 |     | CP | add r14, r14
|   1    | 0.2       | 0.2 |           |           |     | 0.2 | 0.2 |     | CP | add rbx, rbx
|   1    | 0.2       | 0.2 |           |           |     | 0.2 | 0.2 |     | CP | add rcx, rcx
|   1    | 0.2       | 0.2 |           |           |     | 0.2 | 0.2 |     | CP | add rdx, rdx
|   1    | 0.2       | 0.2 |           |           |     | 0.2 | 0.2 |     | CP | add rdi, rdi
|   1    | 0.2       | 0.2 |           |           |     | 0.2 | 0.2 |     | CP | add rsi, rsi
|   1    | 0.2       | 0.2 |           |           |     | 0.2 | 0.2 |     | CP | add rbp, rbp
Total Num Of Uops: 13

With the -no_interiteration flag

Throughput Analysis Report
--------------------------
Block Throughput: 0.25 Cycles       Throughput Bottleneck: FrontEnd, Port0, Port1, Port5, Port6

Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |  6   |  7   |
---------------------------------------------------------------------------------------
| Cycles | 0.2    0.0  | 0.2  | 0.0    0.0  | 0.0    0.0  | 0.0  | 0.2  | 0.2  | 0.0  |
---------------------------------------------------------------------------------------


| Num Of |                    Ports pressure in cycles                     |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |  6  |  7  |    |
---------------------------------------------------------------------------------
|   1    | 0.2       | 0.2 |           |           |     | 0.2 | 0.2 |     | CP | add r8, r9
Total Num Of Uops: 1