VPMULUDQ (ZMM, ZMM, ZMM)

With unroll_count=500 and no inner loop

Code:

   0:	62 f1 f5 48 f4 c2    	vpmuludq zmm0,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 0.5
- Reference cycles: 0.32
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.5
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.18

With loop_count=1000 and unroll_count=10

Code:

   0:	62 f1 f5 48 f4 c2    	vpmuludq zmm0,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 0.5
- Reference cycles: 0.33
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.5
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 f1 f5 48 f4 c2    	vpmuludq zmm0,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 0.5
- Reference cycles: 0.3
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.5
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 f1 f5 48 f4 c2    	vpmuludq zmm0,zmm1,zmm2
   6:	62 f1 f5 48 f4 da    	vpmuludq zmm3,zmm1,zmm2
   c:	62 f1 f5 48 f4 e2    	vpmuludq zmm4,zmm1,zmm2
  12:	62 f1 f5 48 f4 ea    	vpmuludq zmm5,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 2.0
- Reference cycles: 1.2
- UOPS_EXECUTED.THREAD: 3.99
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 2.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.72

With loop_count=1000 and unroll_count=2

Code:

   0:	62 f1 f5 48 f4 c2    	vpmuludq zmm0,zmm1,zmm2
   6:	62 f1 f5 48 f4 da    	vpmuludq zmm3,zmm1,zmm2
   c:	62 f1 f5 48 f4 e2    	vpmuludq zmm4,zmm1,zmm2
  12:	62 f1 f5 48 f4 ea    	vpmuludq zmm5,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 2.0
- Reference cycles: 1.34
- UOPS_EXECUTED.THREAD: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 2.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	62 f1 f5 48 f4 c2    	vpmuludq zmm0,zmm1,zmm2
   6:	62 f1 f5 48 f4 da    	vpmuludq zmm3,zmm1,zmm2
   c:	62 f1 f5 48 f4 e2    	vpmuludq zmm4,zmm1,zmm2
  12:	62 f1 f5 48 f4 ea    	vpmuludq zmm5,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 2.0
- Reference cycles: 1.2
- UOPS_EXECUTED.THREAD: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 2.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f1 f5 48 f4 c2    	vpmuludq zmm0,zmm1,zmm2
   6:	62 f1 f5 48 f4 da    	vpmuludq zmm3,zmm1,zmm2
   c:	62 f1 f5 48 f4 e2    	vpmuludq zmm4,zmm1,zmm2
  12:	62 f1 f5 48 f4 ea    	vpmuludq zmm5,zmm1,zmm2
  18:	62 f1 f5 48 f4 f2    	vpmuludq zmm6,zmm1,zmm2
  1e:	62 f1 f5 48 f4 fa    	vpmuludq zmm7,zmm1,zmm2
  24:	62 71 f5 48 f4 c2    	vpmuludq zmm8,zmm1,zmm2
  2a:	62 71 f5 48 f4 ca    	vpmuludq zmm9,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 4.01
- Reference cycles: 2.0
- UOPS_EXECUTED.THREAD: 7.98
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.13
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 4.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.44

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f1 f5 48 f4 c2    	vpmuludq zmm0,zmm1,zmm2
   6:	62 f1 f5 48 f4 da    	vpmuludq zmm3,zmm1,zmm2
   c:	62 f1 f5 48 f4 e2    	vpmuludq zmm4,zmm1,zmm2
  12:	62 f1 f5 48 f4 ea    	vpmuludq zmm5,zmm1,zmm2
  18:	62 f1 f5 48 f4 f2    	vpmuludq zmm6,zmm1,zmm2
  1e:	62 f1 f5 48 f4 fa    	vpmuludq zmm7,zmm1,zmm2
  24:	62 71 f5 48 f4 c2    	vpmuludq zmm8,zmm1,zmm2
  2a:	62 71 f5 48 f4 ca    	vpmuludq zmm9,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 4.01
- Reference cycles: 2.68
- UOPS_EXECUTED.THREAD: 9.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 4.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	62 f1 f5 48 f4 c2    	vpmuludq zmm0,zmm1,zmm2
   6:	62 f1 f5 48 f4 da    	vpmuludq zmm3,zmm1,zmm2
   c:	62 f1 f5 48 f4 e2    	vpmuludq zmm4,zmm1,zmm2
  12:	62 f1 f5 48 f4 ea    	vpmuludq zmm5,zmm1,zmm2
  18:	62 f1 f5 48 f4 f2    	vpmuludq zmm6,zmm1,zmm2
  1e:	62 f1 f5 48 f4 fa    	vpmuludq zmm7,zmm1,zmm2
  24:	62 71 f5 48 f4 c2    	vpmuludq zmm8,zmm1,zmm2
  2a:	62 71 f5 48 f4 ca    	vpmuludq zmm9,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 4.01
- Reference cycles: 2.57
- UOPS_EXECUTED.THREAD: 8.1
- RETIRE_SLOTS: 8.11
- UOPS_MITE: 0.11
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 4.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f1 f5 48 f4 c2    	vpmuludq zmm0,zmm1,zmm2
   6:	62 f1 f5 48 f4 da    	vpmuludq zmm3,zmm1,zmm2
   c:	62 f1 f5 48 f4 e2    	vpmuludq zmm4,zmm1,zmm2
  12:	62 f1 f5 48 f4 ea    	vpmuludq zmm5,zmm1,zmm2
  18:	62 f1 f5 48 f4 f2    	vpmuludq zmm6,zmm1,zmm2
  1e:	62 f1 f5 48 f4 fa    	vpmuludq zmm7,zmm1,zmm2
  24:	62 71 f5 48 f4 c2    	vpmuludq zmm8,zmm1,zmm2
  2a:	62 71 f5 48 f4 ca    	vpmuludq zmm9,zmm1,zmm2
  30:	62 71 f5 48 f4 d2    	vpmuludq zmm10,zmm1,zmm2
  36:	62 71 f5 48 f4 da    	vpmuludq zmm11,zmm1,zmm2
  3c:	62 71 f5 48 f4 e2    	vpmuludq zmm12,zmm1,zmm2
  42:	62 e1 f5 48 f4 c2    	vpmuludq zmm16,zmm1,zmm2
  48:	62 e1 f5 48 f4 ca    	vpmuludq zmm17,zmm1,zmm2
  4e:	62 e1 f5 48 f4 d2    	vpmuludq zmm18,zmm1,zmm2
  54:	62 e1 f5 48 f4 da    	vpmuludq zmm19,zmm1,zmm2
  5a:	62 e1 f5 48 f4 e2    	vpmuludq zmm20,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 8.0
- Reference cycles: 5.2
- UOPS_EXECUTED.THREAD: 16.02
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 15.92
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 8.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.89

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f1 f5 48 f4 c2    	vpmuludq zmm0,zmm1,zmm2
   6:	62 f1 f5 48 f4 da    	vpmuludq zmm3,zmm1,zmm2
   c:	62 f1 f5 48 f4 e2    	vpmuludq zmm4,zmm1,zmm2
  12:	62 f1 f5 48 f4 ea    	vpmuludq zmm5,zmm1,zmm2
  18:	62 f1 f5 48 f4 f2    	vpmuludq zmm6,zmm1,zmm2
  1e:	62 f1 f5 48 f4 fa    	vpmuludq zmm7,zmm1,zmm2
  24:	62 71 f5 48 f4 c2    	vpmuludq zmm8,zmm1,zmm2
  2a:	62 71 f5 48 f4 ca    	vpmuludq zmm9,zmm1,zmm2
  30:	62 71 f5 48 f4 d2    	vpmuludq zmm10,zmm1,zmm2
  36:	62 71 f5 48 f4 da    	vpmuludq zmm11,zmm1,zmm2
  3c:	62 71 f5 48 f4 e2    	vpmuludq zmm12,zmm1,zmm2
  42:	62 e1 f5 48 f4 c2    	vpmuludq zmm16,zmm1,zmm2
  48:	62 e1 f5 48 f4 ca    	vpmuludq zmm17,zmm1,zmm2
  4e:	62 e1 f5 48 f4 d2    	vpmuludq zmm18,zmm1,zmm2
  54:	62 e1 f5 48 f4 da    	vpmuludq zmm19,zmm1,zmm2
  5a:	62 e1 f5 48 f4 e2    	vpmuludq zmm20,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 8.01
- Reference cycles: 5.36
- UOPS_EXECUTED.THREAD: 17.0
- RETIRE_SLOTS: 17.01
- UOPS_MITE: 0.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 8.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	62 f1 f5 48 f4 c2    	vpmuludq zmm0,zmm1,zmm2
   6:	62 f1 f5 48 f4 da    	vpmuludq zmm3,zmm1,zmm2
   c:	62 f1 f5 48 f4 e2    	vpmuludq zmm4,zmm1,zmm2
  12:	62 f1 f5 48 f4 ea    	vpmuludq zmm5,zmm1,zmm2
  18:	62 f1 f5 48 f4 f2    	vpmuludq zmm6,zmm1,zmm2
  1e:	62 f1 f5 48 f4 fa    	vpmuludq zmm7,zmm1,zmm2
  24:	62 71 f5 48 f4 c2    	vpmuludq zmm8,zmm1,zmm2
  2a:	62 71 f5 48 f4 ca    	vpmuludq zmm9,zmm1,zmm2
  30:	62 71 f5 48 f4 d2    	vpmuludq zmm10,zmm1,zmm2
  36:	62 71 f5 48 f4 da    	vpmuludq zmm11,zmm1,zmm2
  3c:	62 71 f5 48 f4 e2    	vpmuludq zmm12,zmm1,zmm2
  42:	62 e1 f5 48 f4 c2    	vpmuludq zmm16,zmm1,zmm2
  48:	62 e1 f5 48 f4 ca    	vpmuludq zmm17,zmm1,zmm2
  4e:	62 e1 f5 48 f4 d2    	vpmuludq zmm18,zmm1,zmm2
  54:	62 e1 f5 48 f4 da    	vpmuludq zmm19,zmm1,zmm2
  5a:	62 e1 f5 48 f4 e2    	vpmuludq zmm20,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 8.01
- Reference cycles: 5.36
- UOPS_EXECUTED.THREAD: 16.1
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.17
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 8.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.03

With the same register for for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	62 f1 fd 48 f4 c0    	vpmuludq zmm0,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 5.5
- Reference cycles: 3.52
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.5
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.19

With loop_count=1000 and unroll_count=10

Code:

   0:	62 f1 fd 48 f4 c0    	vpmuludq zmm0,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 5.45
- Reference cycles: 3.31
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.5
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 f1 fd 48 f4 c0    	vpmuludq zmm0,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 5.48
- Reference cycles: 3.38
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.5
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 f1 fd 48 f4 c0    	vpmuludq zmm0,zmm0,zmm0
   6:	62 f1 f5 48 f4 c9    	vpmuludq zmm1,zmm1,zmm1
   c:	62 f1 ed 48 f4 d2    	vpmuludq zmm2,zmm2,zmm2
  12:	62 f1 e5 48 f4 db    	vpmuludq zmm3,zmm3,zmm3

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 5.1
- Reference cycles: 3.2
- UOPS_EXECUTED.THREAD: 4.01
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 2.01
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.74

With loop_count=1000 and unroll_count=2

Code:

   0:	62 f1 fd 48 f4 c0    	vpmuludq zmm0,zmm0,zmm0
   6:	62 f1 f5 48 f4 c9    	vpmuludq zmm1,zmm1,zmm1
   c:	62 f1 ed 48 f4 d2    	vpmuludq zmm2,zmm2,zmm2
  12:	62 f1 e5 48 f4 db    	vpmuludq zmm3,zmm3,zmm3

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 5.29
- Reference cycles: 3.21
- UOPS_EXECUTED.THREAD: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 2.02
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	62 f1 fd 48 f4 c0    	vpmuludq zmm0,zmm0,zmm0
   6:	62 f1 f5 48 f4 c9    	vpmuludq zmm1,zmm1,zmm1
   c:	62 f1 ed 48 f4 d2    	vpmuludq zmm2,zmm2,zmm2
  12:	62 f1 e5 48 f4 db    	vpmuludq zmm3,zmm3,zmm3

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 5.04
- Reference cycles: 3.04
- UOPS_EXECUTED.THREAD: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 2.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f1 fd 48 f4 c0    	vpmuludq zmm0,zmm0,zmm0
   6:	62 f1 f5 48 f4 c9    	vpmuludq zmm1,zmm1,zmm1
   c:	62 f1 ed 48 f4 d2    	vpmuludq zmm2,zmm2,zmm2
  12:	62 f1 e5 48 f4 db    	vpmuludq zmm3,zmm3,zmm3
  18:	62 f1 dd 48 f4 e4    	vpmuludq zmm4,zmm4,zmm4
  1e:	62 f1 d5 48 f4 ed    	vpmuludq zmm5,zmm5,zmm5
  24:	62 f1 cd 48 f4 f6    	vpmuludq zmm6,zmm6,zmm6
  2a:	62 f1 c5 48 f4 ff    	vpmuludq zmm7,zmm7,zmm7

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 5.0
- Reference cycles: 2.8
- UOPS_EXECUTED.THREAD: 7.99
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.01
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 4.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.45

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f1 fd 48 f4 c0    	vpmuludq zmm0,zmm0,zmm0
   6:	62 f1 f5 48 f4 c9    	vpmuludq zmm1,zmm1,zmm1
   c:	62 f1 ed 48 f4 d2    	vpmuludq zmm2,zmm2,zmm2
  12:	62 f1 e5 48 f4 db    	vpmuludq zmm3,zmm3,zmm3
  18:	62 f1 dd 48 f4 e4    	vpmuludq zmm4,zmm4,zmm4
  1e:	62 f1 d5 48 f4 ed    	vpmuludq zmm5,zmm5,zmm5
  24:	62 f1 cd 48 f4 f6    	vpmuludq zmm6,zmm6,zmm6
  2a:	62 f1 c5 48 f4 ff    	vpmuludq zmm7,zmm7,zmm7

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 5.44
- Reference cycles: 3.61
- UOPS_EXECUTED.THREAD: 9.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 4.01
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	62 f1 fd 48 f4 c0    	vpmuludq zmm0,zmm0,zmm0
   6:	62 f1 f5 48 f4 c9    	vpmuludq zmm1,zmm1,zmm1
   c:	62 f1 ed 48 f4 d2    	vpmuludq zmm2,zmm2,zmm2
  12:	62 f1 e5 48 f4 db    	vpmuludq zmm3,zmm3,zmm3
  18:	62 f1 dd 48 f4 e4    	vpmuludq zmm4,zmm4,zmm4
  1e:	62 f1 d5 48 f4 ed    	vpmuludq zmm5,zmm5,zmm5
  24:	62 f1 cd 48 f4 f6    	vpmuludq zmm6,zmm6,zmm6
  2a:	62 f1 c5 48 f4 ff    	vpmuludq zmm7,zmm7,zmm7

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 5.06
- Reference cycles: 3.05
- UOPS_EXECUTED.THREAD: 8.11
- RETIRE_SLOTS: 8.11
- UOPS_MITE: 0.1
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 4.05
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f1 fd 48 f4 c0    	vpmuludq zmm0,zmm0,zmm0
   6:	62 f1 f5 48 f4 c9    	vpmuludq zmm1,zmm1,zmm1
   c:	62 f1 ed 48 f4 d2    	vpmuludq zmm2,zmm2,zmm2
  12:	62 f1 e5 48 f4 db    	vpmuludq zmm3,zmm3,zmm3
  18:	62 f1 dd 48 f4 e4    	vpmuludq zmm4,zmm4,zmm4
  1e:	62 f1 d5 48 f4 ed    	vpmuludq zmm5,zmm5,zmm5
  24:	62 f1 cd 48 f4 f6    	vpmuludq zmm6,zmm6,zmm6
  2a:	62 f1 c5 48 f4 ff    	vpmuludq zmm7,zmm7,zmm7
  30:	62 51 bd 48 f4 c0    	vpmuludq zmm8,zmm8,zmm8
  36:	62 51 b5 48 f4 c9    	vpmuludq zmm9,zmm9,zmm9
  3c:	62 51 ad 48 f4 d2    	vpmuludq zmm10,zmm10,zmm10
  42:	62 51 a5 48 f4 db    	vpmuludq zmm11,zmm11,zmm11
  48:	62 51 9d 48 f4 e4    	vpmuludq zmm12,zmm12,zmm12
  4e:	62 a1 fd 40 f4 c0    	vpmuludq zmm16,zmm16,zmm16
  54:	62 a1 f5 40 f4 c9    	vpmuludq zmm17,zmm17,zmm17
  5a:	62 a1 ed 40 f4 d2    	vpmuludq zmm18,zmm18,zmm18

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7;
VXORPS ZMM8, ZMM8, ZMM8;
VXORPS ZMM9, ZMM9, ZMM9;
VXORPS ZMM10, ZMM10, ZMM10;
VXORPS ZMM11, ZMM11, ZMM11;
VXORPS ZMM12, ZMM12, ZMM12;
VXORPS ZMM16, ZMM16, ZMM16;
VXORPS ZMM17, ZMM17, ZMM17;
VXORPS ZMM18, ZMM18, ZMM18

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 8.0
- Reference cycles: 4.93
- UOPS_EXECUTED.THREAD: 15.98
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.03
- UOPS_MS: 0.01
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 8.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.91

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f1 fd 48 f4 c0    	vpmuludq zmm0,zmm0,zmm0
   6:	62 f1 f5 48 f4 c9    	vpmuludq zmm1,zmm1,zmm1
   c:	62 f1 ed 48 f4 d2    	vpmuludq zmm2,zmm2,zmm2
  12:	62 f1 e5 48 f4 db    	vpmuludq zmm3,zmm3,zmm3
  18:	62 f1 dd 48 f4 e4    	vpmuludq zmm4,zmm4,zmm4
  1e:	62 f1 d5 48 f4 ed    	vpmuludq zmm5,zmm5,zmm5
  24:	62 f1 cd 48 f4 f6    	vpmuludq zmm6,zmm6,zmm6
  2a:	62 f1 c5 48 f4 ff    	vpmuludq zmm7,zmm7,zmm7
  30:	62 51 bd 48 f4 c0    	vpmuludq zmm8,zmm8,zmm8
  36:	62 51 b5 48 f4 c9    	vpmuludq zmm9,zmm9,zmm9
  3c:	62 51 ad 48 f4 d2    	vpmuludq zmm10,zmm10,zmm10
  42:	62 51 a5 48 f4 db    	vpmuludq zmm11,zmm11,zmm11
  48:	62 51 9d 48 f4 e4    	vpmuludq zmm12,zmm12,zmm12
  4e:	62 a1 fd 40 f4 c0    	vpmuludq zmm16,zmm16,zmm16
  54:	62 a1 f5 40 f4 c9    	vpmuludq zmm17,zmm17,zmm17
  5a:	62 a1 ed 40 f4 d2    	vpmuludq zmm18,zmm18,zmm18

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7;
VXORPS ZMM8, ZMM8, ZMM8;
VXORPS ZMM9, ZMM9, ZMM9;
VXORPS ZMM10, ZMM10, ZMM10;
VXORPS ZMM11, ZMM11, ZMM11;
VXORPS ZMM12, ZMM12, ZMM12;
VXORPS ZMM16, ZMM16, ZMM16;
VXORPS ZMM17, ZMM17, ZMM17;
VXORPS ZMM18, ZMM18, ZMM18

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 8.01
- Reference cycles: 5.36
- UOPS_EXECUTED.THREAD: 17.0
- RETIRE_SLOTS: 17.01
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 8.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	62 f1 fd 48 f4 c0    	vpmuludq zmm0,zmm0,zmm0
   6:	62 f1 f5 48 f4 c9    	vpmuludq zmm1,zmm1,zmm1
   c:	62 f1 ed 48 f4 d2    	vpmuludq zmm2,zmm2,zmm2
  12:	62 f1 e5 48 f4 db    	vpmuludq zmm3,zmm3,zmm3
  18:	62 f1 dd 48 f4 e4    	vpmuludq zmm4,zmm4,zmm4
  1e:	62 f1 d5 48 f4 ed    	vpmuludq zmm5,zmm5,zmm5
  24:	62 f1 cd 48 f4 f6    	vpmuludq zmm6,zmm6,zmm6
  2a:	62 f1 c5 48 f4 ff    	vpmuludq zmm7,zmm7,zmm7
  30:	62 51 bd 48 f4 c0    	vpmuludq zmm8,zmm8,zmm8
  36:	62 51 b5 48 f4 c9    	vpmuludq zmm9,zmm9,zmm9
  3c:	62 51 ad 48 f4 d2    	vpmuludq zmm10,zmm10,zmm10
  42:	62 51 a5 48 f4 db    	vpmuludq zmm11,zmm11,zmm11
  48:	62 51 9d 48 f4 e4    	vpmuludq zmm12,zmm12,zmm12
  4e:	62 a1 fd 40 f4 c0    	vpmuludq zmm16,zmm16,zmm16
  54:	62 a1 f5 40 f4 c9    	vpmuludq zmm17,zmm17,zmm17
  5a:	62 a1 ed 40 f4 d2    	vpmuludq zmm18,zmm18,zmm18

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7;
VXORPS ZMM8, ZMM8, ZMM8;
VXORPS ZMM9, ZMM9, ZMM9;
VXORPS ZMM10, ZMM10, ZMM10;
VXORPS ZMM11, ZMM11, ZMM11;
VXORPS ZMM12, ZMM12, ZMM12;
VXORPS ZMM16, ZMM16, ZMM16;
VXORPS ZMM17, ZMM17, ZMM17;
VXORPS ZMM18, ZMM18, ZMM18

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 8.01
- Reference cycles: 4.88
- UOPS_EXECUTED.THREAD: 16.1
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.18
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 8.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

VPMULUDQ (ZMM, ZMM, ZMM) - Throughput and Uops

With different registers for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With the same register for for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10