VPMULLQ (ZMM, ZMM, ZMM)

With unroll_count=500 and no inner loop

Code:

   0:	62 f2 f5 48 40 c2    	vpmullq zmm0,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.5
- Reference cycles: 0.91
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.5
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	62 f2 f5 48 40 c2    	vpmullq zmm0,zmm1,zmm2
   6:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 2.0
- Reference cycles: 1.33
- UOPS_EXECUTED.THREAD: 2.99
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 6.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.45
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.55
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	62 f2 f5 48 40 c2    	vpmullq zmm0,zmm1,zmm2
   6:	90                   	nop
   7:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 2.0
- Reference cycles: 1.23
- UOPS_EXECUTED.THREAD: 2.99
- RETIRE_SLOTS: 7.0
- UOPS_MITE: 7.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.45
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.55
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	62 f2 f5 48 40 c2    	vpmullq zmm0,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.5
- Reference cycles: 0.91
- UOPS_EXECUTED.THREAD: 3.1
- RETIRE_SLOTS: 5.1
- UOPS_MITE: 5.11
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.5
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000, unroll_count=10, and padding (long NOPs)

Code:

   0:	62 f2 f5 48 40 c2    	vpmullq zmm0,zmm1,zmm2
   6:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
   d:	0f 1f 84 00 00 00 00 
  14:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 2.2
- Core cycles: 2.0
- Reference cycles: 1.22
- UOPS_EXECUTED.THREAD: 3.1
- RETIRE_SLOTS: 6.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.45
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.55
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 f2 f5 48 40 c2    	vpmullq zmm0,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.5
- Reference cycles: 0.91
- UOPS_EXECUTED.THREAD: 3.01
- RETIRE_SLOTS: 5.01
- UOPS_MITE: 5.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.5
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=100, unroll_count=100, and padding (long NOPs)

Code:

   0:	62 f2 f5 48 40 c2    	vpmullq zmm0,zmm1,zmm2
   6:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
   d:	0f 1f 84 00 00 00 00 
  14:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 2.02
- Core cycles: 2.0
- Reference cycles: 1.22
- UOPS_EXECUTED.THREAD: 3.01
- RETIRE_SLOTS: 6.01
- UOPS_MITE: 0.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.45
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.55
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 f2 f5 48 40 c2    	vpmullq zmm0,zmm1,zmm2
   6:	62 f2 f5 48 40 da    	vpmullq zmm3,zmm1,zmm2
   c:	62 f2 f5 48 40 e2    	vpmullq zmm4,zmm1,zmm2
  12:	62 f2 f5 48 40 ea    	vpmullq zmm5,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 6.0
- Reference cycles: 3.67
- UOPS_EXECUTED.THREAD: 12.0
- RETIRE_SLOTS: 20.0
- UOPS_MITE: 20.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 6.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 6.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	62 f2 f5 48 40 c2    	vpmullq zmm0,zmm1,zmm2
   6:	62 f2 f5 48 40 da    	vpmullq zmm3,zmm1,zmm2
   c:	62 f2 f5 48 40 e2    	vpmullq zmm4,zmm1,zmm2
  12:	62 f2 f5 48 40 ea    	vpmullq zmm5,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 6.01
- Reference cycles: 3.88
- UOPS_EXECUTED.THREAD: 12.5
- RETIRE_SLOTS: 20.5
- UOPS_MITE: 20.57
- UOPS_MS: 0.0
- UOPS_PORT_0: 6.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 6.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.01

With loop_count=1000, unroll_count=2, and padding (long NOPs)

Code:

   0:	62 f2 f5 48 40 c2    	vpmullq zmm0,zmm1,zmm2
   6:	62 f2 f5 48 40 da    	vpmullq zmm3,zmm1,zmm2
   c:	62 f2 f5 48 40 e2    	vpmullq zmm4,zmm1,zmm2
  12:	62 f2 f5 48 40 ea    	vpmullq zmm5,zmm1,zmm2
  18:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  1f:	0f 1f 84 00 00 00 00 
  26:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.01
- Reference cycles: 4.01
- UOPS_EXECUTED.THREAD: 12.5
- RETIRE_SLOTS: 21.5
- UOPS_MITE: 21.58
- UOPS_MS: 0.0
- UOPS_PORT_0: 6.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 6.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.51

With loop_count=100 and unroll_count=20

Code:

   0:	62 f2 f5 48 40 c2    	vpmullq zmm0,zmm1,zmm2
   6:	62 f2 f5 48 40 da    	vpmullq zmm3,zmm1,zmm2
   c:	62 f2 f5 48 40 e2    	vpmullq zmm4,zmm1,zmm2
  12:	62 f2 f5 48 40 ea    	vpmullq zmm5,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 6.01
- Reference cycles: 3.64
- UOPS_EXECUTED.THREAD: 12.05
- RETIRE_SLOTS: 20.05
- UOPS_MITE: 20.05
- UOPS_MS: 0.0
- UOPS_PORT_0: 6.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 6.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=100, unroll_count=20, and padding (long NOPs)

Code:

   0:	62 f2 f5 48 40 c2    	vpmullq zmm0,zmm1,zmm2
   6:	62 f2 f5 48 40 da    	vpmullq zmm3,zmm1,zmm2
   c:	62 f2 f5 48 40 e2    	vpmullq zmm4,zmm1,zmm2
  12:	62 f2 f5 48 40 ea    	vpmullq zmm5,zmm1,zmm2
  18:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  1f:	0f 1f 84 00 00 00 00 
  26:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 5.1
- Core cycles: 6.01
- Reference cycles: 3.64
- UOPS_EXECUTED.THREAD: 12.05
- RETIRE_SLOTS: 21.05
- UOPS_MITE: 21.09
- UOPS_MS: 0.0
- UOPS_PORT_0: 6.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 6.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.06

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f2 f5 48 40 c2    	vpmullq zmm0,zmm1,zmm2
   6:	62 f2 f5 48 40 da    	vpmullq zmm3,zmm1,zmm2
   c:	62 f2 f5 48 40 e2    	vpmullq zmm4,zmm1,zmm2
  12:	62 f2 f5 48 40 ea    	vpmullq zmm5,zmm1,zmm2
  18:	62 f2 f5 48 40 f2    	vpmullq zmm6,zmm1,zmm2
  1e:	62 f2 f5 48 40 fa    	vpmullq zmm7,zmm1,zmm2
  24:	62 72 f5 48 40 c2    	vpmullq zmm8,zmm1,zmm2
  2a:	62 72 f5 48 40 ca    	vpmullq zmm9,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 11.99
- Reference cycles: 7.73
- UOPS_EXECUTED.THREAD: 23.99
- RETIRE_SLOTS: 40.0
- UOPS_MITE: 39.97
- UOPS_MS: 0.01
- UOPS_PORT_0: 12.0
- UOPS_PORT_1: 0.01
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 12.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.02

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f2 f5 48 40 c2    	vpmullq zmm0,zmm1,zmm2
   6:	62 f2 f5 48 40 da    	vpmullq zmm3,zmm1,zmm2
   c:	62 f2 f5 48 40 e2    	vpmullq zmm4,zmm1,zmm2
  12:	62 f2 f5 48 40 ea    	vpmullq zmm5,zmm1,zmm2
  18:	62 f2 f5 48 40 f2    	vpmullq zmm6,zmm1,zmm2
  1e:	62 f2 f5 48 40 fa    	vpmullq zmm7,zmm1,zmm2
  24:	62 72 f5 48 40 c2    	vpmullq zmm8,zmm1,zmm2
  2a:	62 72 f5 48 40 ca    	vpmullq zmm9,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 12.02
- Reference cycles: 8.0
- UOPS_EXECUTED.THREAD: 25.0
- RETIRE_SLOTS: 41.0
- UOPS_MITE: 41.13
- UOPS_MS: 0.0
- UOPS_PORT_0: 12.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 12.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.02

With loop_count=1000, unroll_count=1, and padding (long NOPs)

Code:

   0:	62 f2 f5 48 40 c2    	vpmullq zmm0,zmm1,zmm2
   6:	62 f2 f5 48 40 da    	vpmullq zmm3,zmm1,zmm2
   c:	62 f2 f5 48 40 e2    	vpmullq zmm4,zmm1,zmm2
  12:	62 f2 f5 48 40 ea    	vpmullq zmm5,zmm1,zmm2
  18:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  1f:	0f 1f 84 00 00 00 00 
  26:	00 
  27:	62 f2 f5 48 40 f2    	vpmullq zmm6,zmm1,zmm2
  2d:	62 f2 f5 48 40 fa    	vpmullq zmm7,zmm1,zmm2
  33:	62 72 f5 48 40 c2    	vpmullq zmm8,zmm1,zmm2
  39:	62 72 f5 48 40 ca    	vpmullq zmm9,zmm1,zmm2
  3f:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  46:	0f 1f 84 00 00 00 00 
  4d:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 12.02
- Reference cycles: 7.28
- UOPS_EXECUTED.THREAD: 25.0
- RETIRE_SLOTS: 43.0
- UOPS_MITE: 43.18
- UOPS_MS: 0.0
- UOPS_PORT_0: 12.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 12.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 9.02

With loop_count=100 and unroll_count=10

Code:

   0:	62 f2 f5 48 40 c2    	vpmullq zmm0,zmm1,zmm2
   6:	62 f2 f5 48 40 da    	vpmullq zmm3,zmm1,zmm2
   c:	62 f2 f5 48 40 e2    	vpmullq zmm4,zmm1,zmm2
  12:	62 f2 f5 48 40 ea    	vpmullq zmm5,zmm1,zmm2
  18:	62 f2 f5 48 40 f2    	vpmullq zmm6,zmm1,zmm2
  1e:	62 f2 f5 48 40 fa    	vpmullq zmm7,zmm1,zmm2
  24:	62 72 f5 48 40 c2    	vpmullq zmm8,zmm1,zmm2
  2a:	62 72 f5 48 40 ca    	vpmullq zmm9,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 12.02
- Reference cycles: 7.28
- UOPS_EXECUTED.THREAD: 24.1
- RETIRE_SLOTS: 40.1
- UOPS_MITE: 40.11
- UOPS_MS: 0.0
- UOPS_PORT_0: 12.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 12.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=100, unroll_count=10, and padding (long NOPs)

Code:

   0:	62 f2 f5 48 40 c2    	vpmullq zmm0,zmm1,zmm2
   6:	62 f2 f5 48 40 da    	vpmullq zmm3,zmm1,zmm2
   c:	62 f2 f5 48 40 e2    	vpmullq zmm4,zmm1,zmm2
  12:	62 f2 f5 48 40 ea    	vpmullq zmm5,zmm1,zmm2
  18:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  1f:	0f 1f 84 00 00 00 00 
  26:	00 
  27:	62 f2 f5 48 40 f2    	vpmullq zmm6,zmm1,zmm2
  2d:	62 f2 f5 48 40 fa    	vpmullq zmm7,zmm1,zmm2
  33:	62 72 f5 48 40 c2    	vpmullq zmm8,zmm1,zmm2
  39:	62 72 f5 48 40 ca    	vpmullq zmm9,zmm1,zmm2
  3f:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  46:	0f 1f 84 00 00 00 00 
  4d:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 10.2
- Core cycles: 12.02
- Reference cycles: 7.29
- UOPS_EXECUTED.THREAD: 24.1
- RETIRE_SLOTS: 42.1
- UOPS_MITE: 42.15
- UOPS_MS: 0.0
- UOPS_PORT_0: 12.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 12.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.12

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f2 f5 48 40 c2    	vpmullq zmm0,zmm1,zmm2
   6:	62 f2 f5 48 40 da    	vpmullq zmm3,zmm1,zmm2
   c:	62 f2 f5 48 40 e2    	vpmullq zmm4,zmm1,zmm2
  12:	62 f2 f5 48 40 ea    	vpmullq zmm5,zmm1,zmm2
  18:	62 f2 f5 48 40 f2    	vpmullq zmm6,zmm1,zmm2
  1e:	62 f2 f5 48 40 fa    	vpmullq zmm7,zmm1,zmm2
  24:	62 72 f5 48 40 c2    	vpmullq zmm8,zmm1,zmm2
  2a:	62 72 f5 48 40 ca    	vpmullq zmm9,zmm1,zmm2
  30:	62 72 f5 48 40 d2    	vpmullq zmm10,zmm1,zmm2
  36:	62 72 f5 48 40 da    	vpmullq zmm11,zmm1,zmm2
  3c:	62 72 f5 48 40 e2    	vpmullq zmm12,zmm1,zmm2
  42:	62 e2 f5 48 40 c2    	vpmullq zmm16,zmm1,zmm2
  48:	62 e2 f5 48 40 ca    	vpmullq zmm17,zmm1,zmm2
  4e:	62 e2 f5 48 40 d2    	vpmullq zmm18,zmm1,zmm2
  54:	62 e2 f5 48 40 da    	vpmullq zmm19,zmm1,zmm2
  5a:	62 e2 f5 48 40 e2    	vpmullq zmm20,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 24.01
- Reference cycles: 16.0
- UOPS_EXECUTED.THREAD: 48.0
- RETIRE_SLOTS: 80.0
- UOPS_MITE: 79.97
- UOPS_MS: 0.0
- UOPS_PORT_0: 24.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 24.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 15.98

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f2 f5 48 40 c2    	vpmullq zmm0,zmm1,zmm2
   6:	62 f2 f5 48 40 da    	vpmullq zmm3,zmm1,zmm2
   c:	62 f2 f5 48 40 e2    	vpmullq zmm4,zmm1,zmm2
  12:	62 f2 f5 48 40 ea    	vpmullq zmm5,zmm1,zmm2
  18:	62 f2 f5 48 40 f2    	vpmullq zmm6,zmm1,zmm2
  1e:	62 f2 f5 48 40 fa    	vpmullq zmm7,zmm1,zmm2
  24:	62 72 f5 48 40 c2    	vpmullq zmm8,zmm1,zmm2
  2a:	62 72 f5 48 40 ca    	vpmullq zmm9,zmm1,zmm2
  30:	62 72 f5 48 40 d2    	vpmullq zmm10,zmm1,zmm2
  36:	62 72 f5 48 40 da    	vpmullq zmm11,zmm1,zmm2
  3c:	62 72 f5 48 40 e2    	vpmullq zmm12,zmm1,zmm2
  42:	62 e2 f5 48 40 c2    	vpmullq zmm16,zmm1,zmm2
  48:	62 e2 f5 48 40 ca    	vpmullq zmm17,zmm1,zmm2
  4e:	62 e2 f5 48 40 d2    	vpmullq zmm18,zmm1,zmm2
  54:	62 e2 f5 48 40 da    	vpmullq zmm19,zmm1,zmm2
  5a:	62 e2 f5 48 40 e2    	vpmullq zmm20,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 24.02
- Reference cycles: 16.04
- UOPS_EXECUTED.THREAD: 49.0
- RETIRE_SLOTS: 81.01
- UOPS_MITE: 81.1
- UOPS_MS: 0.0
- UOPS_PORT_0: 24.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 24.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.02

With loop_count=1000, unroll_count=1, and padding (long NOPs)

Code:

   0:	62 f2 f5 48 40 c2    	vpmullq zmm0,zmm1,zmm2
   6:	62 f2 f5 48 40 da    	vpmullq zmm3,zmm1,zmm2
   c:	62 f2 f5 48 40 e2    	vpmullq zmm4,zmm1,zmm2
  12:	62 f2 f5 48 40 ea    	vpmullq zmm5,zmm1,zmm2
  18:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  1f:	0f 1f 84 00 00 00 00 
  26:	00 
  27:	62 f2 f5 48 40 f2    	vpmullq zmm6,zmm1,zmm2
  2d:	62 f2 f5 48 40 fa    	vpmullq zmm7,zmm1,zmm2
  33:	62 72 f5 48 40 c2    	vpmullq zmm8,zmm1,zmm2
  39:	62 72 f5 48 40 ca    	vpmullq zmm9,zmm1,zmm2
  3f:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  46:	0f 1f 84 00 00 00 00 
  4d:	00 
  4e:	62 72 f5 48 40 d2    	vpmullq zmm10,zmm1,zmm2
  54:	62 72 f5 48 40 da    	vpmullq zmm11,zmm1,zmm2
  5a:	62 72 f5 48 40 e2    	vpmullq zmm12,zmm1,zmm2
  60:	62 e2 f5 48 40 c2    	vpmullq zmm16,zmm1,zmm2
  66:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  6d:	0f 1f 84 00 00 00 00 
  74:	00 
  75:	62 e2 f5 48 40 ca    	vpmullq zmm17,zmm1,zmm2
  7b:	62 e2 f5 48 40 d2    	vpmullq zmm18,zmm1,zmm2
  81:	62 e2 f5 48 40 da    	vpmullq zmm19,zmm1,zmm2
  87:	62 e2 f5 48 40 e2    	vpmullq zmm20,zmm1,zmm2
  8d:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  94:	0f 1f 84 00 00 00 00 
  9b:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 22.0
- Core cycles: 24.02
- Reference cycles: 14.57
- UOPS_EXECUTED.THREAD: 49.0
- RETIRE_SLOTS: 85.02
- UOPS_MITE: 85.17
- UOPS_MS: -0.03
- UOPS_PORT_0: 24.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 24.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 17.03

With loop_count=100 and unroll_count=10

Code:

   0:	62 f2 f5 48 40 c2    	vpmullq zmm0,zmm1,zmm2
   6:	62 f2 f5 48 40 da    	vpmullq zmm3,zmm1,zmm2
   c:	62 f2 f5 48 40 e2    	vpmullq zmm4,zmm1,zmm2
  12:	62 f2 f5 48 40 ea    	vpmullq zmm5,zmm1,zmm2
  18:	62 f2 f5 48 40 f2    	vpmullq zmm6,zmm1,zmm2
  1e:	62 f2 f5 48 40 fa    	vpmullq zmm7,zmm1,zmm2
  24:	62 72 f5 48 40 c2    	vpmullq zmm8,zmm1,zmm2
  2a:	62 72 f5 48 40 ca    	vpmullq zmm9,zmm1,zmm2
  30:	62 72 f5 48 40 d2    	vpmullq zmm10,zmm1,zmm2
  36:	62 72 f5 48 40 da    	vpmullq zmm11,zmm1,zmm2
  3c:	62 72 f5 48 40 e2    	vpmullq zmm12,zmm1,zmm2
  42:	62 e2 f5 48 40 c2    	vpmullq zmm16,zmm1,zmm2
  48:	62 e2 f5 48 40 ca    	vpmullq zmm17,zmm1,zmm2
  4e:	62 e2 f5 48 40 d2    	vpmullq zmm18,zmm1,zmm2
  54:	62 e2 f5 48 40 da    	vpmullq zmm19,zmm1,zmm2
  5a:	62 e2 f5 48 40 e2    	vpmullq zmm20,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 24.02
- Reference cycles: 14.56
- UOPS_EXECUTED.THREAD: 48.1
- RETIRE_SLOTS: 80.1
- UOPS_MITE: 80.15
- UOPS_MS: 0.0
- UOPS_PORT_0: 24.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 24.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.0

With loop_count=100, unroll_count=10, and padding (long NOPs)

Code:

   0:	62 f2 f5 48 40 c2    	vpmullq zmm0,zmm1,zmm2
   6:	62 f2 f5 48 40 da    	vpmullq zmm3,zmm1,zmm2
   c:	62 f2 f5 48 40 e2    	vpmullq zmm4,zmm1,zmm2
  12:	62 f2 f5 48 40 ea    	vpmullq zmm5,zmm1,zmm2
  18:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  1f:	0f 1f 84 00 00 00 00 
  26:	00 
  27:	62 f2 f5 48 40 f2    	vpmullq zmm6,zmm1,zmm2
  2d:	62 f2 f5 48 40 fa    	vpmullq zmm7,zmm1,zmm2
  33:	62 72 f5 48 40 c2    	vpmullq zmm8,zmm1,zmm2
  39:	62 72 f5 48 40 ca    	vpmullq zmm9,zmm1,zmm2
  3f:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  46:	0f 1f 84 00 00 00 00 
  4d:	00 
  4e:	62 72 f5 48 40 d2    	vpmullq zmm10,zmm1,zmm2
  54:	62 72 f5 48 40 da    	vpmullq zmm11,zmm1,zmm2
  5a:	62 72 f5 48 40 e2    	vpmullq zmm12,zmm1,zmm2
  60:	62 e2 f5 48 40 c2    	vpmullq zmm16,zmm1,zmm2
  66:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  6d:	0f 1f 84 00 00 00 00 
  74:	00 
  75:	62 e2 f5 48 40 ca    	vpmullq zmm17,zmm1,zmm2
  7b:	62 e2 f5 48 40 d2    	vpmullq zmm18,zmm1,zmm2
  81:	62 e2 f5 48 40 da    	vpmullq zmm19,zmm1,zmm2
  87:	62 e2 f5 48 40 e2    	vpmullq zmm20,zmm1,zmm2
  8d:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  94:	0f 1f 84 00 00 00 00 
  9b:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 20.2
- Core cycles: 24.02
- Reference cycles: 14.57
- UOPS_EXECUTED.THREAD: 48.1
- RETIRE_SLOTS: 84.1
- UOPS_MITE: 84.1
- UOPS_MS: 0.0
- UOPS_PORT_0: 24.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 24.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.1

With the same register for for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	62 f2 fd 48 40 c0    	vpmullq zmm0,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 16.23
- Reference cycles: 9.52
- UOPS_EXECUTED.THREAD: 3.01
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.49
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.51
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	62 f2 fd 48 40 c0    	vpmullq zmm0,zmm0,zmm0
   6:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 16.25
- Reference cycles: 10.88
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 6.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.49
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.51
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	62 f2 fd 48 40 c0    	vpmullq zmm0,zmm0,zmm0
   6:	90                   	nop
   7:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 16.27
- Reference cycles: 9.6
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 7.0
- UOPS_MITE: 7.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.49
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.51
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	62 f2 fd 48 40 c0    	vpmullq zmm0,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 16.18
- Reference cycles: 10.21
- UOPS_EXECUTED.THREAD: 3.1
- RETIRE_SLOTS: 5.1
- UOPS_MITE: 5.11
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.49
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.51
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000, unroll_count=10, and padding (long NOPs)

Code:

   0:	62 f2 fd 48 40 c0    	vpmullq zmm0,zmm0,zmm0
   6:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
   d:	0f 1f 84 00 00 00 00 
  14:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 2.2
- Core cycles: 16.25
- Reference cycles: 10.29
- UOPS_EXECUTED.THREAD: 3.1
- RETIRE_SLOTS: 6.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.49
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.51
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 f2 fd 48 40 c0    	vpmullq zmm0,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 16.12
- Reference cycles: 9.49
- UOPS_EXECUTED.THREAD: 3.01
- RETIRE_SLOTS: 5.01
- UOPS_MITE: 5.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.49
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.51
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=100, unroll_count=100, and padding (long NOPs)

Code:

   0:	62 f2 fd 48 40 c0    	vpmullq zmm0,zmm0,zmm0
   6:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
   d:	0f 1f 84 00 00 00 00 
  14:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 2.02
- Core cycles: 16.26
- Reference cycles: 9.57
- UOPS_EXECUTED.THREAD: 3.01
- RETIRE_SLOTS: 6.01
- UOPS_MITE: 0.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.49
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.51
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 f2 fd 48 40 c0    	vpmullq zmm0,zmm0,zmm0
   6:	62 f2 f5 48 40 c9    	vpmullq zmm1,zmm1,zmm1
   c:	62 f2 ed 48 40 d2    	vpmullq zmm2,zmm2,zmm2
  12:	62 f2 e5 48 40 db    	vpmullq zmm3,zmm3,zmm3

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 16.33
- Reference cycles: 10.6
- UOPS_EXECUTED.THREAD: 12.01
- RETIRE_SLOTS: 20.0
- UOPS_MITE: 20.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 5.94
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 6.06
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	62 f2 fd 48 40 c0    	vpmullq zmm0,zmm0,zmm0
   6:	62 f2 f5 48 40 c9    	vpmullq zmm1,zmm1,zmm1
   c:	62 f2 ed 48 40 d2    	vpmullq zmm2,zmm2,zmm2
  12:	62 f2 e5 48 40 db    	vpmullq zmm3,zmm3,zmm3

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 16.31
- Reference cycles: 10.88
- UOPS_EXECUTED.THREAD: 12.5
- RETIRE_SLOTS: 20.5
- UOPS_MITE: 20.57
- UOPS_MS: 0.0
- UOPS_PORT_0: 5.94
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 6.06
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.01

With loop_count=1000, unroll_count=2, and padding (long NOPs)

Code:

   0:	62 f2 fd 48 40 c0    	vpmullq zmm0,zmm0,zmm0
   6:	62 f2 f5 48 40 c9    	vpmullq zmm1,zmm1,zmm1
   c:	62 f2 ed 48 40 d2    	vpmullq zmm2,zmm2,zmm2
  12:	62 f2 e5 48 40 db    	vpmullq zmm3,zmm3,zmm3
  18:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  1f:	0f 1f 84 00 00 00 00 
  26:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 16.31
- Reference cycles: 9.89
- UOPS_EXECUTED.THREAD: 12.5
- RETIRE_SLOTS: 21.5
- UOPS_MITE: 21.55
- UOPS_MS: 0.0
- UOPS_PORT_0: 5.94
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 6.06
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.51

With loop_count=100 and unroll_count=20

Code:

   0:	62 f2 fd 48 40 c0    	vpmullq zmm0,zmm0,zmm0
   6:	62 f2 f5 48 40 c9    	vpmullq zmm1,zmm1,zmm1
   c:	62 f2 ed 48 40 d2    	vpmullq zmm2,zmm2,zmm2
  12:	62 f2 e5 48 40 db    	vpmullq zmm3,zmm3,zmm3

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 16.31
- Reference cycles: 9.89
- UOPS_EXECUTED.THREAD: 12.05
- RETIRE_SLOTS: 20.05
- UOPS_MITE: 20.05
- UOPS_MS: 0.0
- UOPS_PORT_0: 5.94
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 6.06
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=100, unroll_count=20, and padding (long NOPs)

Code:

   0:	62 f2 fd 48 40 c0    	vpmullq zmm0,zmm0,zmm0
   6:	62 f2 f5 48 40 c9    	vpmullq zmm1,zmm1,zmm1
   c:	62 f2 ed 48 40 d2    	vpmullq zmm2,zmm2,zmm2
  12:	62 f2 e5 48 40 db    	vpmullq zmm3,zmm3,zmm3
  18:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  1f:	0f 1f 84 00 00 00 00 
  26:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3

Show nanoBench command
Results:
- Instructions retired: 5.1
- Core cycles: 16.32
- Reference cycles: 9.9
- UOPS_EXECUTED.THREAD: 12.05
- RETIRE_SLOTS: 21.05
- UOPS_MITE: 21.07
- UOPS_MS: 0.0
- UOPS_PORT_0: 5.94
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 6.06
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.06

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f2 fd 48 40 c0    	vpmullq zmm0,zmm0,zmm0
   6:	62 f2 f5 48 40 c9    	vpmullq zmm1,zmm1,zmm1
   c:	62 f2 ed 48 40 d2    	vpmullq zmm2,zmm2,zmm2
  12:	62 f2 e5 48 40 db    	vpmullq zmm3,zmm3,zmm3
  18:	62 f2 dd 48 40 e4    	vpmullq zmm4,zmm4,zmm4
  1e:	62 f2 d5 48 40 ed    	vpmullq zmm5,zmm5,zmm5
  24:	62 f2 cd 48 40 f6    	vpmullq zmm6,zmm6,zmm6
  2a:	62 f2 c5 48 40 ff    	vpmullq zmm7,zmm7,zmm7

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 17.33
- Reference cycles: 11.73
- UOPS_EXECUTED.THREAD: 24.0
- RETIRE_SLOTS: 40.0
- UOPS_MITE: 40.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 11.83
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 12.17
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f2 fd 48 40 c0    	vpmullq zmm0,zmm0,zmm0
   6:	62 f2 f5 48 40 c9    	vpmullq zmm1,zmm1,zmm1
   c:	62 f2 ed 48 40 d2    	vpmullq zmm2,zmm2,zmm2
  12:	62 f2 e5 48 40 db    	vpmullq zmm3,zmm3,zmm3
  18:	62 f2 dd 48 40 e4    	vpmullq zmm4,zmm4,zmm4
  1e:	62 f2 d5 48 40 ed    	vpmullq zmm5,zmm5,zmm5
  24:	62 f2 cd 48 40 f6    	vpmullq zmm6,zmm6,zmm6
  2a:	62 f2 c5 48 40 ff    	vpmullq zmm7,zmm7,zmm7

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 17.39
- Reference cycles: 11.56
- UOPS_EXECUTED.THREAD: 25.0
- RETIRE_SLOTS: 41.0
- UOPS_MITE: 41.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 11.84
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 12.16
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.02

With loop_count=1000, unroll_count=1, and padding (long NOPs)

Code:

   0:	62 f2 fd 48 40 c0    	vpmullq zmm0,zmm0,zmm0
   6:	62 f2 f5 48 40 c9    	vpmullq zmm1,zmm1,zmm1
   c:	62 f2 ed 48 40 d2    	vpmullq zmm2,zmm2,zmm2
  12:	62 f2 e5 48 40 db    	vpmullq zmm3,zmm3,zmm3
  18:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  1f:	0f 1f 84 00 00 00 00 
  26:	00 
  27:	62 f2 dd 48 40 e4    	vpmullq zmm4,zmm4,zmm4
  2d:	62 f2 d5 48 40 ed    	vpmullq zmm5,zmm5,zmm5
  33:	62 f2 cd 48 40 f6    	vpmullq zmm6,zmm6,zmm6
  39:	62 f2 c5 48 40 ff    	vpmullq zmm7,zmm7,zmm7
  3f:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  46:	0f 1f 84 00 00 00 00 
  4d:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 17.41
- Reference cycles: 10.24
- UOPS_EXECUTED.THREAD: 25.0
- RETIRE_SLOTS: 43.0
- UOPS_MITE: 43.1
- UOPS_MS: 0.0
- UOPS_PORT_0: 11.84
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 12.16
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 9.03

With loop_count=100 and unroll_count=10

Code:

   0:	62 f2 fd 48 40 c0    	vpmullq zmm0,zmm0,zmm0
   6:	62 f2 f5 48 40 c9    	vpmullq zmm1,zmm1,zmm1
   c:	62 f2 ed 48 40 d2    	vpmullq zmm2,zmm2,zmm2
  12:	62 f2 e5 48 40 db    	vpmullq zmm3,zmm3,zmm3
  18:	62 f2 dd 48 40 e4    	vpmullq zmm4,zmm4,zmm4
  1e:	62 f2 d5 48 40 ed    	vpmullq zmm5,zmm5,zmm5
  24:	62 f2 cd 48 40 f6    	vpmullq zmm6,zmm6,zmm6
  2a:	62 f2 c5 48 40 ff    	vpmullq zmm7,zmm7,zmm7

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 17.32
- Reference cycles: 10.49
- UOPS_EXECUTED.THREAD: 24.1
- RETIRE_SLOTS: 40.1
- UOPS_MITE: 40.1
- UOPS_MS: 0.0
- UOPS_PORT_0: 11.84
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 12.16
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=100, unroll_count=10, and padding (long NOPs)

Code:

   0:	62 f2 fd 48 40 c0    	vpmullq zmm0,zmm0,zmm0
   6:	62 f2 f5 48 40 c9    	vpmullq zmm1,zmm1,zmm1
   c:	62 f2 ed 48 40 d2    	vpmullq zmm2,zmm2,zmm2
  12:	62 f2 e5 48 40 db    	vpmullq zmm3,zmm3,zmm3
  18:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  1f:	0f 1f 84 00 00 00 00 
  26:	00 
  27:	62 f2 dd 48 40 e4    	vpmullq zmm4,zmm4,zmm4
  2d:	62 f2 d5 48 40 ed    	vpmullq zmm5,zmm5,zmm5
  33:	62 f2 cd 48 40 f6    	vpmullq zmm6,zmm6,zmm6
  39:	62 f2 c5 48 40 ff    	vpmullq zmm7,zmm7,zmm7
  3f:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  46:	0f 1f 84 00 00 00 00 
  4d:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7

Show nanoBench command
Results:
- Instructions retired: 10.2
- Core cycles: 17.35
- Reference cycles: 10.52
- UOPS_EXECUTED.THREAD: 24.1
- RETIRE_SLOTS: 42.1
- UOPS_MITE: 42.18
- UOPS_MS: 0.0
- UOPS_PORT_0: 11.84
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 12.16
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.12

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f2 fd 48 40 c0    	vpmullq zmm0,zmm0,zmm0
   6:	62 f2 f5 48 40 c9    	vpmullq zmm1,zmm1,zmm1
   c:	62 f2 ed 48 40 d2    	vpmullq zmm2,zmm2,zmm2
  12:	62 f2 e5 48 40 db    	vpmullq zmm3,zmm3,zmm3
  18:	62 f2 dd 48 40 e4    	vpmullq zmm4,zmm4,zmm4
  1e:	62 f2 d5 48 40 ed    	vpmullq zmm5,zmm5,zmm5
  24:	62 f2 cd 48 40 f6    	vpmullq zmm6,zmm6,zmm6
  2a:	62 f2 c5 48 40 ff    	vpmullq zmm7,zmm7,zmm7
  30:	62 52 bd 48 40 c0    	vpmullq zmm8,zmm8,zmm8
  36:	62 52 b5 48 40 c9    	vpmullq zmm9,zmm9,zmm9
  3c:	62 52 ad 48 40 d2    	vpmullq zmm10,zmm10,zmm10
  42:	62 52 a5 48 40 db    	vpmullq zmm11,zmm11,zmm11
  48:	62 52 9d 48 40 e4    	vpmullq zmm12,zmm12,zmm12
  4e:	62 a2 fd 40 40 c0    	vpmullq zmm16,zmm16,zmm16
  54:	62 a2 f5 40 40 c9    	vpmullq zmm17,zmm17,zmm17
  5a:	62 a2 ed 40 40 d2    	vpmullq zmm18,zmm18,zmm18

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7;
VXORPS ZMM8, ZMM8, ZMM8;
VXORPS ZMM9, ZMM9, ZMM9;
VXORPS ZMM10, ZMM10, ZMM10;
VXORPS ZMM11, ZMM11, ZMM11;
VXORPS ZMM12, ZMM12, ZMM12;
VXORPS ZMM16, ZMM16, ZMM16;
VXORPS ZMM17, ZMM17, ZMM17;
VXORPS ZMM18, ZMM18, ZMM18

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 24.0
- Reference cycles: 15.87
- UOPS_EXECUTED.THREAD: 47.97
- RETIRE_SLOTS: 80.0
- UOPS_MITE: 79.94
- UOPS_MS: 0.01
- UOPS_PORT_0: 24.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 24.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 15.99

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f2 fd 48 40 c0    	vpmullq zmm0,zmm0,zmm0
   6:	62 f2 f5 48 40 c9    	vpmullq zmm1,zmm1,zmm1
   c:	62 f2 ed 48 40 d2    	vpmullq zmm2,zmm2,zmm2
  12:	62 f2 e5 48 40 db    	vpmullq zmm3,zmm3,zmm3
  18:	62 f2 dd 48 40 e4    	vpmullq zmm4,zmm4,zmm4
  1e:	62 f2 d5 48 40 ed    	vpmullq zmm5,zmm5,zmm5
  24:	62 f2 cd 48 40 f6    	vpmullq zmm6,zmm6,zmm6
  2a:	62 f2 c5 48 40 ff    	vpmullq zmm7,zmm7,zmm7
  30:	62 52 bd 48 40 c0    	vpmullq zmm8,zmm8,zmm8
  36:	62 52 b5 48 40 c9    	vpmullq zmm9,zmm9,zmm9
  3c:	62 52 ad 48 40 d2    	vpmullq zmm10,zmm10,zmm10
  42:	62 52 a5 48 40 db    	vpmullq zmm11,zmm11,zmm11
  48:	62 52 9d 48 40 e4    	vpmullq zmm12,zmm12,zmm12
  4e:	62 a2 fd 40 40 c0    	vpmullq zmm16,zmm16,zmm16
  54:	62 a2 f5 40 40 c9    	vpmullq zmm17,zmm17,zmm17
  5a:	62 a2 ed 40 40 d2    	vpmullq zmm18,zmm18,zmm18

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7;
VXORPS ZMM8, ZMM8, ZMM8;
VXORPS ZMM9, ZMM9, ZMM9;
VXORPS ZMM10, ZMM10, ZMM10;
VXORPS ZMM11, ZMM11, ZMM11;
VXORPS ZMM12, ZMM12, ZMM12;
VXORPS ZMM16, ZMM16, ZMM16;
VXORPS ZMM17, ZMM17, ZMM17;
VXORPS ZMM18, ZMM18, ZMM18

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 24.02
- Reference cycles: 14.56
- UOPS_EXECUTED.THREAD: 49.0
- RETIRE_SLOTS: 81.01
- UOPS_MITE: 81.1
- UOPS_MS: 0.0
- UOPS_PORT_0: 24.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 24.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.03

With loop_count=1000, unroll_count=1, and padding (long NOPs)

Code:

   0:	62 f2 fd 48 40 c0    	vpmullq zmm0,zmm0,zmm0
   6:	62 f2 f5 48 40 c9    	vpmullq zmm1,zmm1,zmm1
   c:	62 f2 ed 48 40 d2    	vpmullq zmm2,zmm2,zmm2
  12:	62 f2 e5 48 40 db    	vpmullq zmm3,zmm3,zmm3
  18:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  1f:	0f 1f 84 00 00 00 00 
  26:	00 
  27:	62 f2 dd 48 40 e4    	vpmullq zmm4,zmm4,zmm4
  2d:	62 f2 d5 48 40 ed    	vpmullq zmm5,zmm5,zmm5
  33:	62 f2 cd 48 40 f6    	vpmullq zmm6,zmm6,zmm6
  39:	62 f2 c5 48 40 ff    	vpmullq zmm7,zmm7,zmm7
  3f:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  46:	0f 1f 84 00 00 00 00 
  4d:	00 
  4e:	62 52 bd 48 40 c0    	vpmullq zmm8,zmm8,zmm8
  54:	62 52 b5 48 40 c9    	vpmullq zmm9,zmm9,zmm9
  5a:	62 52 ad 48 40 d2    	vpmullq zmm10,zmm10,zmm10
  60:	62 52 a5 48 40 db    	vpmullq zmm11,zmm11,zmm11
  66:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  6d:	0f 1f 84 00 00 00 00 
  74:	00 
  75:	62 52 9d 48 40 e4    	vpmullq zmm12,zmm12,zmm12
  7b:	62 a2 fd 40 40 c0    	vpmullq zmm16,zmm16,zmm16
  81:	62 a2 f5 40 40 c9    	vpmullq zmm17,zmm17,zmm17
  87:	62 a2 ed 40 40 d2    	vpmullq zmm18,zmm18,zmm18
  8d:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  94:	0f 1f 84 00 00 00 00 
  9b:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7;
VXORPS ZMM8, ZMM8, ZMM8;
VXORPS ZMM9, ZMM9, ZMM9;
VXORPS ZMM10, ZMM10, ZMM10;
VXORPS ZMM11, ZMM11, ZMM11;
VXORPS ZMM12, ZMM12, ZMM12;
VXORPS ZMM16, ZMM16, ZMM16;
VXORPS ZMM17, ZMM17, ZMM17;
VXORPS ZMM18, ZMM18, ZMM18

Show nanoBench command
Results:
- Instructions retired: 22.0
- Core cycles: 24.02
- Reference cycles: 14.57
- UOPS_EXECUTED.THREAD: 49.0
- RETIRE_SLOTS: 85.02
- UOPS_MITE: 85.18
- UOPS_MS: -0.03
- UOPS_PORT_0: 24.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 24.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 17.03

With loop_count=100 and unroll_count=10

Code:

   0:	62 f2 fd 48 40 c0    	vpmullq zmm0,zmm0,zmm0
   6:	62 f2 f5 48 40 c9    	vpmullq zmm1,zmm1,zmm1
   c:	62 f2 ed 48 40 d2    	vpmullq zmm2,zmm2,zmm2
  12:	62 f2 e5 48 40 db    	vpmullq zmm3,zmm3,zmm3
  18:	62 f2 dd 48 40 e4    	vpmullq zmm4,zmm4,zmm4
  1e:	62 f2 d5 48 40 ed    	vpmullq zmm5,zmm5,zmm5
  24:	62 f2 cd 48 40 f6    	vpmullq zmm6,zmm6,zmm6
  2a:	62 f2 c5 48 40 ff    	vpmullq zmm7,zmm7,zmm7
  30:	62 52 bd 48 40 c0    	vpmullq zmm8,zmm8,zmm8
  36:	62 52 b5 48 40 c9    	vpmullq zmm9,zmm9,zmm9
  3c:	62 52 ad 48 40 d2    	vpmullq zmm10,zmm10,zmm10
  42:	62 52 a5 48 40 db    	vpmullq zmm11,zmm11,zmm11
  48:	62 52 9d 48 40 e4    	vpmullq zmm12,zmm12,zmm12
  4e:	62 a2 fd 40 40 c0    	vpmullq zmm16,zmm16,zmm16
  54:	62 a2 f5 40 40 c9    	vpmullq zmm17,zmm17,zmm17
  5a:	62 a2 ed 40 40 d2    	vpmullq zmm18,zmm18,zmm18

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7;
VXORPS ZMM8, ZMM8, ZMM8;
VXORPS ZMM9, ZMM9, ZMM9;
VXORPS ZMM10, ZMM10, ZMM10;
VXORPS ZMM11, ZMM11, ZMM11;
VXORPS ZMM12, ZMM12, ZMM12;
VXORPS ZMM16, ZMM16, ZMM16;
VXORPS ZMM17, ZMM17, ZMM17;
VXORPS ZMM18, ZMM18, ZMM18

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 24.02
- Reference cycles: 14.56
- UOPS_EXECUTED.THREAD: 48.1
- RETIRE_SLOTS: 80.1
- UOPS_MITE: 80.13
- UOPS_MS: 0.0
- UOPS_PORT_0: 24.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 24.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.01

With loop_count=100, unroll_count=10, and padding (long NOPs)

Code:

   0:	62 f2 fd 48 40 c0    	vpmullq zmm0,zmm0,zmm0
   6:	62 f2 f5 48 40 c9    	vpmullq zmm1,zmm1,zmm1
   c:	62 f2 ed 48 40 d2    	vpmullq zmm2,zmm2,zmm2
  12:	62 f2 e5 48 40 db    	vpmullq zmm3,zmm3,zmm3
  18:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  1f:	0f 1f 84 00 00 00 00 
  26:	00 
  27:	62 f2 dd 48 40 e4    	vpmullq zmm4,zmm4,zmm4
  2d:	62 f2 d5 48 40 ed    	vpmullq zmm5,zmm5,zmm5
  33:	62 f2 cd 48 40 f6    	vpmullq zmm6,zmm6,zmm6
  39:	62 f2 c5 48 40 ff    	vpmullq zmm7,zmm7,zmm7
  3f:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  46:	0f 1f 84 00 00 00 00 
  4d:	00 
  4e:	62 52 bd 48 40 c0    	vpmullq zmm8,zmm8,zmm8
  54:	62 52 b5 48 40 c9    	vpmullq zmm9,zmm9,zmm9
  5a:	62 52 ad 48 40 d2    	vpmullq zmm10,zmm10,zmm10
  60:	62 52 a5 48 40 db    	vpmullq zmm11,zmm11,zmm11
  66:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  6d:	0f 1f 84 00 00 00 00 
  74:	00 
  75:	62 52 9d 48 40 e4    	vpmullq zmm12,zmm12,zmm12
  7b:	62 a2 fd 40 40 c0    	vpmullq zmm16,zmm16,zmm16
  81:	62 a2 f5 40 40 c9    	vpmullq zmm17,zmm17,zmm17
  87:	62 a2 ed 40 40 d2    	vpmullq zmm18,zmm18,zmm18
  8d:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  94:	0f 1f 84 00 00 00 00 
  9b:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7;
VXORPS ZMM8, ZMM8, ZMM8;
VXORPS ZMM9, ZMM9, ZMM9;
VXORPS ZMM10, ZMM10, ZMM10;
VXORPS ZMM11, ZMM11, ZMM11;
VXORPS ZMM12, ZMM12, ZMM12;
VXORPS ZMM16, ZMM16, ZMM16;
VXORPS ZMM17, ZMM17, ZMM17;
VXORPS ZMM18, ZMM18, ZMM18

Show nanoBench command
Results:
- Instructions retired: 20.2
- Core cycles: 24.02
- Reference cycles: 14.56
- UOPS_EXECUTED.THREAD: 48.1
- RETIRE_SLOTS: 84.1
- UOPS_MITE: 84.1
- UOPS_MS: 0.0
- UOPS_PORT_0: 24.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 24.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.1

VPMULLQ (ZMM, ZMM, ZMM) - Throughput and Uops

With different registers for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=1000, unroll_count=10, and padding (long NOPs)

With loop_count=100 and unroll_count=100

With loop_count=100, unroll_count=100, and padding (long NOPs)

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=1000, unroll_count=2, and padding (long NOPs)

With loop_count=100 and unroll_count=20

With loop_count=100, unroll_count=20, and padding (long NOPs)

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (long NOPs)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (long NOPs)

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (long NOPs)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (long NOPs)

With the same register for for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=1000, unroll_count=10, and padding (long NOPs)

With loop_count=100 and unroll_count=100

With loop_count=100, unroll_count=100, and padding (long NOPs)

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=1000, unroll_count=2, and padding (long NOPs)

With loop_count=100 and unroll_count=20

With loop_count=100, unroll_count=20, and padding (long NOPs)

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (long NOPs)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (long NOPs)

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (long NOPs)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (long NOPs)