VPCMPEQW (K, ZMM, ZMM)

With unroll_count=500 and no inner loop

Code:

   0:	62 f1 7d 48 75 c9    	vpcmpeqw k1,zmm0,zmm1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.72
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.18

With loop_count=1000 and unroll_count=10

Code:

   0:	62 f1 7d 48 75 c9    	vpcmpeqw k1,zmm0,zmm1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 0.67
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 f1 7d 48 75 c9    	vpcmpeqw k1,zmm0,zmm1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 0.61
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 f1 7d 48 75 c9    	vpcmpeqw k1,zmm0,zmm1
   6:	62 f1 7d 48 75 d1    	vpcmpeqw k2,zmm0,zmm1
   c:	62 f1 7d 48 75 d9    	vpcmpeqw k3,zmm0,zmm1
  12:	62 f1 7d 48 75 e1    	vpcmpeqw k4,zmm0,zmm1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 2.27
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 4.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.72

With loop_count=1000 and unroll_count=2

Code:

   0:	62 f1 7d 48 75 c9    	vpcmpeqw k1,zmm0,zmm1
   6:	62 f1 7d 48 75 d1    	vpcmpeqw k2,zmm0,zmm1
   c:	62 f1 7d 48 75 d9    	vpcmpeqw k3,zmm0,zmm1
  12:	62 f1 7d 48 75 e1    	vpcmpeqw k4,zmm0,zmm1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.0
- Reference cycles: 2.68
- UOPS_EXECUTED.THREAD: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 4.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	62 f1 7d 48 75 c9    	vpcmpeqw k1,zmm0,zmm1
   6:	62 f1 7d 48 75 d1    	vpcmpeqw k2,zmm0,zmm1
   c:	62 f1 7d 48 75 d9    	vpcmpeqw k3,zmm0,zmm1
  12:	62 f1 7d 48 75 e1    	vpcmpeqw k4,zmm0,zmm1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.0
- Reference cycles: 2.41
- UOPS_EXECUTED.THREAD: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.05
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 4.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 7 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f1 7d 48 75 c9    	vpcmpeqw k1,zmm0,zmm1
   6:	62 f1 7d 48 75 d1    	vpcmpeqw k2,zmm0,zmm1
   c:	62 f1 7d 48 75 d9    	vpcmpeqw k3,zmm0,zmm1
  12:	62 f1 7d 48 75 e1    	vpcmpeqw k4,zmm0,zmm1
  18:	62 f1 7d 48 75 e9    	vpcmpeqw k5,zmm0,zmm1
  1e:	62 f1 7d 48 75 f1    	vpcmpeqw k6,zmm0,zmm1
  24:	62 f1 7d 48 75 f9    	vpcmpeqw k7,zmm0,zmm1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 7.06
- Reference cycles: 4.8
- UOPS_EXECUTED.THREAD: 7.0
- RETIRE_SLOTS: 7.0
- UOPS_MITE: 7.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 7.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.3

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f1 7d 48 75 c9    	vpcmpeqw k1,zmm0,zmm1
   6:	62 f1 7d 48 75 d1    	vpcmpeqw k2,zmm0,zmm1
   c:	62 f1 7d 48 75 d9    	vpcmpeqw k3,zmm0,zmm1
  12:	62 f1 7d 48 75 e1    	vpcmpeqw k4,zmm0,zmm1
  18:	62 f1 7d 48 75 e9    	vpcmpeqw k5,zmm0,zmm1
  1e:	62 f1 7d 48 75 f1    	vpcmpeqw k6,zmm0,zmm1
  24:	62 f1 7d 48 75 f9    	vpcmpeqw k7,zmm0,zmm1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 7.01
- Reference cycles: 4.68
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 7.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	62 f1 7d 48 75 c9    	vpcmpeqw k1,zmm0,zmm1
   6:	62 f1 7d 48 75 d1    	vpcmpeqw k2,zmm0,zmm1
   c:	62 f1 7d 48 75 d9    	vpcmpeqw k3,zmm0,zmm1
  12:	62 f1 7d 48 75 e1    	vpcmpeqw k4,zmm0,zmm1
  18:	62 f1 7d 48 75 e9    	vpcmpeqw k5,zmm0,zmm1
  1e:	62 f1 7d 48 75 f1    	vpcmpeqw k6,zmm0,zmm1
  24:	62 f1 7d 48 75 f9    	vpcmpeqw k7,zmm0,zmm1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 7.2
- Core cycles: 7.0
- Reference cycles: 4.24
- UOPS_EXECUTED.THREAD: 7.1
- RETIRE_SLOTS: 7.1
- UOPS_MITE: 0.07
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 7.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With the same register for for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	62 f1 7d 48 75 c8    	vpcmpeqw k1,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.64
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.18

With loop_count=1000 and unroll_count=10

Code:

   0:	62 f1 7d 48 75 c8    	vpcmpeqw k1,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 0.61
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 f1 7d 48 75 c8    	vpcmpeqw k1,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 0.61
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 f1 7d 48 75 c8    	vpcmpeqw k1,zmm0,zmm0
   6:	62 f1 75 48 75 d1    	vpcmpeqw k2,zmm1,zmm1
   c:	62 f1 6d 48 75 da    	vpcmpeqw k3,zmm2,zmm2
  12:	62 f1 65 48 75 e3    	vpcmpeqw k4,zmm3,zmm3

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 2.4
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 4.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.73

With loop_count=1000 and unroll_count=2

Code:

   0:	62 f1 7d 48 75 c8    	vpcmpeqw k1,zmm0,zmm0
   6:	62 f1 75 48 75 d1    	vpcmpeqw k2,zmm1,zmm1
   c:	62 f1 6d 48 75 da    	vpcmpeqw k3,zmm2,zmm2
  12:	62 f1 65 48 75 e3    	vpcmpeqw k4,zmm3,zmm3

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.0
- Reference cycles: 2.67
- UOPS_EXECUTED.THREAD: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 4.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	62 f1 7d 48 75 c8    	vpcmpeqw k1,zmm0,zmm0
   6:	62 f1 75 48 75 d1    	vpcmpeqw k2,zmm1,zmm1
   c:	62 f1 6d 48 75 da    	vpcmpeqw k3,zmm2,zmm2
  12:	62 f1 65 48 75 e3    	vpcmpeqw k4,zmm3,zmm3

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.0
- Reference cycles: 2.41
- UOPS_EXECUTED.THREAD: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.05
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 4.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 7 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f1 7d 48 75 c8    	vpcmpeqw k1,zmm0,zmm0
   6:	62 f1 75 48 75 d1    	vpcmpeqw k2,zmm1,zmm1
   c:	62 f1 6d 48 75 da    	vpcmpeqw k3,zmm2,zmm2
  12:	62 f1 65 48 75 e3    	vpcmpeqw k4,zmm3,zmm3
  18:	62 f1 5d 48 75 ec    	vpcmpeqw k5,zmm4,zmm4
  1e:	62 f1 55 48 75 f5    	vpcmpeqw k6,zmm5,zmm5
  24:	62 f1 4d 48 75 fe    	vpcmpeqw k7,zmm6,zmm6

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 7.04
- Reference cycles: 4.8
- UOPS_EXECUTED.THREAD: 7.04
- RETIRE_SLOTS: 7.0
- UOPS_MITE: 7.0
- UOPS_MS: 0.01
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 7.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.3

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f1 7d 48 75 c8    	vpcmpeqw k1,zmm0,zmm0
   6:	62 f1 75 48 75 d1    	vpcmpeqw k2,zmm1,zmm1
   c:	62 f1 6d 48 75 da    	vpcmpeqw k3,zmm2,zmm2
  12:	62 f1 65 48 75 e3    	vpcmpeqw k4,zmm3,zmm3
  18:	62 f1 5d 48 75 ec    	vpcmpeqw k5,zmm4,zmm4
  1e:	62 f1 55 48 75 f5    	vpcmpeqw k6,zmm5,zmm5
  24:	62 f1 4d 48 75 fe    	vpcmpeqw k7,zmm6,zmm6

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 7.01
- Reference cycles: 4.71
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 7.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	62 f1 7d 48 75 c8    	vpcmpeqw k1,zmm0,zmm0
   6:	62 f1 75 48 75 d1    	vpcmpeqw k2,zmm1,zmm1
   c:	62 f1 6d 48 75 da    	vpcmpeqw k3,zmm2,zmm2
  12:	62 f1 65 48 75 e3    	vpcmpeqw k4,zmm3,zmm3
  18:	62 f1 5d 48 75 ec    	vpcmpeqw k5,zmm4,zmm4
  1e:	62 f1 55 48 75 f5    	vpcmpeqw k6,zmm5,zmm5
  24:	62 f1 4d 48 75 fe    	vpcmpeqw k7,zmm6,zmm6

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6

Show nanoBench command
Results:
- Instructions retired: 7.2
- Core cycles: 7.01
- Reference cycles: 4.24
- UOPS_EXECUTED.THREAD: 7.1
- RETIRE_SLOTS: 7.1
- UOPS_MITE: 0.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 7.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

VPCMPEQW (K, ZMM, ZMM) - Throughput and Uops

With different registers for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 7 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With the same register for for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 7 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10