INVLPG (M8) - Throughput and Uops

With a non-indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	41 0f 01 3e          	invlpg BYTE PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 246.48
- Reference cycles: 246.48
- RS_UOPS_DISPATCHED: 60.0
- UOPS_PORT_0: 10.0
- UOPS_PORT_1: 13.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 3.0
- UOPS_PORT_5: 30.0

With loop_count=10 and unroll_count=1

Code:

   0:	41 0f 01 3e          	invlpg BYTE PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 248.7
- Reference cycles: 248.4
- RS_UOPS_DISPATCHED: 63.6
- UOPS_PORT_0: 11.9
- UOPS_PORT_1: 14.1
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 2.9
- UOPS_PORT_5: 30.7

With loop_count=10 and unroll_count=1

Code:

   0:	41 0f 01 3e          	invlpg BYTE PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 248.7
- Reference cycles: 248.4
- RS_UOPS_DISPATCHED: 63.6
- UOPS_PORT_0: 11.9
- UOPS_PORT_1: 14.1
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 2.9
- UOPS_PORT_5: 30.7

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	43 0f 01 3c 2e       	invlpg BYTE PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 246.64
- Reference cycles: 246.65
- RS_UOPS_DISPATCHED: 60.0
- UOPS_PORT_0: 10.0
- UOPS_PORT_1: 13.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 3.0
- UOPS_PORT_5: 30.0

With loop_count=10 and unroll_count=1

Code:

   0:	43 0f 01 3c 2e       	invlpg BYTE PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 248.7
- Reference cycles: 248.8
- RS_UOPS_DISPATCHED: 63.6
- UOPS_PORT_0: 11.9
- UOPS_PORT_1: 14.1
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 2.9
- UOPS_PORT_5: 30.7

With loop_count=10 and unroll_count=1

Code:

   0:	43 0f 01 3c 2e       	invlpg BYTE PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 248.7
- Reference cycles: 248.8
- RS_UOPS_DISPATCHED: 63.6
- UOPS_PORT_0: 11.9
- UOPS_PORT_1: 14.1
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 2.9
- UOPS_PORT_5: 30.7