ADD_03 (R64, R64)

With unroll_count=500 and no inner loop

Code:

   0:	4d 01 c8             	add    r8,r9

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 1.01
- RS_UOPS_DISPATCHED: 1.0
- UOPS_PORT_0: 0.34
- UOPS_PORT_1: 0.34
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.33

With loop_count=1000 and unroll_count=10

Code:

   0:	4d 01 c8             	add    r8,r9

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.05
- Reference cycles: 1.05
- RS_UOPS_DISPATCHED: 1.2
- UOPS_PORT_0: 0.41
- UOPS_PORT_1: 0.34
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.44

With loop_count=100 and unroll_count=100

Code:

   0:	4d 01 c8             	add    r8,r9

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 1.0
- RS_UOPS_DISPATCHED: 1.02
- UOPS_PORT_0: 0.34
- UOPS_PORT_1: 0.34
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.34

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	4d 01 c8             	add    r8,r9
   3:	4d 01 ca             	add    r10,r9
   6:	4d 01 cb             	add    r11,r9
   9:	4d 01 cc             	add    r12,r9

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 1.34
- Reference cycles: 1.34
- RS_UOPS_DISPATCHED: 4.0
- UOPS_PORT_0: 1.33
- UOPS_PORT_1: 1.34
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.34

With loop_count=1000 and unroll_count=2

Code:

   0:	4d 01 c8             	add    r8,r9
   3:	4d 01 ca             	add    r10,r9
   6:	4d 01 cb             	add    r11,r9
   9:	4d 01 cc             	add    r12,r9

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 1.83
- Reference cycles: 1.83
- RS_UOPS_DISPATCHED: 5.01
- UOPS_PORT_0: 1.61
- UOPS_PORT_1: 1.65
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.75

With loop_count=100 and unroll_count=20

Code:

   0:	4d 01 c8             	add    r8,r9
   3:	4d 01 ca             	add    r10,r9
   6:	4d 01 cb             	add    r11,r9
   9:	4d 01 cc             	add    r12,r9

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 1.46
- Reference cycles: 1.45
- RS_UOPS_DISPATCHED: 4.11
- UOPS_PORT_0: 1.34
- UOPS_PORT_1: 1.37
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.4

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	4d 01 c8             	add    r8,r9
   3:	4d 01 ca             	add    r10,r9
   6:	4d 01 cb             	add    r11,r9
   9:	4d 01 cc             	add    r12,r9
   c:	4d 01 cd             	add    r13,r9
   f:	4d 01 ce             	add    r14,r9
  12:	4c 01 cb             	add    rbx,r9
  15:	4c 01 c9             	add    rcx,r9

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 8.0
- RS_UOPS_DISPATCHED: 8.0
- UOPS_PORT_0: 2.64
- UOPS_PORT_1: 2.68
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.68

With loop_count=1000 and unroll_count=1

Code:

   0:	4d 01 c8             	add    r8,r9
   3:	4d 01 ca             	add    r10,r9
   6:	4d 01 cb             	add    r11,r9
   9:	4d 01 cc             	add    r12,r9
   c:	4d 01 cd             	add    r13,r9
   f:	4d 01 ce             	add    r14,r9
  12:	4c 01 cb             	add    rbx,r9
  15:	4c 01 c9             	add    rcx,r9

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 9.01
- Reference cycles: 9.01
- RS_UOPS_DISPATCHED: 10.0
- UOPS_PORT_0: 3.0
- UOPS_PORT_1: 3.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0

With loop_count=100 and unroll_count=10

Code:

   0:	4d 01 c8             	add    r8,r9
   3:	4d 01 ca             	add    r10,r9
   6:	4d 01 cb             	add    r11,r9
   9:	4d 01 cc             	add    r12,r9
   c:	4d 01 cd             	add    r13,r9
   f:	4d 01 ce             	add    r14,r9
  12:	4c 01 cb             	add    rbx,r9
  15:	4c 01 c9             	add    rcx,r9

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.12
- Reference cycles: 8.11
- RS_UOPS_DISPATCHED: 8.2
- UOPS_PORT_0: 2.7
- UOPS_PORT_1: 2.7
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.8

With 12 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	4d 01 c8             	add    r8,r9
   3:	4d 01 ca             	add    r10,r9
   6:	4d 01 cb             	add    r11,r9
   9:	4d 01 cc             	add    r12,r9
   c:	4d 01 cd             	add    r13,r9
   f:	4d 01 ce             	add    r14,r9
  12:	4c 01 cb             	add    rbx,r9
  15:	4c 01 c9             	add    rcx,r9
  18:	4c 01 ca             	add    rdx,r9
  1b:	4c 01 cf             	add    rdi,r9
  1e:	4c 01 ce             	add    rsi,r9
  21:	4c 01 cd             	add    rbp,r9

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 12.0
- Reference cycles: 11.97
- RS_UOPS_DISPATCHED: 12.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 6.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 6.0

With loop_count=1000 and unroll_count=1

Code:

   0:	4d 01 c8             	add    r8,r9
   3:	4d 01 ca             	add    r10,r9
   6:	4d 01 cb             	add    r11,r9
   9:	4d 01 cc             	add    r12,r9
   c:	4d 01 cd             	add    r13,r9
   f:	4d 01 ce             	add    r14,r9
  12:	4c 01 cb             	add    rbx,r9
  15:	4c 01 c9             	add    rcx,r9
  18:	4c 01 ca             	add    rdx,r9
  1b:	4c 01 cf             	add    rdi,r9
  1e:	4c 01 ce             	add    rsi,r9
  21:	4c 01 cd             	add    rbp,r9

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 13.01
- Reference cycles: 13.01
- RS_UOPS_DISPATCHED: 14.0
- UOPS_PORT_0: 4.01
- UOPS_PORT_1: 5.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 5.0

With loop_count=100 and unroll_count=10

Code:

   0:	4d 01 c8             	add    r8,r9
   3:	4d 01 ca             	add    r10,r9
   6:	4d 01 cb             	add    r11,r9
   9:	4d 01 cc             	add    r12,r9
   c:	4d 01 cd             	add    r13,r9
   f:	4d 01 ce             	add    r14,r9
  12:	4c 01 cb             	add    rbx,r9
  15:	4c 01 c9             	add    rcx,r9
  18:	4c 01 ca             	add    rdx,r9
  1b:	4c 01 cf             	add    rdi,r9
  1e:	4c 01 ce             	add    rsi,r9
  21:	4c 01 cd             	add    rbp,r9

Show nanoBench command
Results:
- Instructions retired: 12.2
- Core cycles: 12.11
- Reference cycles: 12.11
- RS_UOPS_DISPATCHED: 12.2
- UOPS_PORT_0: 0.41
- UOPS_PORT_1: 5.95
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 5.85

With the same register for for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	4d 01 c0             	add    r8,r8

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 1.0
- RS_UOPS_DISPATCHED: 1.0
- UOPS_PORT_0: 0.34
- UOPS_PORT_1: 0.34
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.33

With loop_count=1000 and unroll_count=10

Code:

   0:	4d 01 c0             	add    r8,r8

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.05
- Reference cycles: 1.05
- RS_UOPS_DISPATCHED: 1.2
- UOPS_PORT_0: 0.41
- UOPS_PORT_1: 0.34
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.44

With loop_count=100 and unroll_count=100

Code:

   0:	4d 01 c0             	add    r8,r8

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 1.0
- RS_UOPS_DISPATCHED: 1.02
- UOPS_PORT_0: 0.34
- UOPS_PORT_1: 0.34
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.34

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	4d 01 c0             	add    r8,r8
   3:	4d 01 c9             	add    r9,r9
   6:	4d 01 d2             	add    r10,r10
   9:	4d 01 db             	add    r11,r11

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 1.34
- Reference cycles: 1.33
- RS_UOPS_DISPATCHED: 4.0
- UOPS_PORT_0: 1.33
- UOPS_PORT_1: 1.34
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.33

With loop_count=1000 and unroll_count=2

Code:

   0:	4d 01 c0             	add    r8,r8
   3:	4d 01 c9             	add    r9,r9
   6:	4d 01 d2             	add    r10,r10
   9:	4d 01 db             	add    r11,r11

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 1.83
- Reference cycles: 1.83
- RS_UOPS_DISPATCHED: 5.0
- UOPS_PORT_0: 1.6
- UOPS_PORT_1: 1.65
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.75

With loop_count=100 and unroll_count=20

Code:

   0:	4d 01 c0             	add    r8,r8
   3:	4d 01 c9             	add    r9,r9
   6:	4d 01 d2             	add    r10,r10
   9:	4d 01 db             	add    r11,r11

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 1.46
- Reference cycles: 1.46
- RS_UOPS_DISPATCHED: 4.11
- UOPS_PORT_0: 1.34
- UOPS_PORT_1: 1.37
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.4

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	4d 01 c0             	add    r8,r8
   3:	4d 01 c9             	add    r9,r9
   6:	4d 01 d2             	add    r10,r10
   9:	4d 01 db             	add    r11,r11
   c:	4d 01 e4             	add    r12,r12
   f:	4d 01 ed             	add    r13,r13
  12:	4d 01 f6             	add    r14,r14
  15:	48 01 db             	add    rbx,rbx

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 2.68
- Reference cycles: 2.69
- RS_UOPS_DISPATCHED: 8.0
- UOPS_PORT_0: 2.69
- UOPS_PORT_1: 2.66
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.65

With loop_count=1000 and unroll_count=1

Code:

   0:	4d 01 c0             	add    r8,r8
   3:	4d 01 c9             	add    r9,r9
   6:	4d 01 d2             	add    r10,r10
   9:	4d 01 db             	add    r11,r11
   c:	4d 01 e4             	add    r12,r12
   f:	4d 01 ed             	add    r13,r13
  12:	4d 01 f6             	add    r14,r14
  15:	48 01 db             	add    rbx,rbx

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 3.35
- Reference cycles: 3.35
- RS_UOPS_DISPATCHED: 10.02
- UOPS_PORT_0: 3.34
- UOPS_PORT_1: 3.34
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 3.34

With loop_count=100 and unroll_count=10

Code:

   0:	4d 01 c0             	add    r8,r8
   3:	4d 01 c9             	add    r9,r9
   6:	4d 01 d2             	add    r10,r10
   9:	4d 01 db             	add    r11,r11
   c:	4d 01 e4             	add    r12,r12
   f:	4d 01 ed             	add    r13,r13
  12:	4d 01 f6             	add    r14,r14
  15:	48 01 db             	add    rbx,rbx

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 2.76
- Reference cycles: 2.75
- RS_UOPS_DISPATCHED: 8.22
- UOPS_PORT_0: 2.73
- UOPS_PORT_1: 2.74
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.74

With 13 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	4d 01 c0             	add    r8,r8
   3:	4d 01 c9             	add    r9,r9
   6:	4d 01 d2             	add    r10,r10
   9:	4d 01 db             	add    r11,r11
   c:	4d 01 e4             	add    r12,r12
   f:	4d 01 ed             	add    r13,r13
  12:	4d 01 f6             	add    r14,r14
  15:	48 01 db             	add    rbx,rbx
  18:	48 01 c9             	add    rcx,rcx
  1b:	48 01 d2             	add    rdx,rdx
  1e:	48 01 ff             	add    rdi,rdi
  21:	48 01 f6             	add    rsi,rsi
  24:	48 01 ed             	add    rbp,rbp

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 4.44
- Reference cycles: 4.44
- RS_UOPS_DISPATCHED: 13.0
- UOPS_PORT_0: 4.38
- UOPS_PORT_1: 4.32
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.3

With loop_count=1000 and unroll_count=1

Code:

   0:	4d 01 c0             	add    r8,r8
   3:	4d 01 c9             	add    r9,r9
   6:	4d 01 d2             	add    r10,r10
   9:	4d 01 db             	add    r11,r11
   c:	4d 01 e4             	add    r12,r12
   f:	4d 01 ed             	add    r13,r13
  12:	4d 01 f6             	add    r14,r14
  15:	48 01 db             	add    rbx,rbx
  18:	48 01 c9             	add    rcx,rcx
  1b:	48 01 d2             	add    rdx,rdx
  1e:	48 01 ff             	add    rdi,rdi
  21:	48 01 f6             	add    rsi,rsi
  24:	48 01 ed             	add    rbp,rbp

Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 5.02
- Reference cycles: 5.02
- RS_UOPS_DISPATCHED: 15.02
- UOPS_PORT_0: 5.01
- UOPS_PORT_1: 5.01
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 5.01

With loop_count=100 and unroll_count=10

Code:

   0:	4d 01 c0             	add    r8,r8
   3:	4d 01 c9             	add    r9,r9
   6:	4d 01 d2             	add    r10,r10
   9:	4d 01 db             	add    r11,r11
   c:	4d 01 e4             	add    r12,r12
   f:	4d 01 ed             	add    r13,r13
  12:	4d 01 f6             	add    r14,r14
  15:	48 01 db             	add    rbx,rbx
  18:	48 01 c9             	add    rcx,rcx
  1b:	48 01 d2             	add    rdx,rdx
  1e:	48 01 ff             	add    rdi,rdi
  21:	48 01 f6             	add    rsi,rsi
  24:	48 01 ed             	add    rbp,rbp

Show nanoBench command
Results:
- Instructions retired: 13.2
- Core cycles: 4.42
- Reference cycles: 4.42
- RS_UOPS_DISPATCHED: 13.22
- UOPS_PORT_0: 4.41
- UOPS_PORT_1: 4.41
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.4

ADD_03 (R64, R64) - Throughput and Uops

With different registers for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 12 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With the same register for for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 13 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10