ADC (AL, 0) - Throughput and Uops
With unroll_count=500 and no inner loop
Code:
0: 14 00 adc al,0x0
Show nanoBench command
Results:
Instructions retired: 1.0
Core cycles: 2.0
Reference cycles: 1.99
RS_UOPS_DISPATCHED: 2.0
UOPS_PORT_0: 0.67
UOPS_PORT_1: 0.66
UOPS_PORT_2: 0.0
UOPS_PORT_3: 0.0
UOPS_PORT_4: 0.0
UOPS_PORT_5: 0.67
With loop_count=1000 and unroll_count=10
Code:
0: 14 00 adc al,0x0
Show nanoBench command
Results:
Instructions retired: 1.2
Core cycles: 2.8
Reference cycles: 2.8
RS_UOPS_DISPATCHED: 2.2
UOPS_PORT_0: 0.6
UOPS_PORT_1: 0.6
UOPS_PORT_2: 0.0
UOPS_PORT_3: 0.0
UOPS_PORT_4: 0.0
UOPS_PORT_5: 1.0
With loop_count=100 and unroll_count=100
Code:
0: 14 00 adc al,0x0
Show nanoBench command
Results:
Instructions retired: 1.02
Core cycles: 2.08
Reference cycles: 2.08
RS_UOPS_DISPATCHED: 2.02
UOPS_PORT_0: 0.66
UOPS_PORT_1: 0.67
UOPS_PORT_2: 0.0
UOPS_PORT_3: 0.0
UOPS_PORT_4: 0.0
UOPS_PORT_5: 0.69
With additional dependency-breaking instructions
With unroll_count=500 and no inner loop
Code:
0: 48 31 c0 xor rax,rax 3: 14 00 adc al,0x0
Show nanoBench command
Results:
Instructions retired: 2.0
Core cycles: 1.0
Reference cycles: 1.0
RS_UOPS_DISPATCHED: 3.0
UOPS_PORT_0: 1.0
UOPS_PORT_1: 1.0
UOPS_PORT_2: 0.0
UOPS_PORT_3: 0.0
UOPS_PORT_4: 0.0
UOPS_PORT_5: 1.0
With loop_count=1000 and unroll_count=10
Code:
0: 48 31 c0 xor rax,rax 3: 14 00 adc al,0x0
Show nanoBench command
Results:
Instructions retired: 2.2
Core cycles: 1.1
Reference cycles: 1.1
RS_UOPS_DISPATCHED: 3.2
UOPS_PORT_0: 1.05
UOPS_PORT_1: 1.05
UOPS_PORT_2: 0.0
UOPS_PORT_3: 0.0
UOPS_PORT_4: 0.0
UOPS_PORT_5: 1.1
With loop_count=100 and unroll_count=100
Code:
0: 48 31 c0 xor rax,rax 3: 14 00 adc al,0x0
Show nanoBench command
Results:
Instructions retired: 2.02
Core cycles: 1.01
Reference cycles: 1.01
RS_UOPS_DISPATCHED: 3.02
UOPS_PORT_0: 1.01
UOPS_PORT_1: 1.01
UOPS_PORT_2: 0.0
UOPS_PORT_3: 0.0
UOPS_PORT_4: 0.0
UOPS_PORT_5: 1.01