VPTESTMB (K, ZMM, M512) - Throughput and Uops

With unroll_count=500 and no inner loop

• Code:

     0:	62 d2 7d 48 26 0e    	vptestmb k1,zmm0,ZMMWORD PTR [r14]
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS ZMM0, ZMM0, ZMM0

• Show nanoBench command
• Results:
  • Instructions retired: 1.0
  • Core cycles: 1.0
  • Reference cycles: 0.77
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.5
  • UOPS_PORT_3: 0.5
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 1.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

• Code:

     0:	62 d2 7d 48 26 0e    	vptestmb k1,zmm0,ZMMWORD PTR [r14]
     6:	90                   	nop
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS ZMM0, ZMM0, ZMM0

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.0
  • Reference cycles: 0.71
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 3.0
  • UOPS_MITE: 3.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.5
  • UOPS_PORT_3: 0.5
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 1.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

• Code:

     0:	62 d2 7d 48 26 0e    	vptestmb k1,zmm0,ZMMWORD PTR [r14]
     6:	90                   	nop
     7:	90                   	nop
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS ZMM0, ZMM0, ZMM0

• Show nanoBench command
• Results:
  • Instructions retired: 3.0
  • Core cycles: 1.0
  • Reference cycles: 0.64
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 4.0
  • UOPS_MITE: 4.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.5
  • UOPS_PORT_3: 0.5
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 1.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

• Code:

     0:	62 d2 7d 48 26 0e    	vptestmb k1,zmm0,ZMMWORD PTR [r14]
     6:	90                   	nop
     7:	90                   	nop
     8:	90                   	nop
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS ZMM0, ZMM0, ZMM0

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 1.25
  • Reference cycles: 0.92
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 5.0
  • UOPS_MITE: 5.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.5
  • UOPS_PORT_3: 0.5
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 1.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 4 NOPs

• Code:

     0:	62 d2 7d 48 26 0e    	vptestmb k1,zmm0,ZMMWORD PTR [r14]
     6:	90                   	nop
     7:	90                   	nop
     8:	90                   	nop
     9:	90                   	nop
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS ZMM0, ZMM0, ZMM0

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 2.0
  • Reference cycles: 1.38
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 6.0
  • UOPS_MITE: 6.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.5
  • UOPS_PORT_3: 0.5
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 1.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

• Code:

     0:	62 d2 7d 48 26 0e    	vptestmb k1,zmm0,ZMMWORD PTR [r14]
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS ZMM0, ZMM0, ZMM0

• Show nanoBench command
• Results:
  • Instructions retired: 1.2
  • Core cycles: 1.0
  • Reference cycles: 0.7
  • UOPS_EXECUTED.THREAD: 2.1
  • RETIRE_SLOTS: 2.1
  • UOPS_MITE: 0.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.5
  • UOPS_PORT_3: 0.5
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 1.0
  • UOPS_PORT_6: 0.1
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

• Code:

     0:	62 d2 7d 48 26 0e    	vptestmb k1,zmm0,ZMMWORD PTR [r14]
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS ZMM0, ZMM0, ZMM0

• Show nanoBench command
• Results:
  • Instructions retired: 1.02
  • Core cycles: 1.0
  • Reference cycles: 0.7
  • UOPS_EXECUTED.THREAD: 2.01
  • RETIRE_SLOTS: 2.01
  • UOPS_MITE: 0.02
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.5
  • UOPS_PORT_3: 0.5
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 1.0
  • UOPS_PORT_6: 0.01
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With unroll_count=200 and no inner loop

• Code:

     0:	62 d2 7d 48 26 0e    	vptestmb k1,zmm0,ZMMWORD PTR [r14]
     6:	62 d2 7d 48 26 56 01 	vptestmb k2,zmm0,ZMMWORD PTR [r14+0x40]
     d:	62 d2 7d 48 26 5e 02 	vptestmb k3,zmm0,ZMMWORD PTR [r14+0x80]
    14:	62 d2 7d 48 26 66 03 	vptestmb k4,zmm0,ZMMWORD PTR [r14+0xc0]
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS ZMM0, ZMM0, ZMM0

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 4.0
  • Reference cycles: 2.84
  • UOPS_EXECUTED.THREAD: 8.0
  • RETIRE_SLOTS: 8.0
  • UOPS_MITE: 8.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 2.0
  • UOPS_PORT_3: 2.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 4.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

• Code:

     0:	62 d2 7d 48 26 0e    	vptestmb k1,zmm0,ZMMWORD PTR [r14]
     6:	62 d2 7d 48 26 56 01 	vptestmb k2,zmm0,ZMMWORD PTR [r14+0x40]
     d:	62 d2 7d 48 26 5e 02 	vptestmb k3,zmm0,ZMMWORD PTR [r14+0x80]
    14:	62 d2 7d 48 26 66 03 	vptestmb k4,zmm0,ZMMWORD PTR [r14+0xc0]
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS ZMM0, ZMM0, ZMM0

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 4.01
  • Reference cycles: 2.76
  • UOPS_EXECUTED.THREAD: 8.5
  • RETIRE_SLOTS: 8.5
  • UOPS_MITE: 0.01
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 2.0
  • UOPS_PORT_3: 2.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 4.0
  • UOPS_PORT_6: 0.5
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

• Code:

     0:	62 d2 7d 48 26 0e    	vptestmb k1,zmm0,ZMMWORD PTR [r14]
     6:	62 d2 7d 48 26 56 01 	vptestmb k2,zmm0,ZMMWORD PTR [r14+0x40]
     d:	62 d2 7d 48 26 5e 02 	vptestmb k3,zmm0,ZMMWORD PTR [r14+0x80]
    14:	62 d2 7d 48 26 66 03 	vptestmb k4,zmm0,ZMMWORD PTR [r14+0xc0]
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS ZMM0, ZMM0, ZMM0

• Show nanoBench command
• Results:
  • Instructions retired: 4.1
  • Core cycles: 4.01
  • Reference cycles: 2.8
  • UOPS_EXECUTED.THREAD: 8.05
  • RETIRE_SLOTS: 8.05
  • UOPS_MITE: 0.09
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 2.0
  • UOPS_PORT_3: 2.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 4.0
  • UOPS_PORT_6: 0.05
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.04

With unroll_count=100 and no inner loop

• Code:

     0:	62 d2 7d 48 26 0e    	vptestmb k1,zmm0,ZMMWORD PTR [r14]
     6:	62 d2 7d 48 26 56 01 	vptestmb k2,zmm0,ZMMWORD PTR [r14+0x40]
     d:	62 d2 7d 48 26 5e 02 	vptestmb k3,zmm0,ZMMWORD PTR [r14+0x80]
    14:	62 d2 7d 48 26 66 03 	vptestmb k4,zmm0,ZMMWORD PTR [r14+0xc0]
    1b:	62 d2 7d 48 26 6e 04 	vptestmb k5,zmm0,ZMMWORD PTR [r14+0x100]
    22:	62 d2 7d 48 26 76 05 	vptestmb k6,zmm0,ZMMWORD PTR [r14+0x140]
    29:	62 d2 7d 48 26 7e 06 	vptestmb k7,zmm0,ZMMWORD PTR [r14+0x180]
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS ZMM0, ZMM0, ZMM0

• Show nanoBench command
• Results:
  • Instructions retired: 7.0
  • Core cycles: 7.0
  • Reference cycles: 4.91
  • UOPS_EXECUTED.THREAD: 14.0
  • RETIRE_SLOTS: 14.0
  • UOPS_MITE: 14.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 3.5
  • UOPS_PORT_3: 3.5
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 7.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 7.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	62 d2 7d 48 26 0e    	vptestmb k1,zmm0,ZMMWORD PTR [r14]
     6:	62 d2 7d 48 26 56 01 	vptestmb k2,zmm0,ZMMWORD PTR [r14+0x40]
     d:	62 d2 7d 48 26 5e 02 	vptestmb k3,zmm0,ZMMWORD PTR [r14+0x80]
    14:	62 d2 7d 48 26 66 03 	vptestmb k4,zmm0,ZMMWORD PTR [r14+0xc0]
    1b:	62 d2 7d 48 26 6e 04 	vptestmb k5,zmm0,ZMMWORD PTR [r14+0x100]
    22:	62 d2 7d 48 26 76 05 	vptestmb k6,zmm0,ZMMWORD PTR [r14+0x140]
    29:	62 d2 7d 48 26 7e 06 	vptestmb k7,zmm0,ZMMWORD PTR [r14+0x180]
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS ZMM0, ZMM0, ZMM0

• Show nanoBench command
• Results:
  • Instructions retired: 9.0
  • Core cycles: 7.02
  • Reference cycles: 4.85
  • UOPS_EXECUTED.THREAD: 15.01
  • RETIRE_SLOTS: 15.0
  • UOPS_MITE: 0.01
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 3.5
  • UOPS_PORT_3: 3.5
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 7.0
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

• Code:

     0:	62 d2 7d 48 26 0e    	vptestmb k1,zmm0,ZMMWORD PTR [r14]
     6:	62 d2 7d 48 26 56 01 	vptestmb k2,zmm0,ZMMWORD PTR [r14+0x40]
     d:	62 d2 7d 48 26 5e 02 	vptestmb k3,zmm0,ZMMWORD PTR [r14+0x80]
    14:	62 d2 7d 48 26 66 03 	vptestmb k4,zmm0,ZMMWORD PTR [r14+0xc0]
    1b:	62 d2 7d 48 26 6e 04 	vptestmb k5,zmm0,ZMMWORD PTR [r14+0x100]
    22:	62 d2 7d 48 26 76 05 	vptestmb k6,zmm0,ZMMWORD PTR [r14+0x140]
    29:	62 d2 7d 48 26 7e 06 	vptestmb k7,zmm0,ZMMWORD PTR [r14+0x180]
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS ZMM0, ZMM0, ZMM0

• Show nanoBench command
• Results:
  • Instructions retired: 7.2
  • Core cycles: 7.01
  • Reference cycles: 4.88
  • UOPS_EXECUTED.THREAD: 14.11
  • RETIRE_SLOTS: 14.11
  • UOPS_MITE: 0.14
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 3.5
  • UOPS_PORT_3: 3.5
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 7.0
  • UOPS_PORT_6: 0.1
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.07

With unroll_count=500 and no inner loop

• Code:

     0:	62 92 7d 48 26 0c 2e 	vptestmb k1,zmm0,ZMMWORD PTR [r14+r13*1]
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS ZMM0, ZMM0, ZMM0;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 1.0
  • Core cycles: 1.0
  • Reference cycles: 0.67
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.5
  • UOPS_PORT_3: 0.5
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 1.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

• Code:

     0:	62 92 7d 48 26 0c 2e 	vptestmb k1,zmm0,ZMMWORD PTR [r14+r13*1]
     7:	90                   	nop
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS ZMM0, ZMM0, ZMM0;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.0
  • Reference cycles: 0.71
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 3.0
  • UOPS_MITE: 3.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.5
  • UOPS_PORT_3: 0.5
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 1.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

• Code:

     0:	62 92 7d 48 26 0c 2e 	vptestmb k1,zmm0,ZMMWORD PTR [r14+r13*1]
     7:	90                   	nop
     8:	90                   	nop
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS ZMM0, ZMM0, ZMM0;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 3.0
  • Core cycles: 1.0
  • Reference cycles: 0.64
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 4.0
  • UOPS_MITE: 4.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.5
  • UOPS_PORT_3: 0.5
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 1.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

• Code:

     0:	62 92 7d 48 26 0c 2e 	vptestmb k1,zmm0,ZMMWORD PTR [r14+r13*1]
     7:	90                   	nop
     8:	90                   	nop
     9:	90                   	nop
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS ZMM0, ZMM0, ZMM0;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 1.25
  • Reference cycles: 0.92
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 5.0
  • UOPS_MITE: 5.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.5
  • UOPS_PORT_3: 0.5
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 1.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 4 NOPs

• Code:

     0:	62 92 7d 48 26 0c 2e 	vptestmb k1,zmm0,ZMMWORD PTR [r14+r13*1]
     7:	90                   	nop
     8:	90                   	nop
     9:	90                   	nop
     a:	90                   	nop
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS ZMM0, ZMM0, ZMM0;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 2.0
  • Reference cycles: 1.44
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 6.0
  • UOPS_MITE: 6.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.5
  • UOPS_PORT_3: 0.5
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 1.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

• Code:

     0:	62 92 7d 48 26 0c 2e 	vptestmb k1,zmm0,ZMMWORD PTR [r14+r13*1]
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS ZMM0, ZMM0, ZMM0;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 1.2
  • Core cycles: 1.0
  • Reference cycles: 0.69
  • UOPS_EXECUTED.THREAD: 2.1
  • RETIRE_SLOTS: 2.1
  • UOPS_MITE: 0.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.5
  • UOPS_PORT_3: 0.5
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 1.0
  • UOPS_PORT_6: 0.1
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

• Code:

     0:	62 92 7d 48 26 0c 2e 	vptestmb k1,zmm0,ZMMWORD PTR [r14+r13*1]
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS ZMM0, ZMM0, ZMM0;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 1.02
  • Core cycles: 1.0
  • Reference cycles: 0.69
  • UOPS_EXECUTED.THREAD: 2.01
  • RETIRE_SLOTS: 2.01
  • UOPS_MITE: 0.02
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.5
  • UOPS_PORT_3: 0.5
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 1.0
  • UOPS_PORT_6: 0.01
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With unroll_count=200 and no inner loop

• Code:

     0:	62 92 7d 48 26 0c 2e 	vptestmb k1,zmm0,ZMMWORD PTR [r14+r13*1]
     7:	62 92 7d 48 26 54 2e 	vptestmb k2,zmm0,ZMMWORD PTR [r14+r13*1+0x40]
     e:	01 
     f:	62 92 7d 48 26 5c 2e 	vptestmb k3,zmm0,ZMMWORD PTR [r14+r13*1+0x80]
    16:	02 
    17:	62 92 7d 48 26 64 2e 	vptestmb k4,zmm0,ZMMWORD PTR [r14+r13*1+0xc0]
    1e:	03 
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS ZMM0, ZMM0, ZMM0;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 4.0
  • Reference cycles: 2.91
  • UOPS_EXECUTED.THREAD: 8.0
  • RETIRE_SLOTS: 8.0
  • UOPS_MITE: 8.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 2.0
  • UOPS_PORT_3: 2.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 4.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

• Code:

     0:	62 92 7d 48 26 0c 2e 	vptestmb k1,zmm0,ZMMWORD PTR [r14+r13*1]
     7:	62 92 7d 48 26 54 2e 	vptestmb k2,zmm0,ZMMWORD PTR [r14+r13*1+0x40]
     e:	01 
     f:	62 92 7d 48 26 5c 2e 	vptestmb k3,zmm0,ZMMWORD PTR [r14+r13*1+0x80]
    16:	02 
    17:	62 92 7d 48 26 64 2e 	vptestmb k4,zmm0,ZMMWORD PTR [r14+r13*1+0xc0]
    1e:	03 
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS ZMM0, ZMM0, ZMM0;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 4.01
  • Reference cycles: 2.78
  • UOPS_EXECUTED.THREAD: 8.5
  • RETIRE_SLOTS: 8.5
  • UOPS_MITE: 0.01
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 2.0
  • UOPS_PORT_3: 2.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 4.0
  • UOPS_PORT_6: 0.5
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

• Code:

     0:	62 92 7d 48 26 0c 2e 	vptestmb k1,zmm0,ZMMWORD PTR [r14+r13*1]
     7:	62 92 7d 48 26 54 2e 	vptestmb k2,zmm0,ZMMWORD PTR [r14+r13*1+0x40]
     e:	01 
     f:	62 92 7d 48 26 5c 2e 	vptestmb k3,zmm0,ZMMWORD PTR [r14+r13*1+0x80]
    16:	02 
    17:	62 92 7d 48 26 64 2e 	vptestmb k4,zmm0,ZMMWORD PTR [r14+r13*1+0xc0]
    1e:	03 
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS ZMM0, ZMM0, ZMM0;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 4.1
  • Core cycles: 4.01
  • Reference cycles: 2.8
  • UOPS_EXECUTED.THREAD: 8.05
  • RETIRE_SLOTS: 8.05
  • UOPS_MITE: 0.08
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 2.0
  • UOPS_PORT_3: 2.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 4.0
  • UOPS_PORT_6: 0.05
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.04

With unroll_count=100 and no inner loop

• Code:

     0:	62 92 7d 48 26 0c 2e 	vptestmb k1,zmm0,ZMMWORD PTR [r14+r13*1]
     7:	62 92 7d 48 26 54 2e 	vptestmb k2,zmm0,ZMMWORD PTR [r14+r13*1+0x40]
     e:	01 
     f:	62 92 7d 48 26 5c 2e 	vptestmb k3,zmm0,ZMMWORD PTR [r14+r13*1+0x80]
    16:	02 
    17:	62 92 7d 48 26 64 2e 	vptestmb k4,zmm0,ZMMWORD PTR [r14+r13*1+0xc0]
    1e:	03 
    1f:	62 92 7d 48 26 6c 2e 	vptestmb k5,zmm0,ZMMWORD PTR [r14+r13*1+0x100]
    26:	04 
    27:	62 92 7d 48 26 74 2e 	vptestmb k6,zmm0,ZMMWORD PTR [r14+r13*1+0x140]
    2e:	05 
    2f:	62 92 7d 48 26 7c 2e 	vptestmb k7,zmm0,ZMMWORD PTR [r14+r13*1+0x180]
    36:	06 
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS ZMM0, ZMM0, ZMM0;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 7.0
  • Core cycles: 7.0
  • Reference cycles: 4.6
  • UOPS_EXECUTED.THREAD: 14.0
  • RETIRE_SLOTS: 14.0
  • UOPS_MITE: 14.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 3.5
  • UOPS_PORT_3: 3.5
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 7.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 7.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	62 92 7d 48 26 0c 2e 	vptestmb k1,zmm0,ZMMWORD PTR [r14+r13*1]
     7:	62 92 7d 48 26 54 2e 	vptestmb k2,zmm0,ZMMWORD PTR [r14+r13*1+0x40]
     e:	01 
     f:	62 92 7d 48 26 5c 2e 	vptestmb k3,zmm0,ZMMWORD PTR [r14+r13*1+0x80]
    16:	02 
    17:	62 92 7d 48 26 64 2e 	vptestmb k4,zmm0,ZMMWORD PTR [r14+r13*1+0xc0]
    1e:	03 
    1f:	62 92 7d 48 26 6c 2e 	vptestmb k5,zmm0,ZMMWORD PTR [r14+r13*1+0x100]
    26:	04 
    27:	62 92 7d 48 26 74 2e 	vptestmb k6,zmm0,ZMMWORD PTR [r14+r13*1+0x140]
    2e:	05 
    2f:	62 92 7d 48 26 7c 2e 	vptestmb k7,zmm0,ZMMWORD PTR [r14+r13*1+0x180]
    36:	06 
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS ZMM0, ZMM0, ZMM0;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 9.0
  • Core cycles: 7.01
  • Reference cycles: 4.85
  • UOPS_EXECUTED.THREAD: 15.01
  • RETIRE_SLOTS: 15.0
  • UOPS_MITE: 0.02
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 3.5
  • UOPS_PORT_3: 3.5
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 7.0
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

• Code:

     0:	62 92 7d 48 26 0c 2e 	vptestmb k1,zmm0,ZMMWORD PTR [r14+r13*1]
     7:	62 92 7d 48 26 54 2e 	vptestmb k2,zmm0,ZMMWORD PTR [r14+r13*1+0x40]
     e:	01 
     f:	62 92 7d 48 26 5c 2e 	vptestmb k3,zmm0,ZMMWORD PTR [r14+r13*1+0x80]
    16:	02 
    17:	62 92 7d 48 26 64 2e 	vptestmb k4,zmm0,ZMMWORD PTR [r14+r13*1+0xc0]
    1e:	03 
    1f:	62 92 7d 48 26 6c 2e 	vptestmb k5,zmm0,ZMMWORD PTR [r14+r13*1+0x100]
    26:	04 
    27:	62 92 7d 48 26 74 2e 	vptestmb k6,zmm0,ZMMWORD PTR [r14+r13*1+0x140]
    2e:	05 
    2f:	62 92 7d 48 26 7c 2e 	vptestmb k7,zmm0,ZMMWORD PTR [r14+r13*1+0x180]
    36:	06 
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS ZMM0, ZMM0, ZMM0;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 7.2
  • Core cycles: 7.01
  • Reference cycles: 4.86
  • UOPS_EXECUTED.THREAD: 14.11
  • RETIRE_SLOTS: 14.1
  • UOPS_MITE: 0.14
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 3.5
  • UOPS_PORT_3: 3.5
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 7.0
  • UOPS_PORT_6: 0.1
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.07