VPERMD (ZMM, ZMM, M512)

With unroll_count=500 and no inner loop

Code:

   0:	62 d2 75 48 36 06    	vpermd zmm0,zmm1,ZMMWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.83
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	62 d2 75 48 36 06    	vpermd zmm0,zmm1,ZMMWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 0.71
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 d2 75 48 36 06    	vpermd zmm0,zmm1,ZMMWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 0.72
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 d2 75 48 36 06    	vpermd zmm0,zmm1,ZMMWORD PTR [r14]
   6:	62 d2 75 48 36 56 01 	vpermd zmm2,zmm1,ZMMWORD PTR [r14+0x40]
   d:	62 d2 75 48 36 5e 02 	vpermd zmm3,zmm1,ZMMWORD PTR [r14+0x80]
  14:	62 d2 75 48 36 66 03 	vpermd zmm4,zmm1,ZMMWORD PTR [r14+0xc0]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 2.76
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	62 d2 75 48 36 06    	vpermd zmm0,zmm1,ZMMWORD PTR [r14]
   6:	62 d2 75 48 36 56 01 	vpermd zmm2,zmm1,ZMMWORD PTR [r14+0x40]
   d:	62 d2 75 48 36 5e 02 	vpermd zmm3,zmm1,ZMMWORD PTR [r14+0x80]
  14:	62 d2 75 48 36 66 03 	vpermd zmm4,zmm1,ZMMWORD PTR [r14+0xc0]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.01
- Reference cycles: 2.87
- UOPS_EXECUTED.THREAD: 8.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	62 d2 75 48 36 06    	vpermd zmm0,zmm1,ZMMWORD PTR [r14]
   6:	62 d2 75 48 36 56 01 	vpermd zmm2,zmm1,ZMMWORD PTR [r14+0x40]
   d:	62 d2 75 48 36 5e 02 	vpermd zmm3,zmm1,ZMMWORD PTR [r14+0x80]
  14:	62 d2 75 48 36 66 03 	vpermd zmm4,zmm1,ZMMWORD PTR [r14+0xc0]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.01
- Reference cycles: 2.85
- UOPS_EXECUTED.THREAD: 8.05
- RETIRE_SLOTS: 4.06
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 d2 75 48 36 06    	vpermd zmm0,zmm1,ZMMWORD PTR [r14]
   6:	62 d2 75 48 36 56 01 	vpermd zmm2,zmm1,ZMMWORD PTR [r14+0x40]
   d:	62 d2 75 48 36 5e 02 	vpermd zmm3,zmm1,ZMMWORD PTR [r14+0x80]
  14:	62 d2 75 48 36 66 03 	vpermd zmm4,zmm1,ZMMWORD PTR [r14+0xc0]
  1b:	62 d2 75 48 36 6e 04 	vpermd zmm5,zmm1,ZMMWORD PTR [r14+0x100]
  22:	62 d2 75 48 36 76 05 	vpermd zmm6,zmm1,ZMMWORD PTR [r14+0x140]
  29:	62 d2 75 48 36 7e 06 	vpermd zmm7,zmm1,ZMMWORD PTR [r14+0x180]
  30:	62 52 75 48 36 46 07 	vpermd zmm8,zmm1,ZMMWORD PTR [r14+0x1c0]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 5.52
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 d2 75 48 36 06    	vpermd zmm0,zmm1,ZMMWORD PTR [r14]
   6:	62 d2 75 48 36 56 01 	vpermd zmm2,zmm1,ZMMWORD PTR [r14+0x40]
   d:	62 d2 75 48 36 5e 02 	vpermd zmm3,zmm1,ZMMWORD PTR [r14+0x80]
  14:	62 d2 75 48 36 66 03 	vpermd zmm4,zmm1,ZMMWORD PTR [r14+0xc0]
  1b:	62 d2 75 48 36 6e 04 	vpermd zmm5,zmm1,ZMMWORD PTR [r14+0x100]
  22:	62 d2 75 48 36 76 05 	vpermd zmm6,zmm1,ZMMWORD PTR [r14+0x140]
  29:	62 d2 75 48 36 7e 06 	vpermd zmm7,zmm1,ZMMWORD PTR [r14+0x180]
  30:	62 52 75 48 36 46 07 	vpermd zmm8,zmm1,ZMMWORD PTR [r14+0x1c0]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.01
- Reference cycles: 5.7
- UOPS_EXECUTED.THREAD: 17.01
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	62 d2 75 48 36 06    	vpermd zmm0,zmm1,ZMMWORD PTR [r14]
   6:	62 d2 75 48 36 56 01 	vpermd zmm2,zmm1,ZMMWORD PTR [r14+0x40]
   d:	62 d2 75 48 36 5e 02 	vpermd zmm3,zmm1,ZMMWORD PTR [r14+0x80]
  14:	62 d2 75 48 36 66 03 	vpermd zmm4,zmm1,ZMMWORD PTR [r14+0xc0]
  1b:	62 d2 75 48 36 6e 04 	vpermd zmm5,zmm1,ZMMWORD PTR [r14+0x100]
  22:	62 d2 75 48 36 76 05 	vpermd zmm6,zmm1,ZMMWORD PTR [r14+0x140]
  29:	62 d2 75 48 36 7e 06 	vpermd zmm7,zmm1,ZMMWORD PTR [r14+0x180]
  30:	62 52 75 48 36 46 07 	vpermd zmm8,zmm1,ZMMWORD PTR [r14+0x1c0]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.02
- Reference cycles: 5.7
- UOPS_EXECUTED.THREAD: 16.11
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 d2 75 48 36 06    	vpermd zmm0,zmm1,ZMMWORD PTR [r14]
   6:	62 d2 75 48 36 56 01 	vpermd zmm2,zmm1,ZMMWORD PTR [r14+0x40]
   d:	62 d2 75 48 36 5e 02 	vpermd zmm3,zmm1,ZMMWORD PTR [r14+0x80]
  14:	62 d2 75 48 36 66 03 	vpermd zmm4,zmm1,ZMMWORD PTR [r14+0xc0]
  1b:	62 d2 75 48 36 6e 04 	vpermd zmm5,zmm1,ZMMWORD PTR [r14+0x100]
  22:	62 d2 75 48 36 76 05 	vpermd zmm6,zmm1,ZMMWORD PTR [r14+0x140]
  29:	62 d2 75 48 36 7e 06 	vpermd zmm7,zmm1,ZMMWORD PTR [r14+0x180]
  30:	62 52 75 48 36 46 07 	vpermd zmm8,zmm1,ZMMWORD PTR [r14+0x1c0]
  37:	62 52 75 48 36 4e 08 	vpermd zmm9,zmm1,ZMMWORD PTR [r14+0x200]
  3e:	62 52 75 48 36 56 09 	vpermd zmm10,zmm1,ZMMWORD PTR [r14+0x240]
  45:	62 52 75 48 36 5e 0a 	vpermd zmm11,zmm1,ZMMWORD PTR [r14+0x280]
  4c:	62 52 75 48 36 66 0b 	vpermd zmm12,zmm1,ZMMWORD PTR [r14+0x2c0]
  53:	62 c2 75 48 36 46 0c 	vpermd zmm16,zmm1,ZMMWORD PTR [r14+0x300]
  5a:	62 c2 75 48 36 4e 0d 	vpermd zmm17,zmm1,ZMMWORD PTR [r14+0x340]
  61:	62 c2 75 48 36 56 0e 	vpermd zmm18,zmm1,ZMMWORD PTR [r14+0x380]
  68:	62 c2 75 48 36 5e 0f 	vpermd zmm19,zmm1,ZMMWORD PTR [r14+0x3c0]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 16.0
- Reference cycles: 11.65
- UOPS_EXECUTED.THREAD: 32.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 d2 75 48 36 06    	vpermd zmm0,zmm1,ZMMWORD PTR [r14]
   6:	62 d2 75 48 36 56 01 	vpermd zmm2,zmm1,ZMMWORD PTR [r14+0x40]
   d:	62 d2 75 48 36 5e 02 	vpermd zmm3,zmm1,ZMMWORD PTR [r14+0x80]
  14:	62 d2 75 48 36 66 03 	vpermd zmm4,zmm1,ZMMWORD PTR [r14+0xc0]
  1b:	62 d2 75 48 36 6e 04 	vpermd zmm5,zmm1,ZMMWORD PTR [r14+0x100]
  22:	62 d2 75 48 36 76 05 	vpermd zmm6,zmm1,ZMMWORD PTR [r14+0x140]
  29:	62 d2 75 48 36 7e 06 	vpermd zmm7,zmm1,ZMMWORD PTR [r14+0x180]
  30:	62 52 75 48 36 46 07 	vpermd zmm8,zmm1,ZMMWORD PTR [r14+0x1c0]
  37:	62 52 75 48 36 4e 08 	vpermd zmm9,zmm1,ZMMWORD PTR [r14+0x200]
  3e:	62 52 75 48 36 56 09 	vpermd zmm10,zmm1,ZMMWORD PTR [r14+0x240]
  45:	62 52 75 48 36 5e 0a 	vpermd zmm11,zmm1,ZMMWORD PTR [r14+0x280]
  4c:	62 52 75 48 36 66 0b 	vpermd zmm12,zmm1,ZMMWORD PTR [r14+0x2c0]
  53:	62 c2 75 48 36 46 0c 	vpermd zmm16,zmm1,ZMMWORD PTR [r14+0x300]
  5a:	62 c2 75 48 36 4e 0d 	vpermd zmm17,zmm1,ZMMWORD PTR [r14+0x340]
  61:	62 c2 75 48 36 56 0e 	vpermd zmm18,zmm1,ZMMWORD PTR [r14+0x380]
  68:	62 c2 75 48 36 5e 0f 	vpermd zmm19,zmm1,ZMMWORD PTR [r14+0x3c0]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 16.02
- Reference cycles: 11.45
- UOPS_EXECUTED.THREAD: 33.0
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	62 d2 75 48 36 06    	vpermd zmm0,zmm1,ZMMWORD PTR [r14]
   6:	62 d2 75 48 36 56 01 	vpermd zmm2,zmm1,ZMMWORD PTR [r14+0x40]
   d:	62 d2 75 48 36 5e 02 	vpermd zmm3,zmm1,ZMMWORD PTR [r14+0x80]
  14:	62 d2 75 48 36 66 03 	vpermd zmm4,zmm1,ZMMWORD PTR [r14+0xc0]
  1b:	62 d2 75 48 36 6e 04 	vpermd zmm5,zmm1,ZMMWORD PTR [r14+0x100]
  22:	62 d2 75 48 36 76 05 	vpermd zmm6,zmm1,ZMMWORD PTR [r14+0x140]
  29:	62 d2 75 48 36 7e 06 	vpermd zmm7,zmm1,ZMMWORD PTR [r14+0x180]
  30:	62 52 75 48 36 46 07 	vpermd zmm8,zmm1,ZMMWORD PTR [r14+0x1c0]
  37:	62 52 75 48 36 4e 08 	vpermd zmm9,zmm1,ZMMWORD PTR [r14+0x200]
  3e:	62 52 75 48 36 56 09 	vpermd zmm10,zmm1,ZMMWORD PTR [r14+0x240]
  45:	62 52 75 48 36 5e 0a 	vpermd zmm11,zmm1,ZMMWORD PTR [r14+0x280]
  4c:	62 52 75 48 36 66 0b 	vpermd zmm12,zmm1,ZMMWORD PTR [r14+0x2c0]
  53:	62 c2 75 48 36 46 0c 	vpermd zmm16,zmm1,ZMMWORD PTR [r14+0x300]
  5a:	62 c2 75 48 36 4e 0d 	vpermd zmm17,zmm1,ZMMWORD PTR [r14+0x340]
  61:	62 c2 75 48 36 56 0e 	vpermd zmm18,zmm1,ZMMWORD PTR [r14+0x380]
  68:	62 c2 75 48 36 5e 0f 	vpermd zmm19,zmm1,ZMMWORD PTR [r14+0x3c0]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 16.01
- Reference cycles: 11.45
- UOPS_EXECUTED.THREAD: 32.11
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	62 92 75 48 36 04 2e 	vpermd zmm0,zmm1,ZMMWORD PTR [r14+r13*1]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.64
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	62 92 75 48 36 04 2e 	vpermd zmm0,zmm1,ZMMWORD PTR [r14+r13*1]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 0.71
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 92 75 48 36 04 2e 	vpermd zmm0,zmm1,ZMMWORD PTR [r14+r13*1]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 0.72
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 92 75 48 36 04 2e 	vpermd zmm0,zmm1,ZMMWORD PTR [r14+r13*1]
   7:	62 92 75 48 36 54 2e 	vpermd zmm2,zmm1,ZMMWORD PTR [r14+r13*1+0x40]
   e:	01 
   f:	62 92 75 48 36 5c 2e 	vpermd zmm3,zmm1,ZMMWORD PTR [r14+r13*1+0x80]
  16:	02 
  17:	62 92 75 48 36 64 2e 	vpermd zmm4,zmm1,ZMMWORD PTR [r14+r13*1+0xc0]
  1e:	03

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 3.07
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	62 92 75 48 36 04 2e 	vpermd zmm0,zmm1,ZMMWORD PTR [r14+r13*1]
   7:	62 92 75 48 36 54 2e 	vpermd zmm2,zmm1,ZMMWORD PTR [r14+r13*1+0x40]
   e:	01 
   f:	62 92 75 48 36 5c 2e 	vpermd zmm3,zmm1,ZMMWORD PTR [r14+r13*1+0x80]
  16:	02 
  17:	62 92 75 48 36 64 2e 	vpermd zmm4,zmm1,ZMMWORD PTR [r14+r13*1+0xc0]
  1e:	03

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.01
- Reference cycles: 2.85
- UOPS_EXECUTED.THREAD: 8.5
- RETIRE_SLOTS: 8.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	62 92 75 48 36 04 2e 	vpermd zmm0,zmm1,ZMMWORD PTR [r14+r13*1]
   7:	62 92 75 48 36 54 2e 	vpermd zmm2,zmm1,ZMMWORD PTR [r14+r13*1+0x40]
   e:	01 
   f:	62 92 75 48 36 5c 2e 	vpermd zmm3,zmm1,ZMMWORD PTR [r14+r13*1+0x80]
  16:	02 
  17:	62 92 75 48 36 64 2e 	vpermd zmm4,zmm1,ZMMWORD PTR [r14+r13*1+0xc0]
  1e:	03

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.01
- Reference cycles: 2.85
- UOPS_EXECUTED.THREAD: 8.05
- RETIRE_SLOTS: 8.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 92 75 48 36 04 2e 	vpermd zmm0,zmm1,ZMMWORD PTR [r14+r13*1]
   7:	62 92 75 48 36 54 2e 	vpermd zmm2,zmm1,ZMMWORD PTR [r14+r13*1+0x40]
   e:	01 
   f:	62 92 75 48 36 5c 2e 	vpermd zmm3,zmm1,ZMMWORD PTR [r14+r13*1+0x80]
  16:	02 
  17:	62 92 75 48 36 64 2e 	vpermd zmm4,zmm1,ZMMWORD PTR [r14+r13*1+0xc0]
  1e:	03 
  1f:	62 92 75 48 36 6c 2e 	vpermd zmm5,zmm1,ZMMWORD PTR [r14+r13*1+0x100]
  26:	04 
  27:	62 92 75 48 36 74 2e 	vpermd zmm6,zmm1,ZMMWORD PTR [r14+r13*1+0x140]
  2e:	05 
  2f:	62 92 75 48 36 7c 2e 	vpermd zmm7,zmm1,ZMMWORD PTR [r14+r13*1+0x180]
  36:	06 
  37:	62 12 75 48 36 44 2e 	vpermd zmm8,zmm1,ZMMWORD PTR [r14+r13*1+0x1c0]
  3e:	07

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.01
- Reference cycles: 5.52
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 92 75 48 36 04 2e 	vpermd zmm0,zmm1,ZMMWORD PTR [r14+r13*1]
   7:	62 92 75 48 36 54 2e 	vpermd zmm2,zmm1,ZMMWORD PTR [r14+r13*1+0x40]
   e:	01 
   f:	62 92 75 48 36 5c 2e 	vpermd zmm3,zmm1,ZMMWORD PTR [r14+r13*1+0x80]
  16:	02 
  17:	62 92 75 48 36 64 2e 	vpermd zmm4,zmm1,ZMMWORD PTR [r14+r13*1+0xc0]
  1e:	03 
  1f:	62 92 75 48 36 6c 2e 	vpermd zmm5,zmm1,ZMMWORD PTR [r14+r13*1+0x100]
  26:	04 
  27:	62 92 75 48 36 74 2e 	vpermd zmm6,zmm1,ZMMWORD PTR [r14+r13*1+0x140]
  2e:	05 
  2f:	62 92 75 48 36 7c 2e 	vpermd zmm7,zmm1,ZMMWORD PTR [r14+r13*1+0x180]
  36:	06 
  37:	62 12 75 48 36 44 2e 	vpermd zmm8,zmm1,ZMMWORD PTR [r14+r13*1+0x1c0]
  3e:	07

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.02
- Reference cycles: 5.77
- UOPS_EXECUTED.THREAD: 17.01
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	62 92 75 48 36 04 2e 	vpermd zmm0,zmm1,ZMMWORD PTR [r14+r13*1]
   7:	62 92 75 48 36 54 2e 	vpermd zmm2,zmm1,ZMMWORD PTR [r14+r13*1+0x40]
   e:	01 
   f:	62 92 75 48 36 5c 2e 	vpermd zmm3,zmm1,ZMMWORD PTR [r14+r13*1+0x80]
  16:	02 
  17:	62 92 75 48 36 64 2e 	vpermd zmm4,zmm1,ZMMWORD PTR [r14+r13*1+0xc0]
  1e:	03 
  1f:	62 92 75 48 36 6c 2e 	vpermd zmm5,zmm1,ZMMWORD PTR [r14+r13*1+0x100]
  26:	04 
  27:	62 92 75 48 36 74 2e 	vpermd zmm6,zmm1,ZMMWORD PTR [r14+r13*1+0x140]
  2e:	05 
  2f:	62 92 75 48 36 7c 2e 	vpermd zmm7,zmm1,ZMMWORD PTR [r14+r13*1+0x180]
  36:	06 
  37:	62 12 75 48 36 44 2e 	vpermd zmm8,zmm1,ZMMWORD PTR [r14+r13*1+0x1c0]
  3e:	07

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.02
- Reference cycles: 5.73
- UOPS_EXECUTED.THREAD: 16.1
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 92 75 48 36 04 2e 	vpermd zmm0,zmm1,ZMMWORD PTR [r14+r13*1]
   7:	62 92 75 48 36 54 2e 	vpermd zmm2,zmm1,ZMMWORD PTR [r14+r13*1+0x40]
   e:	01 
   f:	62 92 75 48 36 5c 2e 	vpermd zmm3,zmm1,ZMMWORD PTR [r14+r13*1+0x80]
  16:	02 
  17:	62 92 75 48 36 64 2e 	vpermd zmm4,zmm1,ZMMWORD PTR [r14+r13*1+0xc0]
  1e:	03 
  1f:	62 92 75 48 36 6c 2e 	vpermd zmm5,zmm1,ZMMWORD PTR [r14+r13*1+0x100]
  26:	04 
  27:	62 92 75 48 36 74 2e 	vpermd zmm6,zmm1,ZMMWORD PTR [r14+r13*1+0x140]
  2e:	05 
  2f:	62 92 75 48 36 7c 2e 	vpermd zmm7,zmm1,ZMMWORD PTR [r14+r13*1+0x180]
  36:	06 
  37:	62 12 75 48 36 44 2e 	vpermd zmm8,zmm1,ZMMWORD PTR [r14+r13*1+0x1c0]
  3e:	07 
  3f:	62 12 75 48 36 4c 2e 	vpermd zmm9,zmm1,ZMMWORD PTR [r14+r13*1+0x200]
  46:	08 
  47:	62 12 75 48 36 54 2e 	vpermd zmm10,zmm1,ZMMWORD PTR [r14+r13*1+0x240]
  4e:	09 
  4f:	62 12 75 48 36 5c 2e 	vpermd zmm11,zmm1,ZMMWORD PTR [r14+r13*1+0x280]
  56:	0a 
  57:	62 12 75 48 36 64 2e 	vpermd zmm12,zmm1,ZMMWORD PTR [r14+r13*1+0x2c0]
  5e:	0b 
  5f:	62 82 75 48 36 44 2e 	vpermd zmm16,zmm1,ZMMWORD PTR [r14+r13*1+0x300]
  66:	0c 
  67:	62 82 75 48 36 4c 2e 	vpermd zmm17,zmm1,ZMMWORD PTR [r14+r13*1+0x340]
  6e:	0d 
  6f:	62 82 75 48 36 54 2e 	vpermd zmm18,zmm1,ZMMWORD PTR [r14+r13*1+0x380]
  76:	0e 
  77:	62 82 75 48 36 5c 2e 	vpermd zmm19,zmm1,ZMMWORD PTR [r14+r13*1+0x3c0]
  7e:	0f

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 16.0
- Reference cycles: 11.19
- UOPS_EXECUTED.THREAD: 32.0
- RETIRE_SLOTS: 32.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 92 75 48 36 04 2e 	vpermd zmm0,zmm1,ZMMWORD PTR [r14+r13*1]
   7:	62 92 75 48 36 54 2e 	vpermd zmm2,zmm1,ZMMWORD PTR [r14+r13*1+0x40]
   e:	01 
   f:	62 92 75 48 36 5c 2e 	vpermd zmm3,zmm1,ZMMWORD PTR [r14+r13*1+0x80]
  16:	02 
  17:	62 92 75 48 36 64 2e 	vpermd zmm4,zmm1,ZMMWORD PTR [r14+r13*1+0xc0]
  1e:	03 
  1f:	62 92 75 48 36 6c 2e 	vpermd zmm5,zmm1,ZMMWORD PTR [r14+r13*1+0x100]
  26:	04 
  27:	62 92 75 48 36 74 2e 	vpermd zmm6,zmm1,ZMMWORD PTR [r14+r13*1+0x140]
  2e:	05 
  2f:	62 92 75 48 36 7c 2e 	vpermd zmm7,zmm1,ZMMWORD PTR [r14+r13*1+0x180]
  36:	06 
  37:	62 12 75 48 36 44 2e 	vpermd zmm8,zmm1,ZMMWORD PTR [r14+r13*1+0x1c0]
  3e:	07 
  3f:	62 12 75 48 36 4c 2e 	vpermd zmm9,zmm1,ZMMWORD PTR [r14+r13*1+0x200]
  46:	08 
  47:	62 12 75 48 36 54 2e 	vpermd zmm10,zmm1,ZMMWORD PTR [r14+r13*1+0x240]
  4e:	09 
  4f:	62 12 75 48 36 5c 2e 	vpermd zmm11,zmm1,ZMMWORD PTR [r14+r13*1+0x280]
  56:	0a 
  57:	62 12 75 48 36 64 2e 	vpermd zmm12,zmm1,ZMMWORD PTR [r14+r13*1+0x2c0]
  5e:	0b 
  5f:	62 82 75 48 36 44 2e 	vpermd zmm16,zmm1,ZMMWORD PTR [r14+r13*1+0x300]
  66:	0c 
  67:	62 82 75 48 36 4c 2e 	vpermd zmm17,zmm1,ZMMWORD PTR [r14+r13*1+0x340]
  6e:	0d 
  6f:	62 82 75 48 36 54 2e 	vpermd zmm18,zmm1,ZMMWORD PTR [r14+r13*1+0x380]
  76:	0e 
  77:	62 82 75 48 36 5c 2e 	vpermd zmm19,zmm1,ZMMWORD PTR [r14+r13*1+0x3c0]
  7e:	0f

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 16.02
- Reference cycles: 11.41
- UOPS_EXECUTED.THREAD: 33.01
- RETIRE_SLOTS: 33.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	62 92 75 48 36 04 2e 	vpermd zmm0,zmm1,ZMMWORD PTR [r14+r13*1]
   7:	62 92 75 48 36 54 2e 	vpermd zmm2,zmm1,ZMMWORD PTR [r14+r13*1+0x40]
   e:	01 
   f:	62 92 75 48 36 5c 2e 	vpermd zmm3,zmm1,ZMMWORD PTR [r14+r13*1+0x80]
  16:	02 
  17:	62 92 75 48 36 64 2e 	vpermd zmm4,zmm1,ZMMWORD PTR [r14+r13*1+0xc0]
  1e:	03 
  1f:	62 92 75 48 36 6c 2e 	vpermd zmm5,zmm1,ZMMWORD PTR [r14+r13*1+0x100]
  26:	04 
  27:	62 92 75 48 36 74 2e 	vpermd zmm6,zmm1,ZMMWORD PTR [r14+r13*1+0x140]
  2e:	05 
  2f:	62 92 75 48 36 7c 2e 	vpermd zmm7,zmm1,ZMMWORD PTR [r14+r13*1+0x180]
  36:	06 
  37:	62 12 75 48 36 44 2e 	vpermd zmm8,zmm1,ZMMWORD PTR [r14+r13*1+0x1c0]
  3e:	07 
  3f:	62 12 75 48 36 4c 2e 	vpermd zmm9,zmm1,ZMMWORD PTR [r14+r13*1+0x200]
  46:	08 
  47:	62 12 75 48 36 54 2e 	vpermd zmm10,zmm1,ZMMWORD PTR [r14+r13*1+0x240]
  4e:	09 
  4f:	62 12 75 48 36 5c 2e 	vpermd zmm11,zmm1,ZMMWORD PTR [r14+r13*1+0x280]
  56:	0a 
  57:	62 12 75 48 36 64 2e 	vpermd zmm12,zmm1,ZMMWORD PTR [r14+r13*1+0x2c0]
  5e:	0b 
  5f:	62 82 75 48 36 44 2e 	vpermd zmm16,zmm1,ZMMWORD PTR [r14+r13*1+0x300]
  66:	0c 
  67:	62 82 75 48 36 4c 2e 	vpermd zmm17,zmm1,ZMMWORD PTR [r14+r13*1+0x340]
  6e:	0d 
  6f:	62 82 75 48 36 54 2e 	vpermd zmm18,zmm1,ZMMWORD PTR [r14+r13*1+0x380]
  76:	0e 
  77:	62 82 75 48 36 5c 2e 	vpermd zmm19,zmm1,ZMMWORD PTR [r14+r13*1+0x3c0]
  7e:	0f

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 16.02
- Reference cycles: 11.41
- UOPS_EXECUTED.THREAD: 32.11
- RETIRE_SLOTS: 32.1
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

VPERMD (ZMM, ZMM, M512) - Throughput and Uops

With a non-indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10