VEXTRACTF64X4 (YMM, ZMM, I8)

With unroll_count=500 and no inner loop

Code:

   0:	62 f3 fd 48 1b c8 02 	vextractf64x4 ymm0,zmm1,0x2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.58
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	62 f3 fd 48 1b c8 02 	vextractf64x4 ymm0,zmm1,0x2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 0.69
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 f3 fd 48 1b c8 02 	vextractf64x4 ymm0,zmm1,0x2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 0.69
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 f3 fd 48 1b c8 02 	vextractf64x4 ymm0,zmm1,0x2
   7:	62 f3 fd 48 1b ca 02 	vextractf64x4 ymm2,zmm1,0x2
   e:	62 f3 fd 48 1b cb 02 	vextractf64x4 ymm3,zmm1,0x2
  15:	62 f3 fd 48 1b cc 02 	vextractf64x4 ymm4,zmm1,0x2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 2.68
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	62 f3 fd 48 1b c8 02 	vextractf64x4 ymm0,zmm1,0x2
   7:	62 f3 fd 48 1b ca 02 	vextractf64x4 ymm2,zmm1,0x2
   e:	62 f3 fd 48 1b cb 02 	vextractf64x4 ymm3,zmm1,0x2
  15:	62 f3 fd 48 1b cc 02 	vextractf64x4 ymm4,zmm1,0x2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.0
- Reference cycles: 2.76
- UOPS_EXECUTED.THREAD: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	62 f3 fd 48 1b c8 02 	vextractf64x4 ymm0,zmm1,0x2
   7:	62 f3 fd 48 1b ca 02 	vextractf64x4 ymm2,zmm1,0x2
   e:	62 f3 fd 48 1b cb 02 	vextractf64x4 ymm3,zmm1,0x2
  15:	62 f3 fd 48 1b cc 02 	vextractf64x4 ymm4,zmm1,0x2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.01
- Reference cycles: 2.78
- UOPS_EXECUTED.THREAD: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f3 fd 48 1b c8 02 	vextractf64x4 ymm0,zmm1,0x2
   7:	62 f3 fd 48 1b ca 02 	vextractf64x4 ymm2,zmm1,0x2
   e:	62 f3 fd 48 1b cb 02 	vextractf64x4 ymm3,zmm1,0x2
  15:	62 f3 fd 48 1b cc 02 	vextractf64x4 ymm4,zmm1,0x2
  1c:	62 f3 fd 48 1b cd 02 	vextractf64x4 ymm5,zmm1,0x2
  23:	62 f3 fd 48 1b ce 02 	vextractf64x4 ymm6,zmm1,0x2
  2a:	62 f3 fd 48 1b cf 02 	vextractf64x4 ymm7,zmm1,0x2
  31:	62 d3 fd 48 1b c8 02 	vextractf64x4 ymm8,zmm1,0x2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 5.37
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f3 fd 48 1b c8 02 	vextractf64x4 ymm0,zmm1,0x2
   7:	62 f3 fd 48 1b ca 02 	vextractf64x4 ymm2,zmm1,0x2
   e:	62 f3 fd 48 1b cb 02 	vextractf64x4 ymm3,zmm1,0x2
  15:	62 f3 fd 48 1b cc 02 	vextractf64x4 ymm4,zmm1,0x2
  1c:	62 f3 fd 48 1b cd 02 	vextractf64x4 ymm5,zmm1,0x2
  23:	62 f3 fd 48 1b ce 02 	vextractf64x4 ymm6,zmm1,0x2
  2a:	62 f3 fd 48 1b cf 02 	vextractf64x4 ymm7,zmm1,0x2
  31:	62 d3 fd 48 1b c8 02 	vextractf64x4 ymm8,zmm1,0x2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.01
- Reference cycles: 5.57
- UOPS_EXECUTED.THREAD: 9.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	62 f3 fd 48 1b c8 02 	vextractf64x4 ymm0,zmm1,0x2
   7:	62 f3 fd 48 1b ca 02 	vextractf64x4 ymm2,zmm1,0x2
   e:	62 f3 fd 48 1b cb 02 	vextractf64x4 ymm3,zmm1,0x2
  15:	62 f3 fd 48 1b cc 02 	vextractf64x4 ymm4,zmm1,0x2
  1c:	62 f3 fd 48 1b cd 02 	vextractf64x4 ymm5,zmm1,0x2
  23:	62 f3 fd 48 1b ce 02 	vextractf64x4 ymm6,zmm1,0x2
  2a:	62 f3 fd 48 1b cf 02 	vextractf64x4 ymm7,zmm1,0x2
  31:	62 d3 fd 48 1b c8 02 	vextractf64x4 ymm8,zmm1,0x2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.01
- Reference cycles: 5.57
- UOPS_EXECUTED.THREAD: 8.1
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f3 fd 48 1b c8 02 	vextractf64x4 ymm0,zmm1,0x2
   7:	62 f3 fd 48 1b ca 02 	vextractf64x4 ymm2,zmm1,0x2
   e:	62 f3 fd 48 1b cb 02 	vextractf64x4 ymm3,zmm1,0x2
  15:	62 f3 fd 48 1b cc 02 	vextractf64x4 ymm4,zmm1,0x2
  1c:	62 f3 fd 48 1b cd 02 	vextractf64x4 ymm5,zmm1,0x2
  23:	62 f3 fd 48 1b ce 02 	vextractf64x4 ymm6,zmm1,0x2
  2a:	62 f3 fd 48 1b cf 02 	vextractf64x4 ymm7,zmm1,0x2
  31:	62 d3 fd 48 1b c8 02 	vextractf64x4 ymm8,zmm1,0x2
  38:	62 d3 fd 48 1b c9 02 	vextractf64x4 ymm9,zmm1,0x2
  3f:	62 d3 fd 48 1b ca 02 	vextractf64x4 ymm10,zmm1,0x2
  46:	62 d3 fd 48 1b cb 02 	vextractf64x4 ymm11,zmm1,0x2
  4d:	62 d3 fd 48 1b cc 02 	vextractf64x4 ymm12,zmm1,0x2
  54:	62 b3 fd 48 1b c8 02 	vextractf64x4 ymm16,zmm1,0x2
  5b:	62 b3 fd 48 1b c9 02 	vextractf64x4 ymm17,zmm1,0x2
  62:	62 b3 fd 48 1b ca 02 	vextractf64x4 ymm18,zmm1,0x2
  69:	62 b3 fd 48 1b cb 02 	vextractf64x4 ymm19,zmm1,0x2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 16.0
- Reference cycles: 11.65
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f3 fd 48 1b c8 02 	vextractf64x4 ymm0,zmm1,0x2
   7:	62 f3 fd 48 1b ca 02 	vextractf64x4 ymm2,zmm1,0x2
   e:	62 f3 fd 48 1b cb 02 	vextractf64x4 ymm3,zmm1,0x2
  15:	62 f3 fd 48 1b cc 02 	vextractf64x4 ymm4,zmm1,0x2
  1c:	62 f3 fd 48 1b cd 02 	vextractf64x4 ymm5,zmm1,0x2
  23:	62 f3 fd 48 1b ce 02 	vextractf64x4 ymm6,zmm1,0x2
  2a:	62 f3 fd 48 1b cf 02 	vextractf64x4 ymm7,zmm1,0x2
  31:	62 d3 fd 48 1b c8 02 	vextractf64x4 ymm8,zmm1,0x2
  38:	62 d3 fd 48 1b c9 02 	vextractf64x4 ymm9,zmm1,0x2
  3f:	62 d3 fd 48 1b ca 02 	vextractf64x4 ymm10,zmm1,0x2
  46:	62 d3 fd 48 1b cb 02 	vextractf64x4 ymm11,zmm1,0x2
  4d:	62 d3 fd 48 1b cc 02 	vextractf64x4 ymm12,zmm1,0x2
  54:	62 b3 fd 48 1b c8 02 	vextractf64x4 ymm16,zmm1,0x2
  5b:	62 b3 fd 48 1b c9 02 	vextractf64x4 ymm17,zmm1,0x2
  62:	62 b3 fd 48 1b ca 02 	vextractf64x4 ymm18,zmm1,0x2
  69:	62 b3 fd 48 1b cb 02 	vextractf64x4 ymm19,zmm1,0x2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 16.01
- Reference cycles: 11.41
- UOPS_EXECUTED.THREAD: 17.0
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	62 f3 fd 48 1b c8 02 	vextractf64x4 ymm0,zmm1,0x2
   7:	62 f3 fd 48 1b ca 02 	vextractf64x4 ymm2,zmm1,0x2
   e:	62 f3 fd 48 1b cb 02 	vextractf64x4 ymm3,zmm1,0x2
  15:	62 f3 fd 48 1b cc 02 	vextractf64x4 ymm4,zmm1,0x2
  1c:	62 f3 fd 48 1b cd 02 	vextractf64x4 ymm5,zmm1,0x2
  23:	62 f3 fd 48 1b ce 02 	vextractf64x4 ymm6,zmm1,0x2
  2a:	62 f3 fd 48 1b cf 02 	vextractf64x4 ymm7,zmm1,0x2
  31:	62 d3 fd 48 1b c8 02 	vextractf64x4 ymm8,zmm1,0x2
  38:	62 d3 fd 48 1b c9 02 	vextractf64x4 ymm9,zmm1,0x2
  3f:	62 d3 fd 48 1b ca 02 	vextractf64x4 ymm10,zmm1,0x2
  46:	62 d3 fd 48 1b cb 02 	vextractf64x4 ymm11,zmm1,0x2
  4d:	62 d3 fd 48 1b cc 02 	vextractf64x4 ymm12,zmm1,0x2
  54:	62 b3 fd 48 1b c8 02 	vextractf64x4 ymm16,zmm1,0x2
  5b:	62 b3 fd 48 1b c9 02 	vextractf64x4 ymm17,zmm1,0x2
  62:	62 b3 fd 48 1b ca 02 	vextractf64x4 ymm18,zmm1,0x2
  69:	62 b3 fd 48 1b cb 02 	vextractf64x4 ymm19,zmm1,0x2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 16.01
- Reference cycles: 11.45
- UOPS_EXECUTED.THREAD: 16.1
- RETIRE_SLOTS: 16.11
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.05

With the same register for for different operands

With unroll_count=500 and no inner loop

Code:

   0:	62 f3 fd 48 1b c0 02 	vextractf64x4 ymm0,zmm0,0x2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 3.0
- Reference cycles: 2.15
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	62 f3 fd 48 1b c0 02 	vextractf64x4 ymm0,zmm0,0x2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 3.0
- Reference cycles: 2.14
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 f3 fd 48 1b c0 02 	vextractf64x4 ymm0,zmm0,0x2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 3.0
- Reference cycles: 2.14
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

VEXTRACTF64X4 (YMM, ZMM, I8) - Throughput and Uops

With different registers for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With the same register for for different operands

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100