VCOMPRESSPD (YMM, K, YMM)

With unroll_count=500 and no inner loop

Code:

   0:	62 f2 fd 29 8a c8    	vcompresspd ymm0{k1},ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 3.0
- Reference cycles: 2.21
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	62 f2 fd 29 8a c8    	vcompresspd ymm0{k1},ymm1
   6:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.0
- Reference cycles: 2.18
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 3.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	62 f2 fd 29 8a c8    	vcompresspd ymm0{k1},ymm1
   6:	90                   	nop
   7:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 3.0
- Reference cycles: 2.21
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	62 f2 fd 29 8a c8    	vcompresspd ymm0{k1},ymm1
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 3.0
- Reference cycles: 2.21
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 4 NOPs

Code:

   0:	62 f2 fd 29 8a c8    	vcompresspd ymm0{k1},ymm1
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 3.0
- Reference cycles: 2.21
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 6.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	62 f2 fd 29 8a c8    	vcompresspd ymm0{k1},ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 3.0
- Reference cycles: 2.21
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 f2 fd 29 8a c8    	vcompresspd ymm0{k1},ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 3.0
- Reference cycles: 2.21
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 f2 fd 29 8a c8    	vcompresspd ymm0{k1},ymm1
   6:	62 f2 fd 29 8a ca    	vcompresspd ymm2{k1},ymm1
   c:	62 f2 fd 29 8a cb    	vcompresspd ymm3{k1},ymm1
  12:	62 f2 fd 29 8a cc    	vcompresspd ymm4{k1},ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14];
VMOVUPD YMM3, [R14];
VMOVUPD YMM4, [R14]

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 8.01
- Reference cycles: 5.98
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	62 f2 fd 29 8a c8    	vcompresspd ymm0{k1},ymm1
   6:	62 f2 fd 29 8a ca    	vcompresspd ymm2{k1},ymm1
   c:	62 f2 fd 29 8a cb    	vcompresspd ymm3{k1},ymm1
  12:	62 f2 fd 29 8a cc    	vcompresspd ymm4{k1},ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14];
VMOVUPD YMM3, [R14];
VMOVUPD YMM4, [R14]

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 8.01
- Reference cycles: 5.89
- UOPS_EXECUTED.THREAD: 8.5
- RETIRE_SLOTS: 8.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	62 f2 fd 29 8a c8    	vcompresspd ymm0{k1},ymm1
   6:	62 f2 fd 29 8a ca    	vcompresspd ymm2{k1},ymm1
   c:	62 f2 fd 29 8a cb    	vcompresspd ymm3{k1},ymm1
  12:	62 f2 fd 29 8a cc    	vcompresspd ymm4{k1},ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14];
VMOVUPD YMM3, [R14];
VMOVUPD YMM4, [R14]

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 8.0
- Reference cycles: 5.71
- UOPS_EXECUTED.THREAD: 8.05
- RETIRE_SLOTS: 8.05
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f2 fd 29 8a c8    	vcompresspd ymm0{k1},ymm1
   6:	62 f2 fd 29 8a ca    	vcompresspd ymm2{k1},ymm1
   c:	62 f2 fd 29 8a cb    	vcompresspd ymm3{k1},ymm1
  12:	62 f2 fd 29 8a cc    	vcompresspd ymm4{k1},ymm1
  18:	62 f2 fd 29 8a cd    	vcompresspd ymm5{k1},ymm1
  1e:	62 f2 fd 29 8a ce    	vcompresspd ymm6{k1},ymm1
  24:	62 f2 fd 29 8a cf    	vcompresspd ymm7{k1},ymm1
  2a:	62 d2 fd 29 8a c8    	vcompresspd ymm8{k1},ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14];
VMOVUPD YMM3, [R14];
VMOVUPD YMM4, [R14];
VMOVUPD YMM5, [R14];
VMOVUPD YMM6, [R14];
VMOVUPD YMM7, [R14];
VMOVUPD YMM8, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 16.01
- Reference cycles: 11.96
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f2 fd 29 8a c8    	vcompresspd ymm0{k1},ymm1
   6:	62 f2 fd 29 8a ca    	vcompresspd ymm2{k1},ymm1
   c:	62 f2 fd 29 8a cb    	vcompresspd ymm3{k1},ymm1
  12:	62 f2 fd 29 8a cc    	vcompresspd ymm4{k1},ymm1
  18:	62 f2 fd 29 8a cd    	vcompresspd ymm5{k1},ymm1
  1e:	62 f2 fd 29 8a ce    	vcompresspd ymm6{k1},ymm1
  24:	62 f2 fd 29 8a cf    	vcompresspd ymm7{k1},ymm1
  2a:	62 d2 fd 29 8a c8    	vcompresspd ymm8{k1},ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14];
VMOVUPD YMM3, [R14];
VMOVUPD YMM4, [R14];
VMOVUPD YMM5, [R14];
VMOVUPD YMM6, [R14];
VMOVUPD YMM7, [R14];
VMOVUPD YMM8, [R14]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 16.01
- Reference cycles: 11.42
- UOPS_EXECUTED.THREAD: 17.0
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	62 f2 fd 29 8a c8    	vcompresspd ymm0{k1},ymm1
   6:	62 f2 fd 29 8a ca    	vcompresspd ymm2{k1},ymm1
   c:	62 f2 fd 29 8a cb    	vcompresspd ymm3{k1},ymm1
  12:	62 f2 fd 29 8a cc    	vcompresspd ymm4{k1},ymm1
  18:	62 f2 fd 29 8a cd    	vcompresspd ymm5{k1},ymm1
  1e:	62 f2 fd 29 8a ce    	vcompresspd ymm6{k1},ymm1
  24:	62 f2 fd 29 8a cf    	vcompresspd ymm7{k1},ymm1
  2a:	62 d2 fd 29 8a c8    	vcompresspd ymm8{k1},ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14];
VMOVUPD YMM3, [R14];
VMOVUPD YMM4, [R14];
VMOVUPD YMM5, [R14];
VMOVUPD YMM6, [R14];
VMOVUPD YMM7, [R14];
VMOVUPD YMM8, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 16.01
- Reference cycles: 11.42
- UOPS_EXECUTED.THREAD: 16.1
- RETIRE_SLOTS: 16.11
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f2 fd 29 8a c8    	vcompresspd ymm0{k1},ymm1
   6:	62 f2 fd 29 8a ca    	vcompresspd ymm2{k1},ymm1
   c:	62 f2 fd 29 8a cb    	vcompresspd ymm3{k1},ymm1
  12:	62 f2 fd 29 8a cc    	vcompresspd ymm4{k1},ymm1
  18:	62 f2 fd 29 8a cd    	vcompresspd ymm5{k1},ymm1
  1e:	62 f2 fd 29 8a ce    	vcompresspd ymm6{k1},ymm1
  24:	62 f2 fd 29 8a cf    	vcompresspd ymm7{k1},ymm1
  2a:	62 d2 fd 29 8a c8    	vcompresspd ymm8{k1},ymm1
  30:	62 d2 fd 29 8a c9    	vcompresspd ymm9{k1},ymm1
  36:	62 d2 fd 29 8a ca    	vcompresspd ymm10{k1},ymm1
  3c:	62 d2 fd 29 8a cb    	vcompresspd ymm11{k1},ymm1
  42:	62 d2 fd 29 8a cc    	vcompresspd ymm12{k1},ymm1
  48:	62 b2 fd 29 8a c8    	vcompresspd ymm16{k1},ymm1
  4e:	62 b2 fd 29 8a c9    	vcompresspd ymm17{k1},ymm1
  54:	62 b2 fd 29 8a ca    	vcompresspd ymm18{k1},ymm1
  5a:	62 b2 fd 29 8a cb    	vcompresspd ymm19{k1},ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14];
VMOVUPD YMM3, [R14];
VMOVUPD YMM4, [R14];
VMOVUPD YMM5, [R14];
VMOVUPD YMM6, [R14];
VMOVUPD YMM7, [R14];
VMOVUPD YMM8, [R14];
VMOVUPD YMM9, [R14];
VMOVUPD YMM10, [R14];
VMOVUPD YMM11, [R14];
VMOVUPD YMM12, [R14];
VMOVUPD YMM16, [R14];
VMOVUPD YMM17, [R14];
VMOVUPD YMM18, [R14];
VMOVUPD YMM19, [R14]

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 31.99
- Reference cycles: 23.46
- UOPS_EXECUTED.THREAD: 32.0
- RETIRE_SLOTS: 32.0
- UOPS_MITE: 32.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 32.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f2 fd 29 8a c8    	vcompresspd ymm0{k1},ymm1
   6:	62 f2 fd 29 8a ca    	vcompresspd ymm2{k1},ymm1
   c:	62 f2 fd 29 8a cb    	vcompresspd ymm3{k1},ymm1
  12:	62 f2 fd 29 8a cc    	vcompresspd ymm4{k1},ymm1
  18:	62 f2 fd 29 8a cd    	vcompresspd ymm5{k1},ymm1
  1e:	62 f2 fd 29 8a ce    	vcompresspd ymm6{k1},ymm1
  24:	62 f2 fd 29 8a cf    	vcompresspd ymm7{k1},ymm1
  2a:	62 d2 fd 29 8a c8    	vcompresspd ymm8{k1},ymm1
  30:	62 d2 fd 29 8a c9    	vcompresspd ymm9{k1},ymm1
  36:	62 d2 fd 29 8a ca    	vcompresspd ymm10{k1},ymm1
  3c:	62 d2 fd 29 8a cb    	vcompresspd ymm11{k1},ymm1
  42:	62 d2 fd 29 8a cc    	vcompresspd ymm12{k1},ymm1
  48:	62 b2 fd 29 8a c8    	vcompresspd ymm16{k1},ymm1
  4e:	62 b2 fd 29 8a c9    	vcompresspd ymm17{k1},ymm1
  54:	62 b2 fd 29 8a ca    	vcompresspd ymm18{k1},ymm1
  5a:	62 b2 fd 29 8a cb    	vcompresspd ymm19{k1},ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14];
VMOVUPD YMM3, [R14];
VMOVUPD YMM4, [R14];
VMOVUPD YMM5, [R14];
VMOVUPD YMM6, [R14];
VMOVUPD YMM7, [R14];
VMOVUPD YMM8, [R14];
VMOVUPD YMM9, [R14];
VMOVUPD YMM10, [R14];
VMOVUPD YMM11, [R14];
VMOVUPD YMM12, [R14];
VMOVUPD YMM16, [R14];
VMOVUPD YMM17, [R14];
VMOVUPD YMM18, [R14];
VMOVUPD YMM19, [R14]

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 32.01
- Reference cycles: 22.83
- UOPS_EXECUTED.THREAD: 33.0
- RETIRE_SLOTS: 33.01
- UOPS_MITE: 0.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 32.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With loop_count=100 and unroll_count=10

Code:

   0:	62 f2 fd 29 8a c8    	vcompresspd ymm0{k1},ymm1
   6:	62 f2 fd 29 8a ca    	vcompresspd ymm2{k1},ymm1
   c:	62 f2 fd 29 8a cb    	vcompresspd ymm3{k1},ymm1
  12:	62 f2 fd 29 8a cc    	vcompresspd ymm4{k1},ymm1
  18:	62 f2 fd 29 8a cd    	vcompresspd ymm5{k1},ymm1
  1e:	62 f2 fd 29 8a ce    	vcompresspd ymm6{k1},ymm1
  24:	62 f2 fd 29 8a cf    	vcompresspd ymm7{k1},ymm1
  2a:	62 d2 fd 29 8a c8    	vcompresspd ymm8{k1},ymm1
  30:	62 d2 fd 29 8a c9    	vcompresspd ymm9{k1},ymm1
  36:	62 d2 fd 29 8a ca    	vcompresspd ymm10{k1},ymm1
  3c:	62 d2 fd 29 8a cb    	vcompresspd ymm11{k1},ymm1
  42:	62 d2 fd 29 8a cc    	vcompresspd ymm12{k1},ymm1
  48:	62 b2 fd 29 8a c8    	vcompresspd ymm16{k1},ymm1
  4e:	62 b2 fd 29 8a c9    	vcompresspd ymm17{k1},ymm1
  54:	62 b2 fd 29 8a ca    	vcompresspd ymm18{k1},ymm1
  5a:	62 b2 fd 29 8a cb    	vcompresspd ymm19{k1},ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14];
VMOVUPD YMM3, [R14];
VMOVUPD YMM4, [R14];
VMOVUPD YMM5, [R14];
VMOVUPD YMM6, [R14];
VMOVUPD YMM7, [R14];
VMOVUPD YMM8, [R14];
VMOVUPD YMM9, [R14];
VMOVUPD YMM10, [R14];
VMOVUPD YMM11, [R14];
VMOVUPD YMM12, [R14];
VMOVUPD YMM16, [R14];
VMOVUPD YMM17, [R14];
VMOVUPD YMM18, [R14];
VMOVUPD YMM19, [R14]

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 32.01
- Reference cycles: 22.88
- UOPS_EXECUTED.THREAD: 32.1
- RETIRE_SLOTS: 32.1
- UOPS_MITE: 0.32
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 32.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.16

With the same register for for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	62 f2 fd 29 8a c0    	vcompresspd ymm0{k1},ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 3.0
- Reference cycles: 2.12
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	62 f2 fd 29 8a c0    	vcompresspd ymm0{k1},ymm0
   6:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.0
- Reference cycles: 2.15
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 3.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	62 f2 fd 29 8a c0    	vcompresspd ymm0{k1},ymm0
   6:	90                   	nop
   7:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 3.0
- Reference cycles: 2.18
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	62 f2 fd 29 8a c0    	vcompresspd ymm0{k1},ymm0
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 3.0
- Reference cycles: 2.18
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 4 NOPs

Code:

   0:	62 f2 fd 29 8a c0    	vcompresspd ymm0{k1},ymm0
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 3.0
- Reference cycles: 2.18
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 6.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	62 f2 fd 29 8a c0    	vcompresspd ymm0{k1},ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 3.0
- Reference cycles: 2.14
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 f2 fd 29 8a c0    	vcompresspd ymm0{k1},ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 3.0
- Reference cycles: 2.14
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 f2 fd 29 8a c0    	vcompresspd ymm0{k1},ymm0
   6:	62 f2 fd 29 8a c9    	vcompresspd ymm1{k1},ymm1
   c:	62 f2 fd 29 8a d2    	vcompresspd ymm2{k1},ymm2
  12:	62 f2 fd 29 8a db    	vcompresspd ymm3{k1},ymm3

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14];
VMOVUPD YMM3, [R14]

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 8.01
- Reference cycles: 5.9
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	62 f2 fd 29 8a c0    	vcompresspd ymm0{k1},ymm0
   6:	62 f2 fd 29 8a c9    	vcompresspd ymm1{k1},ymm1
   c:	62 f2 fd 29 8a d2    	vcompresspd ymm2{k1},ymm2
  12:	62 f2 fd 29 8a db    	vcompresspd ymm3{k1},ymm3

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14];
VMOVUPD YMM3, [R14]

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 8.01
- Reference cycles: 5.75
- UOPS_EXECUTED.THREAD: 8.5
- RETIRE_SLOTS: 8.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	62 f2 fd 29 8a c0    	vcompresspd ymm0{k1},ymm0
   6:	62 f2 fd 29 8a c9    	vcompresspd ymm1{k1},ymm1
   c:	62 f2 fd 29 8a d2    	vcompresspd ymm2{k1},ymm2
  12:	62 f2 fd 29 8a db    	vcompresspd ymm3{k1},ymm3

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14];
VMOVUPD YMM3, [R14]

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 8.0
- Reference cycles: 5.7
- UOPS_EXECUTED.THREAD: 8.05
- RETIRE_SLOTS: 8.05
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f2 fd 29 8a c0    	vcompresspd ymm0{k1},ymm0
   6:	62 f2 fd 29 8a c9    	vcompresspd ymm1{k1},ymm1
   c:	62 f2 fd 29 8a d2    	vcompresspd ymm2{k1},ymm2
  12:	62 f2 fd 29 8a db    	vcompresspd ymm3{k1},ymm3
  18:	62 f2 fd 29 8a e4    	vcompresspd ymm4{k1},ymm4
  1e:	62 f2 fd 29 8a ed    	vcompresspd ymm5{k1},ymm5
  24:	62 f2 fd 29 8a f6    	vcompresspd ymm6{k1},ymm6
  2a:	62 f2 fd 29 8a ff    	vcompresspd ymm7{k1},ymm7

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14];
VMOVUPD YMM3, [R14];
VMOVUPD YMM4, [R14];
VMOVUPD YMM5, [R14];
VMOVUPD YMM6, [R14];
VMOVUPD YMM7, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 16.01
- Reference cycles: 11.5
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f2 fd 29 8a c0    	vcompresspd ymm0{k1},ymm0
   6:	62 f2 fd 29 8a c9    	vcompresspd ymm1{k1},ymm1
   c:	62 f2 fd 29 8a d2    	vcompresspd ymm2{k1},ymm2
  12:	62 f2 fd 29 8a db    	vcompresspd ymm3{k1},ymm3
  18:	62 f2 fd 29 8a e4    	vcompresspd ymm4{k1},ymm4
  1e:	62 f2 fd 29 8a ed    	vcompresspd ymm5{k1},ymm5
  24:	62 f2 fd 29 8a f6    	vcompresspd ymm6{k1},ymm6
  2a:	62 f2 fd 29 8a ff    	vcompresspd ymm7{k1},ymm7

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14];
VMOVUPD YMM3, [R14];
VMOVUPD YMM4, [R14];
VMOVUPD YMM5, [R14];
VMOVUPD YMM6, [R14];
VMOVUPD YMM7, [R14]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 16.01
- Reference cycles: 11.42
- UOPS_EXECUTED.THREAD: 17.0
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	62 f2 fd 29 8a c0    	vcompresspd ymm0{k1},ymm0
   6:	62 f2 fd 29 8a c9    	vcompresspd ymm1{k1},ymm1
   c:	62 f2 fd 29 8a d2    	vcompresspd ymm2{k1},ymm2
  12:	62 f2 fd 29 8a db    	vcompresspd ymm3{k1},ymm3
  18:	62 f2 fd 29 8a e4    	vcompresspd ymm4{k1},ymm4
  1e:	62 f2 fd 29 8a ed    	vcompresspd ymm5{k1},ymm5
  24:	62 f2 fd 29 8a f6    	vcompresspd ymm6{k1},ymm6
  2a:	62 f2 fd 29 8a ff    	vcompresspd ymm7{k1},ymm7

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14];
VMOVUPD YMM3, [R14];
VMOVUPD YMM4, [R14];
VMOVUPD YMM5, [R14];
VMOVUPD YMM6, [R14];
VMOVUPD YMM7, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 16.01
- Reference cycles: 11.41
- UOPS_EXECUTED.THREAD: 16.1
- RETIRE_SLOTS: 16.11
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f2 fd 29 8a c0    	vcompresspd ymm0{k1},ymm0
   6:	62 f2 fd 29 8a c9    	vcompresspd ymm1{k1},ymm1
   c:	62 f2 fd 29 8a d2    	vcompresspd ymm2{k1},ymm2
  12:	62 f2 fd 29 8a db    	vcompresspd ymm3{k1},ymm3
  18:	62 f2 fd 29 8a e4    	vcompresspd ymm4{k1},ymm4
  1e:	62 f2 fd 29 8a ed    	vcompresspd ymm5{k1},ymm5
  24:	62 f2 fd 29 8a f6    	vcompresspd ymm6{k1},ymm6
  2a:	62 f2 fd 29 8a ff    	vcompresspd ymm7{k1},ymm7
  30:	62 52 fd 29 8a c0    	vcompresspd ymm8{k1},ymm8
  36:	62 52 fd 29 8a c9    	vcompresspd ymm9{k1},ymm9
  3c:	62 52 fd 29 8a d2    	vcompresspd ymm10{k1},ymm10
  42:	62 52 fd 29 8a db    	vcompresspd ymm11{k1},ymm11
  48:	62 52 fd 29 8a e4    	vcompresspd ymm12{k1},ymm12
  4e:	62 a2 fd 29 8a c0    	vcompresspd ymm16{k1},ymm16
  54:	62 a2 fd 29 8a c9    	vcompresspd ymm17{k1},ymm17
  5a:	62 a2 fd 29 8a d2    	vcompresspd ymm18{k1},ymm18

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14];
VMOVUPD YMM3, [R14];
VMOVUPD YMM4, [R14];
VMOVUPD YMM5, [R14];
VMOVUPD YMM6, [R14];
VMOVUPD YMM7, [R14];
VMOVUPD YMM8, [R14];
VMOVUPD YMM9, [R14];
VMOVUPD YMM10, [R14];
VMOVUPD YMM11, [R14];
VMOVUPD YMM12, [R14];
VMOVUPD YMM16, [R14];
VMOVUPD YMM17, [R14];
VMOVUPD YMM18, [R14]

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 31.99
- Reference cycles: 23.15
- UOPS_EXECUTED.THREAD: 32.0
- RETIRE_SLOTS: 32.0
- UOPS_MITE: 32.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 32.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f2 fd 29 8a c0    	vcompresspd ymm0{k1},ymm0
   6:	62 f2 fd 29 8a c9    	vcompresspd ymm1{k1},ymm1
   c:	62 f2 fd 29 8a d2    	vcompresspd ymm2{k1},ymm2
  12:	62 f2 fd 29 8a db    	vcompresspd ymm3{k1},ymm3
  18:	62 f2 fd 29 8a e4    	vcompresspd ymm4{k1},ymm4
  1e:	62 f2 fd 29 8a ed    	vcompresspd ymm5{k1},ymm5
  24:	62 f2 fd 29 8a f6    	vcompresspd ymm6{k1},ymm6
  2a:	62 f2 fd 29 8a ff    	vcompresspd ymm7{k1},ymm7
  30:	62 52 fd 29 8a c0    	vcompresspd ymm8{k1},ymm8
  36:	62 52 fd 29 8a c9    	vcompresspd ymm9{k1},ymm9
  3c:	62 52 fd 29 8a d2    	vcompresspd ymm10{k1},ymm10
  42:	62 52 fd 29 8a db    	vcompresspd ymm11{k1},ymm11
  48:	62 52 fd 29 8a e4    	vcompresspd ymm12{k1},ymm12
  4e:	62 a2 fd 29 8a c0    	vcompresspd ymm16{k1},ymm16
  54:	62 a2 fd 29 8a c9    	vcompresspd ymm17{k1},ymm17
  5a:	62 a2 fd 29 8a d2    	vcompresspd ymm18{k1},ymm18

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14];
VMOVUPD YMM3, [R14];
VMOVUPD YMM4, [R14];
VMOVUPD YMM5, [R14];
VMOVUPD YMM6, [R14];
VMOVUPD YMM7, [R14];
VMOVUPD YMM8, [R14];
VMOVUPD YMM9, [R14];
VMOVUPD YMM10, [R14];
VMOVUPD YMM11, [R14];
VMOVUPD YMM12, [R14];
VMOVUPD YMM16, [R14];
VMOVUPD YMM17, [R14];
VMOVUPD YMM18, [R14]

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 32.01
- Reference cycles: 22.89
- UOPS_EXECUTED.THREAD: 33.0
- RETIRE_SLOTS: 33.01
- UOPS_MITE: 0.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 32.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With loop_count=100 and unroll_count=10

Code:

   0:	62 f2 fd 29 8a c0    	vcompresspd ymm0{k1},ymm0
   6:	62 f2 fd 29 8a c9    	vcompresspd ymm1{k1},ymm1
   c:	62 f2 fd 29 8a d2    	vcompresspd ymm2{k1},ymm2
  12:	62 f2 fd 29 8a db    	vcompresspd ymm3{k1},ymm3
  18:	62 f2 fd 29 8a e4    	vcompresspd ymm4{k1},ymm4
  1e:	62 f2 fd 29 8a ed    	vcompresspd ymm5{k1},ymm5
  24:	62 f2 fd 29 8a f6    	vcompresspd ymm6{k1},ymm6
  2a:	62 f2 fd 29 8a ff    	vcompresspd ymm7{k1},ymm7
  30:	62 52 fd 29 8a c0    	vcompresspd ymm8{k1},ymm8
  36:	62 52 fd 29 8a c9    	vcompresspd ymm9{k1},ymm9
  3c:	62 52 fd 29 8a d2    	vcompresspd ymm10{k1},ymm10
  42:	62 52 fd 29 8a db    	vcompresspd ymm11{k1},ymm11
  48:	62 52 fd 29 8a e4    	vcompresspd ymm12{k1},ymm12
  4e:	62 a2 fd 29 8a c0    	vcompresspd ymm16{k1},ymm16
  54:	62 a2 fd 29 8a c9    	vcompresspd ymm17{k1},ymm17
  5a:	62 a2 fd 29 8a d2    	vcompresspd ymm18{k1},ymm18

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14];
VMOVUPD YMM3, [R14];
VMOVUPD YMM4, [R14];
VMOVUPD YMM5, [R14];
VMOVUPD YMM6, [R14];
VMOVUPD YMM7, [R14];
VMOVUPD YMM8, [R14];
VMOVUPD YMM9, [R14];
VMOVUPD YMM10, [R14];
VMOVUPD YMM11, [R14];
VMOVUPD YMM12, [R14];
VMOVUPD YMM16, [R14];
VMOVUPD YMM17, [R14];
VMOVUPD YMM18, [R14]

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 32.01
- Reference cycles: 22.83
- UOPS_EXECUTED.THREAD: 32.1
- RETIRE_SLOTS: 32.1
- UOPS_MITE: 0.32
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 32.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.16

VCOMPRESSPD (YMM, K, YMM) - Throughput and Uops

With different registers for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With unroll_count=500, no inner loop, and 4 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With the same register for for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With unroll_count=500, no inner loop, and 4 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10